143e3346eSAndrew Jeffery /* 2ff90606fSCédric Le Goater * ASPEED SoC family 343e3346eSAndrew Jeffery * 443e3346eSAndrew Jeffery * Andrew Jeffery <andrew@aj.id.au> 543e3346eSAndrew Jeffery * 643e3346eSAndrew Jeffery * Copyright 2016 IBM Corp. 743e3346eSAndrew Jeffery * 843e3346eSAndrew Jeffery * This code is licensed under the GPL version 2 or later. See 943e3346eSAndrew Jeffery * the COPYING file in the top-level directory. 1043e3346eSAndrew Jeffery */ 1143e3346eSAndrew Jeffery 12ff90606fSCédric Le Goater #ifndef ASPEED_SOC_H 13ff90606fSCédric Le Goater #define ASPEED_SOC_H 1443e3346eSAndrew Jeffery 1543e3346eSAndrew Jeffery #include "hw/intc/aspeed_vic.h" 16334973bbSAndrew Jeffery #include "hw/misc/aspeed_scu.h" 17c2da8a8bSCédric Le Goater #include "hw/misc/aspeed_sdmc.h" 18118c82e7SEddie James #include "hw/misc/aspeed_xdma.h" 1943e3346eSAndrew Jeffery #include "hw/timer/aspeed_timer.h" 2075fb4577SJoel Stanley #include "hw/timer/aspeed_rtc.h" 2116020011SCédric Le Goater #include "hw/i2c/aspeed_i2c.h" 227c1c69bcSCédric Le Goater #include "hw/ssi/aspeed_smc.h" 23013befe1SCédric Le Goater #include "hw/watchdog/wdt_aspeed.h" 24ea337c65SCédric Le Goater #include "hw/net/ftgmac100.h" 25ec150c7eSMarkus Armbruster #include "target/arm/cpu.h" 26fdcc7c06SRashmica Gupta #include "hw/gpio/aspeed_gpio.h" 272bea128cSEddie James #include "hw/sd/aspeed_sdhci.h" 2843e3346eSAndrew Jeffery 29dbcabeebSCédric Le Goater #define ASPEED_SPIS_NUM 2 30*6b2b2a70SJoel Stanley #define ASPEED_WDTS_NUM 4 31ece09beeSCédric Le Goater #define ASPEED_CPUS_NUM 2 3267340990SCédric Le Goater #define ASPEED_MACS_NUM 2 33dbcabeebSCédric Le Goater 34ff90606fSCédric Le Goater typedef struct AspeedSoCState { 3543e3346eSAndrew Jeffery /*< private >*/ 3643e3346eSAndrew Jeffery DeviceState parent; 3743e3346eSAndrew Jeffery 3843e3346eSAndrew Jeffery /*< public >*/ 39ece09beeSCédric Le Goater ARMCPU cpu[ASPEED_CPUS_NUM]; 40ece09beeSCédric Le Goater uint32_t num_cpus; 4174af4eecSCédric Le Goater MemoryRegion sram; 4243e3346eSAndrew Jeffery AspeedVICState vic; 4375fb4577SJoel Stanley AspeedRtcState rtc; 4443e3346eSAndrew Jeffery AspeedTimerCtrlState timerctrl; 4516020011SCédric Le Goater AspeedI2CState i2c; 46334973bbSAndrew Jeffery AspeedSCUState scu; 47118c82e7SEddie James AspeedXDMAState xdma; 480e5803dfSCédric Le Goater AspeedSMCState fmc; 49dbcabeebSCédric Le Goater AspeedSMCState spi[ASPEED_SPIS_NUM]; 50c2da8a8bSCédric Le Goater AspeedSDMCState sdmc; 51f986ee1dSJoel Stanley AspeedWDTState wdt[ASPEED_WDTS_NUM]; 5267340990SCédric Le Goater FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; 53fdcc7c06SRashmica Gupta AspeedGPIOState gpio; 542bea128cSEddie James AspeedSDHCIState sdhci; 55ff90606fSCédric Le Goater } AspeedSoCState; 5643e3346eSAndrew Jeffery 57ff90606fSCédric Le Goater #define TYPE_ASPEED_SOC "aspeed-soc" 58ff90606fSCédric Le Goater #define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC) 5943e3346eSAndrew Jeffery 60b033271fSCédric Le Goater typedef struct AspeedSoCInfo { 61b033271fSCédric Le Goater const char *name; 62ba1ba5ccSIgor Mammedov const char *cpu_type; 63b033271fSCédric Le Goater uint32_t silicon_rev; 6474af4eecSCédric Le Goater uint64_t sram_size; 65dbcabeebSCédric Le Goater int spis_num; 66f986ee1dSJoel Stanley int wdts_num; 67b456b113SCédric Le Goater const int *irqmap; 68d783d1feSCédric Le Goater const hwaddr *memmap; 69ece09beeSCédric Le Goater uint32_t num_cpus; 70b033271fSCédric Le Goater } AspeedSoCInfo; 71b033271fSCédric Le Goater 72b033271fSCédric Le Goater typedef struct AspeedSoCClass { 73b033271fSCédric Le Goater DeviceClass parent_class; 74b033271fSCédric Le Goater AspeedSoCInfo *info; 75b033271fSCédric Le Goater } AspeedSoCClass; 76b033271fSCédric Le Goater 77b033271fSCédric Le Goater #define ASPEED_SOC_CLASS(klass) \ 78b033271fSCédric Le Goater OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC) 79b033271fSCédric Le Goater #define ASPEED_SOC_GET_CLASS(obj) \ 80b033271fSCédric Le Goater OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC) 8143e3346eSAndrew Jeffery 82b456b113SCédric Le Goater enum { 83b456b113SCédric Le Goater ASPEED_IOMEM, 84b456b113SCédric Le Goater ASPEED_UART1, 85b456b113SCédric Le Goater ASPEED_UART2, 86b456b113SCédric Le Goater ASPEED_UART3, 87b456b113SCédric Le Goater ASPEED_UART4, 88b456b113SCédric Le Goater ASPEED_UART5, 89b456b113SCédric Le Goater ASPEED_VUART, 90b456b113SCédric Le Goater ASPEED_FMC, 91b456b113SCédric Le Goater ASPEED_SPI1, 92b456b113SCédric Le Goater ASPEED_SPI2, 93b456b113SCédric Le Goater ASPEED_VIC, 94b456b113SCédric Le Goater ASPEED_SDMC, 95b456b113SCédric Le Goater ASPEED_SCU, 96b456b113SCédric Le Goater ASPEED_ADC, 97b456b113SCédric Le Goater ASPEED_SRAM, 982bea128cSEddie James ASPEED_SDHCI, 99b456b113SCédric Le Goater ASPEED_GPIO, 100b456b113SCédric Le Goater ASPEED_RTC, 101b456b113SCédric Le Goater ASPEED_TIMER1, 102b456b113SCédric Le Goater ASPEED_TIMER2, 103b456b113SCédric Le Goater ASPEED_TIMER3, 104b456b113SCédric Le Goater ASPEED_TIMER4, 105b456b113SCédric Le Goater ASPEED_TIMER5, 106b456b113SCédric Le Goater ASPEED_TIMER6, 107b456b113SCédric Le Goater ASPEED_TIMER7, 108b456b113SCédric Le Goater ASPEED_TIMER8, 109b456b113SCédric Le Goater ASPEED_WDT, 110b456b113SCédric Le Goater ASPEED_PWM, 111b456b113SCédric Le Goater ASPEED_LPC, 112b456b113SCédric Le Goater ASPEED_IBT, 113b456b113SCédric Le Goater ASPEED_I2C, 114b456b113SCédric Le Goater ASPEED_ETH1, 115b456b113SCédric Le Goater ASPEED_ETH2, 116d783d1feSCédric Le Goater ASPEED_SDRAM, 117118c82e7SEddie James ASPEED_XDMA, 118b456b113SCédric Le Goater }; 119b456b113SCédric Le Goater 120ff90606fSCédric Le Goater #endif /* ASPEED_SOC_H */ 121