1 /* 2 * ARM SSE (Subsystems for Embedded): IoTKit 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* 13 * This is a model of the Arm "Subsystems for Embedded" family of 14 * hardware, which include the IoT Kit and the SSE-050, SSE-100 and 15 * SSE-200. Currently we model only the Arm IoT Kit which is documented in 16 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html 17 * It contains: 18 * a Cortex-M33 19 * the IDAU 20 * some timers and watchdogs 21 * two peripheral protection controllers 22 * a memory protection controller 23 * a security controller 24 * a bus fabric which arranges that some parts of the address 25 * space are secure and non-secure aliases of each other 26 * 27 * QEMU interface: 28 * + QOM property "memory" is a MemoryRegion containing the devices provided 29 * by the board model. 30 * + QOM property "MAINCLK" is the frequency of the main system clock 31 * + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts. 32 * (In hardware, the SSE-200 permits the number of expansion interrupts 33 * for the two CPUs to be configured separately, but we restrict it to 34 * being the same for both, to avoid having to have separate Property 35 * lists for different variants. This restriction can be relaxed later 36 * if necessary.) 37 * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0, 38 * which are wired to its NVIC lines 32 .. n+32 39 * + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for 40 * CPU 1, which are wired to its NVIC lines 32 .. n+32 41 * + sysbus MMIO region 0 is the "AHB Slave Expansion" which allows 42 * bus master devices in the board model to make transactions into 43 * all the devices and memory areas in the IoTKit 44 * Controlling up to 4 AHB expansion PPBs which a system using the IoTKit 45 * might provide: 46 * + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15] 47 * + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15] 48 * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable 49 * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear 50 * + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status 51 * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit 52 * might provide: 53 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15] 54 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15] 55 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable 56 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear 57 * + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status 58 * Controlling each of the 16 expansion MPCs which a system using the IoTKit 59 * might provide: 60 * + named GPIO inputs mpcexp_status[0..15] 61 * Controlling each of the 16 expansion MSCs which a system using the IoTKit 62 * might provide: 63 * + named GPIO inputs mscexp_status[0..15] 64 * + named GPIO outputs mscexp_clear[0..15] 65 * + named GPIO outputs mscexp_ns[0..15] 66 */ 67 68 #ifndef ARMSSE_H 69 #define ARMSSE_H 70 71 #include "hw/sysbus.h" 72 #include "hw/arm/armv7m.h" 73 #include "hw/misc/iotkit-secctl.h" 74 #include "hw/misc/tz-ppc.h" 75 #include "hw/misc/tz-mpc.h" 76 #include "hw/timer/cmsdk-apb-timer.h" 77 #include "hw/timer/cmsdk-apb-dualtimer.h" 78 #include "hw/watchdog/cmsdk-apb-watchdog.h" 79 #include "hw/misc/iotkit-sysctl.h" 80 #include "hw/misc/iotkit-sysinfo.h" 81 #include "hw/or-irq.h" 82 #include "hw/core/split-irq.h" 83 84 #define TYPE_ARMSSE "arm-sse" 85 #define ARMSSE(obj) OBJECT_CHECK(ARMSSE, (obj), TYPE_ARMSSE) 86 87 /* 88 * These type names are for specific IoTKit subsystems; other than 89 * instantiating them, code using these devices should always handle 90 * them via the ARMSSE base class, so they have no IOTKIT() etc macros. 91 */ 92 #define TYPE_IOTKIT "iotkit" 93 94 /* We have an IRQ splitter and an OR gate input for each external PPC 95 * and the 2 internal PPCs 96 */ 97 #define NUM_EXTERNAL_PPCS (IOTS_NUM_AHB_EXP_PPC + IOTS_NUM_APB_EXP_PPC) 98 #define NUM_PPCS (NUM_EXTERNAL_PPCS + 2) 99 100 #define MAX_SRAM_BANKS 4 101 #if MAX_SRAM_BANKS > IOTS_NUM_MPC 102 #error Too many SRAM banks 103 #endif 104 105 #define SSE_MAX_CPUS 2 106 107 typedef struct ARMSSE { 108 /*< private >*/ 109 SysBusDevice parent_obj; 110 111 /*< public >*/ 112 ARMv7MState armv7m[SSE_MAX_CPUS]; 113 IoTKitSecCtl secctl; 114 TZPPC apb_ppc0; 115 TZPPC apb_ppc1; 116 TZMPC mpc[IOTS_NUM_MPC]; 117 CMSDKAPBTIMER timer0; 118 CMSDKAPBTIMER timer1; 119 CMSDKAPBTIMER s32ktimer; 120 qemu_or_irq ppc_irq_orgate; 121 SplitIRQ sec_resp_splitter; 122 SplitIRQ ppc_irq_splitter[NUM_PPCS]; 123 SplitIRQ mpc_irq_splitter[IOTS_NUM_EXP_MPC + IOTS_NUM_MPC]; 124 qemu_or_irq mpc_irq_orgate; 125 qemu_or_irq nmi_orgate; 126 127 SplitIRQ cpu_irq_splitter[32]; 128 129 CMSDKAPBDualTimer dualtimer; 130 131 CMSDKAPBWatchdog s32kwatchdog; 132 CMSDKAPBWatchdog nswatchdog; 133 CMSDKAPBWatchdog swatchdog; 134 135 IoTKitSysCtl sysctl; 136 IoTKitSysCtl sysinfo; 137 138 MemoryRegion container; 139 MemoryRegion alias1; 140 MemoryRegion alias2; 141 MemoryRegion alias3; 142 MemoryRegion sram[MAX_SRAM_BANKS]; 143 144 qemu_irq *exp_irqs[SSE_MAX_CPUS]; 145 qemu_irq ppc0_irq; 146 qemu_irq ppc1_irq; 147 qemu_irq sec_resp_cfg; 148 qemu_irq sec_resp_cfg_in; 149 qemu_irq nsc_cfg_in; 150 151 qemu_irq irq_status_in[NUM_EXTERNAL_PPCS]; 152 qemu_irq mpcexp_status_in[IOTS_NUM_EXP_MPC]; 153 154 uint32_t nsccfg; 155 156 /* Properties */ 157 MemoryRegion *board_memory; 158 uint32_t exp_numirq; 159 uint32_t mainclk_frq; 160 uint32_t sram_addr_width; 161 } ARMSSE; 162 163 typedef struct ARMSSEInfo ARMSSEInfo; 164 165 typedef struct ARMSSEClass { 166 DeviceClass parent_class; 167 const ARMSSEInfo *info; 168 } ARMSSEClass; 169 170 #define ARMSSE_CLASS(klass) \ 171 OBJECT_CLASS_CHECK(ARMSSEClass, (klass), TYPE_ARMSSE) 172 #define ARMSSE_GET_CLASS(obj) \ 173 OBJECT_GET_CLASS(ARMSSEClass, (obj), TYPE_ARMSSE) 174 175 #endif 176