1 /* 2 * ARM SSE (Subsystems for Embedded): IoTKit 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* 13 * This is a model of the Arm "Subsystems for Embedded" family of 14 * hardware, which include the IoT Kit and the SSE-050, SSE-100 and 15 * SSE-200. Currently we model only the Arm IoT Kit which is documented in 16 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html 17 * It contains: 18 * a Cortex-M33 19 * the IDAU 20 * some timers and watchdogs 21 * two peripheral protection controllers 22 * a memory protection controller 23 * a security controller 24 * a bus fabric which arranges that some parts of the address 25 * space are secure and non-secure aliases of each other 26 * 27 * QEMU interface: 28 * + QOM property "memory" is a MemoryRegion containing the devices provided 29 * by the board model. 30 * + QOM property "MAINCLK" is the frequency of the main system clock 31 * + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts 32 * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts, which 33 * are wired to the NVIC lines 32 .. n+32 34 * + sysbus MMIO region 0 is the "AHB Slave Expansion" which allows 35 * bus master devices in the board model to make transactions into 36 * all the devices and memory areas in the IoTKit 37 * Controlling up to 4 AHB expansion PPBs which a system using the IoTKit 38 * might provide: 39 * + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15] 40 * + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15] 41 * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable 42 * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear 43 * + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status 44 * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit 45 * might provide: 46 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15] 47 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15] 48 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable 49 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear 50 * + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status 51 * Controlling each of the 16 expansion MPCs which a system using the IoTKit 52 * might provide: 53 * + named GPIO inputs mpcexp_status[0..15] 54 * Controlling each of the 16 expansion MSCs which a system using the IoTKit 55 * might provide: 56 * + named GPIO inputs mscexp_status[0..15] 57 * + named GPIO outputs mscexp_clear[0..15] 58 * + named GPIO outputs mscexp_ns[0..15] 59 */ 60 61 #ifndef ARMSSE_H 62 #define ARMSSE_H 63 64 #include "hw/sysbus.h" 65 #include "hw/arm/armv7m.h" 66 #include "hw/misc/iotkit-secctl.h" 67 #include "hw/misc/tz-ppc.h" 68 #include "hw/misc/tz-mpc.h" 69 #include "hw/timer/cmsdk-apb-timer.h" 70 #include "hw/timer/cmsdk-apb-dualtimer.h" 71 #include "hw/watchdog/cmsdk-apb-watchdog.h" 72 #include "hw/misc/iotkit-sysctl.h" 73 #include "hw/misc/iotkit-sysinfo.h" 74 #include "hw/or-irq.h" 75 #include "hw/core/split-irq.h" 76 77 #define TYPE_ARMSSE "arm-sse" 78 #define ARMSSE(obj) OBJECT_CHECK(ARMSSE, (obj), TYPE_ARMSSE) 79 80 /* 81 * These type names are for specific IoTKit subsystems; other than 82 * instantiating them, code using these devices should always handle 83 * them via the ARMSSE base class, so they have no IOTKIT() etc macros. 84 */ 85 #define TYPE_IOTKIT "iotkit" 86 87 /* We have an IRQ splitter and an OR gate input for each external PPC 88 * and the 2 internal PPCs 89 */ 90 #define NUM_EXTERNAL_PPCS (IOTS_NUM_AHB_EXP_PPC + IOTS_NUM_APB_EXP_PPC) 91 #define NUM_PPCS (NUM_EXTERNAL_PPCS + 2) 92 93 #define MAX_SRAM_BANKS 4 94 #if MAX_SRAM_BANKS > IOTS_NUM_MPC 95 #error Too many SRAM banks 96 #endif 97 98 typedef struct ARMSSE { 99 /*< private >*/ 100 SysBusDevice parent_obj; 101 102 /*< public >*/ 103 ARMv7MState armv7m; 104 IoTKitSecCtl secctl; 105 TZPPC apb_ppc0; 106 TZPPC apb_ppc1; 107 TZMPC mpc[IOTS_NUM_MPC]; 108 CMSDKAPBTIMER timer0; 109 CMSDKAPBTIMER timer1; 110 CMSDKAPBTIMER s32ktimer; 111 qemu_or_irq ppc_irq_orgate; 112 SplitIRQ sec_resp_splitter; 113 SplitIRQ ppc_irq_splitter[NUM_PPCS]; 114 SplitIRQ mpc_irq_splitter[IOTS_NUM_EXP_MPC + IOTS_NUM_MPC]; 115 qemu_or_irq mpc_irq_orgate; 116 qemu_or_irq nmi_orgate; 117 118 CMSDKAPBDualTimer dualtimer; 119 120 CMSDKAPBWatchdog s32kwatchdog; 121 CMSDKAPBWatchdog nswatchdog; 122 CMSDKAPBWatchdog swatchdog; 123 124 IoTKitSysCtl sysctl; 125 IoTKitSysCtl sysinfo; 126 127 MemoryRegion container; 128 MemoryRegion alias1; 129 MemoryRegion alias2; 130 MemoryRegion alias3; 131 MemoryRegion sram[MAX_SRAM_BANKS]; 132 133 qemu_irq *exp_irqs; 134 qemu_irq ppc0_irq; 135 qemu_irq ppc1_irq; 136 qemu_irq sec_resp_cfg; 137 qemu_irq sec_resp_cfg_in; 138 qemu_irq nsc_cfg_in; 139 140 qemu_irq irq_status_in[NUM_EXTERNAL_PPCS]; 141 qemu_irq mpcexp_status_in[IOTS_NUM_EXP_MPC]; 142 143 uint32_t nsccfg; 144 145 /* Properties */ 146 MemoryRegion *board_memory; 147 uint32_t exp_numirq; 148 uint32_t mainclk_frq; 149 uint32_t sram_addr_width; 150 } ARMSSE; 151 152 typedef struct ARMSSEInfo ARMSSEInfo; 153 154 typedef struct ARMSSEClass { 155 DeviceClass parent_class; 156 const ARMSSEInfo *info; 157 } ARMSSEClass; 158 159 #define ARMSSE_CLASS(klass) \ 160 OBJECT_CLASS_CHECK(ARMSSEClass, (klass), TYPE_ARMSSE) 161 #define ARMSSE_GET_CLASS(obj) \ 162 OBJECT_GET_CLASS(ARMSSEClass, (obj), TYPE_ARMSSE) 163 164 #endif 165