1 /* 2 * ARM IoT Kit 3 * 4 * Copyright (c) 2018 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 /* This is a model of the Arm IoT Kit which is documented in 13 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html 14 * It contains: 15 * a Cortex-M33 16 * the IDAU 17 * some timers and watchdogs 18 * two peripheral protection controllers 19 * a memory protection controller 20 * a security controller 21 * a bus fabric which arranges that some parts of the address 22 * space are secure and non-secure aliases of each other 23 * 24 * QEMU interface: 25 * + QOM property "memory" is a MemoryRegion containing the devices provided 26 * by the board model. 27 * + QOM property "MAINCLK" is the frequency of the main system clock 28 * + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts 29 * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts, which 30 * are wired to the NVIC lines 32 .. n+32 31 * Controlling up to 4 AHB expansion PPBs which a system using the IoTKit 32 * might provide: 33 * + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15] 34 * + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15] 35 * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable 36 * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear 37 * + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status 38 * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit 39 * might provide: 40 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15] 41 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15] 42 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable 43 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear 44 * + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status 45 * Controlling each of the 16 expansion MPCs which a system using the IoTKit 46 * might provide: 47 * + named GPIO inputs mpcexp_status[0..15] 48 */ 49 50 #ifndef IOTKIT_H 51 #define IOTKIT_H 52 53 #include "hw/sysbus.h" 54 #include "hw/arm/armv7m.h" 55 #include "hw/misc/iotkit-secctl.h" 56 #include "hw/misc/tz-ppc.h" 57 #include "hw/misc/tz-mpc.h" 58 #include "hw/timer/cmsdk-apb-timer.h" 59 #include "hw/timer/cmsdk-apb-dualtimer.h" 60 #include "hw/misc/unimp.h" 61 #include "hw/or-irq.h" 62 #include "hw/core/split-irq.h" 63 64 #define TYPE_IOTKIT "iotkit" 65 #define IOTKIT(obj) OBJECT_CHECK(IoTKit, (obj), TYPE_IOTKIT) 66 67 /* We have an IRQ splitter and an OR gate input for each external PPC 68 * and the 2 internal PPCs 69 */ 70 #define NUM_EXTERNAL_PPCS (IOTS_NUM_AHB_EXP_PPC + IOTS_NUM_APB_EXP_PPC) 71 #define NUM_PPCS (NUM_EXTERNAL_PPCS + 2) 72 73 typedef struct IoTKit { 74 /*< private >*/ 75 SysBusDevice parent_obj; 76 77 /*< public >*/ 78 ARMv7MState armv7m; 79 IoTKitSecCtl secctl; 80 TZPPC apb_ppc0; 81 TZPPC apb_ppc1; 82 TZMPC mpc; 83 CMSDKAPBTIMER timer0; 84 CMSDKAPBTIMER timer1; 85 qemu_or_irq ppc_irq_orgate; 86 SplitIRQ sec_resp_splitter; 87 SplitIRQ ppc_irq_splitter[NUM_PPCS]; 88 SplitIRQ mpc_irq_splitter[IOTS_NUM_EXP_MPC + IOTS_NUM_MPC]; 89 qemu_or_irq mpc_irq_orgate; 90 91 CMSDKAPBDualTimer dualtimer; 92 UnimplementedDeviceState s32ktimer; 93 94 MemoryRegion container; 95 MemoryRegion alias1; 96 MemoryRegion alias2; 97 MemoryRegion alias3; 98 MemoryRegion sram0; 99 100 qemu_irq *exp_irqs; 101 qemu_irq ppc0_irq; 102 qemu_irq ppc1_irq; 103 qemu_irq sec_resp_cfg; 104 qemu_irq sec_resp_cfg_in; 105 qemu_irq nsc_cfg_in; 106 107 qemu_irq irq_status_in[NUM_EXTERNAL_PPCS]; 108 qemu_irq mpcexp_status_in[IOTS_NUM_EXP_MPC]; 109 110 uint32_t nsccfg; 111 112 /* Properties */ 113 MemoryRegion *board_memory; 114 uint32_t exp_numirq; 115 uint32_t mainclk_frq; 116 } IoTKit; 117 118 #endif 119