xref: /qemu/include/exec/translator.h (revision b3f05b8ce24a2dae2e37bd6e7910f19652848656)
177fc6f5eSLluís Vilanova /*
277fc6f5eSLluís Vilanova  * Generic intermediate code generation.
377fc6f5eSLluís Vilanova  *
477fc6f5eSLluís Vilanova  * Copyright (C) 2016-2017 Lluís Vilanova <vilanova@ac.upc.edu>
577fc6f5eSLluís Vilanova  *
677fc6f5eSLluís Vilanova  * This work is licensed under the terms of the GNU GPL, version 2 or later.
777fc6f5eSLluís Vilanova  * See the COPYING file in the top-level directory.
877fc6f5eSLluís Vilanova  */
977fc6f5eSLluís Vilanova 
1077fc6f5eSLluís Vilanova #ifndef EXEC__TRANSLATOR_H
1177fc6f5eSLluís Vilanova #define EXEC__TRANSLATOR_H
1277fc6f5eSLluís Vilanova 
13bb2e0039SLluís Vilanova /*
14bb2e0039SLluís Vilanova  * Include this header from a target-specific file, and add a
15bb2e0039SLluís Vilanova  *
16bb2e0039SLluís Vilanova  *     DisasContextBase base;
17bb2e0039SLluís Vilanova  *
18bb2e0039SLluís Vilanova  * member in your target-specific DisasContext.
19bb2e0039SLluís Vilanova  */
20bb2e0039SLluís Vilanova 
21409c1a0bSEmilio G. Cota #include "qemu/bswap.h"
2280189472SRichard Henderson #include "exec/vaddr.h"
23bb2e0039SLluís Vilanova 
24306c8721SRichard Henderson /**
25306c8721SRichard Henderson  * gen_intermediate_code
26306c8721SRichard Henderson  * @cpu: cpu context
27306c8721SRichard Henderson  * @tb: translation block
28306c8721SRichard Henderson  * @max_insns: max number of instructions to translate
29306c8721SRichard Henderson  * @pc: guest virtual program counter address
30306c8721SRichard Henderson  * @host_pc: host physical program counter address
31306c8721SRichard Henderson  *
32306c8721SRichard Henderson  * This function must be provided by the target, which should create
33306c8721SRichard Henderson  * the target-specific DisasContext, and then invoke translator_loop.
34306c8721SRichard Henderson  */
35597f9b2dSRichard Henderson void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
3632f0c394SAnton Johansson                            vaddr pc, void *host_pc);
37bb2e0039SLluís Vilanova 
3877fc6f5eSLluís Vilanova /**
3977fc6f5eSLluís Vilanova  * DisasJumpType:
4077fc6f5eSLluís Vilanova  * @DISAS_NEXT: Next instruction in program order.
4177fc6f5eSLluís Vilanova  * @DISAS_TOO_MANY: Too many instructions translated.
4277fc6f5eSLluís Vilanova  * @DISAS_NORETURN: Following code is dead.
4377fc6f5eSLluís Vilanova  * @DISAS_TARGET_*: Start of target-specific conditions.
4477fc6f5eSLluís Vilanova  *
4577fc6f5eSLluís Vilanova  * What instruction to disassemble next.
4677fc6f5eSLluís Vilanova  */
4777fc6f5eSLluís Vilanova typedef enum DisasJumpType {
4877fc6f5eSLluís Vilanova     DISAS_NEXT,
4977fc6f5eSLluís Vilanova     DISAS_TOO_MANY,
5077fc6f5eSLluís Vilanova     DISAS_NORETURN,
5177fc6f5eSLluís Vilanova     DISAS_TARGET_0,
5277fc6f5eSLluís Vilanova     DISAS_TARGET_1,
5377fc6f5eSLluís Vilanova     DISAS_TARGET_2,
5477fc6f5eSLluís Vilanova     DISAS_TARGET_3,
5577fc6f5eSLluís Vilanova     DISAS_TARGET_4,
5677fc6f5eSLluís Vilanova     DISAS_TARGET_5,
5777fc6f5eSLluís Vilanova     DISAS_TARGET_6,
5877fc6f5eSLluís Vilanova     DISAS_TARGET_7,
5977fc6f5eSLluís Vilanova     DISAS_TARGET_8,
6077fc6f5eSLluís Vilanova     DISAS_TARGET_9,
6177fc6f5eSLluís Vilanova     DISAS_TARGET_10,
6277fc6f5eSLluís Vilanova     DISAS_TARGET_11,
6377fc6f5eSLluís Vilanova } DisasJumpType;
6477fc6f5eSLluís Vilanova 
65bb2e0039SLluís Vilanova /**
66bb2e0039SLluís Vilanova  * DisasContextBase:
67bb2e0039SLluís Vilanova  * @tb: Translation block for this disassembly.
68bb2e0039SLluís Vilanova  * @pc_first: Address of first guest instruction in this TB.
69bb2e0039SLluís Vilanova  * @pc_next: Address of next guest instruction in this TB (current during
70bb2e0039SLluís Vilanova  *           disassembly).
71bb2e0039SLluís Vilanova  * @is_jmp: What instruction to disassemble next.
72bb2e0039SLluís Vilanova  * @num_insns: Number of translated instructions (including current).
73b542683dSEmilio G. Cota  * @max_insns: Maximum number of instructions to be translated in this TB.
74bb2e0039SLluís Vilanova  * @singlestep_enabled: "Hardware" single stepping enabled.
7528a4f0baSRichard Henderson  * @plugin_enabled: TCG plugin enabled in this TB.
76*b3f05b8cSRichard Henderson  * @fake_insn: True if translator_fake_ldb used.
77e7face70SRichard Henderson  * @insn_start: The last op emitted by the insn_start hook,
78e7face70SRichard Henderson  *              which is expected to be INDEX_op_insn_start.
79bb2e0039SLluís Vilanova  *
80bb2e0039SLluís Vilanova  * Architecture-agnostic disassembly context.
81bb2e0039SLluís Vilanova  */
82bb2e0039SLluís Vilanova typedef struct DisasContextBase {
8350627f1bSRichard Henderson     TranslationBlock *tb;
8485c19af6SAnton Johansson     vaddr pc_first;
8585c19af6SAnton Johansson     vaddr pc_next;
86bb2e0039SLluís Vilanova     DisasJumpType is_jmp;
87b542683dSEmilio G. Cota     int num_insns;
88b542683dSEmilio G. Cota     int max_insns;
89bb2e0039SLluís Vilanova     bool singlestep_enabled;
9028a4f0baSRichard Henderson     bool plugin_enabled;
91*b3f05b8cSRichard Henderson     bool fake_insn;
92e7face70SRichard Henderson     struct TCGOp *insn_start;
9350627f1bSRichard Henderson     void *host_addr[2];
94ba3fb2a7SRichard Henderson 
95ba3fb2a7SRichard Henderson     /*
96ba3fb2a7SRichard Henderson      * Record insn data that we cannot read directly from host memory.
97ba3fb2a7SRichard Henderson      * There are only two reasons we cannot use host memory:
98ba3fb2a7SRichard Henderson      * (1) We are executing from I/O,
99ba3fb2a7SRichard Henderson      * (2) We are executing a synthetic instruction (s390x EX).
100ba3fb2a7SRichard Henderson      * In both cases we need record exactly one instruction,
101ba3fb2a7SRichard Henderson      * and thus the maximum amount of data we record is limited.
102ba3fb2a7SRichard Henderson      */
103ba3fb2a7SRichard Henderson     int record_start;
104ba3fb2a7SRichard Henderson     int record_len;
105ba3fb2a7SRichard Henderson     uint8_t record[32];
106bb2e0039SLluís Vilanova } DisasContextBase;
107bb2e0039SLluís Vilanova 
108bb2e0039SLluís Vilanova /**
109bb2e0039SLluís Vilanova  * TranslatorOps:
110bb2e0039SLluís Vilanova  * @init_disas_context:
111bb2e0039SLluís Vilanova  *      Initialize the target-specific portions of DisasContext struct.
112bb2e0039SLluís Vilanova  *      The generic DisasContextBase has already been initialized.
113bb2e0039SLluís Vilanova  *
114bb2e0039SLluís Vilanova  * @tb_start:
115bb2e0039SLluís Vilanova  *      Emit any code required before the start of the main loop,
116bb2e0039SLluís Vilanova  *      after the generic gen_tb_start().
117bb2e0039SLluís Vilanova  *
118bb2e0039SLluís Vilanova  * @insn_start:
119bb2e0039SLluís Vilanova  *      Emit the tcg_gen_insn_start opcode.
120bb2e0039SLluís Vilanova  *
121bb2e0039SLluís Vilanova  * @translate_insn:
122bb2e0039SLluís Vilanova  *      Disassemble one instruction and set db->pc_next for the start
123bb2e0039SLluís Vilanova  *      of the following instruction.  Set db->is_jmp as necessary to
124bb2e0039SLluís Vilanova  *      terminate the main loop.
125bb2e0039SLluís Vilanova  *
126bb2e0039SLluís Vilanova  * @tb_stop:
127bb2e0039SLluís Vilanova  *      Emit any opcodes required to exit the TB, based on db->is_jmp.
128bb2e0039SLluís Vilanova  *
129bb2e0039SLluís Vilanova  * @disas_log:
130bb2e0039SLluís Vilanova  *      Print instruction disassembly to log.
131bb2e0039SLluís Vilanova  */
132bb2e0039SLluís Vilanova typedef struct TranslatorOps {
133b542683dSEmilio G. Cota     void (*init_disas_context)(DisasContextBase *db, CPUState *cpu);
134bb2e0039SLluís Vilanova     void (*tb_start)(DisasContextBase *db, CPUState *cpu);
135bb2e0039SLluís Vilanova     void (*insn_start)(DisasContextBase *db, CPUState *cpu);
136bb2e0039SLluís Vilanova     void (*translate_insn)(DisasContextBase *db, CPUState *cpu);
137bb2e0039SLluís Vilanova     void (*tb_stop)(DisasContextBase *db, CPUState *cpu);
1388eb806a7SRichard Henderson     void (*disas_log)(const DisasContextBase *db, CPUState *cpu, FILE *f);
139bb2e0039SLluís Vilanova } TranslatorOps;
140bb2e0039SLluís Vilanova 
141bb2e0039SLluís Vilanova /**
142bb2e0039SLluís Vilanova  * translator_loop:
143bb2e0039SLluís Vilanova  * @cpu: Target vCPU.
144bb2e0039SLluís Vilanova  * @tb: Translation block.
1458b86d6d2SRichard Henderson  * @max_insns: Maximum number of insns to translate.
146306c8721SRichard Henderson  * @pc: guest virtual program counter address
147306c8721SRichard Henderson  * @host_pc: host physical program counter address
148306c8721SRichard Henderson  * @ops: Target-specific operations.
149306c8721SRichard Henderson  * @db: Disassembly context.
150bb2e0039SLluís Vilanova  *
151bb2e0039SLluís Vilanova  * Generic translator loop.
152bb2e0039SLluís Vilanova  *
153bb2e0039SLluís Vilanova  * Translation will stop in the following cases (in order):
154bb2e0039SLluís Vilanova  * - When is_jmp set by #TranslatorOps::breakpoint_check.
155bb2e0039SLluís Vilanova  *   - set to DISAS_TOO_MANY exits after translating one more insn
156bb2e0039SLluís Vilanova  *   - set to any other value than DISAS_NEXT exits immediately.
157bb2e0039SLluís Vilanova  * - When is_jmp set by #TranslatorOps::translate_insn.
158bb2e0039SLluís Vilanova  *   - set to any value other than DISAS_NEXT exits immediately.
159bb2e0039SLluís Vilanova  * - When the TCG operation buffer is full.
160bb2e0039SLluís Vilanova  * - When single-stepping is enabled (system-wide or on the current vCPU).
161bb2e0039SLluís Vilanova  * - When too many instructions have been translated.
162bb2e0039SLluís Vilanova  */
163597f9b2dSRichard Henderson void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns,
164b1c09220SAnton Johansson                      vaddr pc, void *host_pc, const TranslatorOps *ops,
165b1c09220SAnton Johansson                      DisasContextBase *db);
166bb2e0039SLluís Vilanova 
167d3a2a1d8SRichard Henderson /**
168d3a2a1d8SRichard Henderson  * translator_use_goto_tb
169d3a2a1d8SRichard Henderson  * @db: Disassembly context
170d3a2a1d8SRichard Henderson  * @dest: target pc of the goto
171d3a2a1d8SRichard Henderson  *
172d3a2a1d8SRichard Henderson  * Return true if goto_tb is allowed between the current TB
173d3a2a1d8SRichard Henderson  * and the destination PC.
174d3a2a1d8SRichard Henderson  */
175b1c09220SAnton Johansson bool translator_use_goto_tb(DisasContextBase *db, vaddr dest);
176d3a2a1d8SRichard Henderson 
177dfd1b812SRichard Henderson /**
178dfd1b812SRichard Henderson  * translator_io_start
179dfd1b812SRichard Henderson  * @db: Disassembly context
180dfd1b812SRichard Henderson  *
181d417e221SPhilippe Mathieu-Daudé  * If icount is enabled, set cpu->can_do_io, adjust db->is_jmp to
182dfd1b812SRichard Henderson  * DISAS_TOO_MANY if it is still DISAS_NEXT, and return true.
183dfd1b812SRichard Henderson  * Otherwise return false.
184dfd1b812SRichard Henderson  */
185dfd1b812SRichard Henderson bool translator_io_start(DisasContextBase *db);
186dfd1b812SRichard Henderson 
187409c1a0bSEmilio G. Cota /*
188409c1a0bSEmilio G. Cota  * Translator Load Functions
189409c1a0bSEmilio G. Cota  *
190a6d456dfSRichard Henderson  * These are intended to replace the direct usage of the cpu_ld*_code
191a6d456dfSRichard Henderson  * functions and are mandatory for front-ends that have been migrated
192a6d456dfSRichard Henderson  * to the common translator_loop. These functions are only intended
193a6d456dfSRichard Henderson  * to be called from the translation stage and should not be called
194a6d456dfSRichard Henderson  * from helper functions. Those functions should be converted to encode
195a6d456dfSRichard Henderson  * the relevant information at translation time.
196409c1a0bSEmilio G. Cota  */
197409c1a0bSEmilio G. Cota 
19880189472SRichard Henderson uint8_t translator_ldub(CPUArchState *env, DisasContextBase *db, vaddr pc);
19980189472SRichard Henderson uint16_t translator_lduw(CPUArchState *env, DisasContextBase *db, vaddr pc);
20080189472SRichard Henderson uint32_t translator_ldl(CPUArchState *env, DisasContextBase *db, vaddr pc);
20180189472SRichard Henderson uint64_t translator_ldq(CPUArchState *env, DisasContextBase *db, vaddr pc);
20250627f1bSRichard Henderson 
20350627f1bSRichard Henderson static inline uint16_t
20450627f1bSRichard Henderson translator_lduw_swap(CPUArchState *env, DisasContextBase *db,
20580189472SRichard Henderson                      vaddr pc, bool do_swap)
20650627f1bSRichard Henderson {
20750627f1bSRichard Henderson     uint16_t ret = translator_lduw(env, db, pc);
20850627f1bSRichard Henderson     if (do_swap) {
20950627f1bSRichard Henderson         ret = bswap16(ret);
21050627f1bSRichard Henderson     }
21150627f1bSRichard Henderson     return ret;
212409c1a0bSEmilio G. Cota }
213409c1a0bSEmilio G. Cota 
21450627f1bSRichard Henderson static inline uint32_t
21550627f1bSRichard Henderson translator_ldl_swap(CPUArchState *env, DisasContextBase *db,
21680189472SRichard Henderson                     vaddr pc, bool do_swap)
21750627f1bSRichard Henderson {
21850627f1bSRichard Henderson     uint32_t ret = translator_ldl(env, db, pc);
21950627f1bSRichard Henderson     if (do_swap) {
22050627f1bSRichard Henderson         ret = bswap32(ret);
22150627f1bSRichard Henderson     }
22250627f1bSRichard Henderson     return ret;
22350627f1bSRichard Henderson }
224f025692cSIlya Leoshkevich 
22550627f1bSRichard Henderson static inline uint64_t
22650627f1bSRichard Henderson translator_ldq_swap(CPUArchState *env, DisasContextBase *db,
22780189472SRichard Henderson                     vaddr pc, bool do_swap)
22850627f1bSRichard Henderson {
22950627f1bSRichard Henderson     uint64_t ret = translator_ldq(env, db, pc);
23050627f1bSRichard Henderson     if (do_swap) {
23150627f1bSRichard Henderson         ret = bswap64(ret);
23250627f1bSRichard Henderson     }
23350627f1bSRichard Henderson     return ret;
23450627f1bSRichard Henderson }
235409c1a0bSEmilio G. Cota 
2369fa97e04SAlex Bennée /**
2379fa97e04SAlex Bennée  * translator_fake_ldb - fake instruction load
23899977aefSRichard Henderson  * @db: Disassembly context
2399fa97e04SAlex Bennée  * @pc: program counter of instruction
24099977aefSRichard Henderson  * @insn8: byte of instruction
2419fa97e04SAlex Bennée  *
2429fa97e04SAlex Bennée  * This is a special case helper used where the instruction we are
2439fa97e04SAlex Bennée  * about to translate comes from somewhere else (e.g. being
2449fa97e04SAlex Bennée  * re-synthesised for s390x "ex"). It ensures we update other areas of
2459fa97e04SAlex Bennée  * the translator with details of the executed instruction.
2469fa97e04SAlex Bennée  */
24799977aefSRichard Henderson void translator_fake_ldb(DisasContextBase *db, vaddr pc, uint8_t insn8);
2489fa97e04SAlex Bennée 
24966f3b79eSRichard Henderson #ifdef COMPILING_PER_TARGET
250f3b2b81bSIlya Leoshkevich /*
251f3b2b81bSIlya Leoshkevich  * Return whether addr is on the same page as where disassembly started.
252f3b2b81bSIlya Leoshkevich  * Translators can use this to enforce the rule that only single-insn
253f3b2b81bSIlya Leoshkevich  * translation blocks are allowed to cross page boundaries.
254f3b2b81bSIlya Leoshkevich  */
25585c19af6SAnton Johansson static inline bool is_same_page(const DisasContextBase *db, vaddr addr)
256f3b2b81bSIlya Leoshkevich {
257f3b2b81bSIlya Leoshkevich     return ((addr ^ db->pc_first) & TARGET_PAGE_MASK) == 0;
258f3b2b81bSIlya Leoshkevich }
25966f3b79eSRichard Henderson #endif
260f3b2b81bSIlya Leoshkevich 
26177fc6f5eSLluís Vilanova #endif /* EXEC__TRANSLATOR_H */
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