177fc6f5eSLluís Vilanova /*
277fc6f5eSLluís Vilanova * Generic intermediate code generation.
377fc6f5eSLluís Vilanova *
477fc6f5eSLluís Vilanova * Copyright (C) 2016-2017 Lluís Vilanova <vilanova@ac.upc.edu>
577fc6f5eSLluís Vilanova *
677fc6f5eSLluís Vilanova * This work is licensed under the terms of the GNU GPL, version 2 or later.
777fc6f5eSLluís Vilanova * See the COPYING file in the top-level directory.
877fc6f5eSLluís Vilanova */
977fc6f5eSLluís Vilanova
1077fc6f5eSLluís Vilanova #ifndef EXEC__TRANSLATOR_H
1177fc6f5eSLluís Vilanova #define EXEC__TRANSLATOR_H
1277fc6f5eSLluís Vilanova
13bb2e0039SLluís Vilanova /*
14bb2e0039SLluís Vilanova * Include this header from a target-specific file, and add a
15bb2e0039SLluís Vilanova *
16bb2e0039SLluís Vilanova * DisasContextBase base;
17bb2e0039SLluís Vilanova *
18bb2e0039SLluís Vilanova * member in your target-specific DisasContext.
19bb2e0039SLluís Vilanova */
20bb2e0039SLluís Vilanova
21*5c43a750SRichard Henderson #include "exec/memop.h"
2280189472SRichard Henderson #include "exec/vaddr.h"
23bb2e0039SLluís Vilanova
24306c8721SRichard Henderson /**
2577fc6f5eSLluís Vilanova * DisasJumpType:
2677fc6f5eSLluís Vilanova * @DISAS_NEXT: Next instruction in program order.
2777fc6f5eSLluís Vilanova * @DISAS_TOO_MANY: Too many instructions translated.
2877fc6f5eSLluís Vilanova * @DISAS_NORETURN: Following code is dead.
2977fc6f5eSLluís Vilanova * @DISAS_TARGET_*: Start of target-specific conditions.
3077fc6f5eSLluís Vilanova *
3177fc6f5eSLluís Vilanova * What instruction to disassemble next.
3277fc6f5eSLluís Vilanova */
3377fc6f5eSLluís Vilanova typedef enum DisasJumpType {
3477fc6f5eSLluís Vilanova DISAS_NEXT,
3577fc6f5eSLluís Vilanova DISAS_TOO_MANY,
3677fc6f5eSLluís Vilanova DISAS_NORETURN,
3777fc6f5eSLluís Vilanova DISAS_TARGET_0,
3877fc6f5eSLluís Vilanova DISAS_TARGET_1,
3977fc6f5eSLluís Vilanova DISAS_TARGET_2,
4077fc6f5eSLluís Vilanova DISAS_TARGET_3,
4177fc6f5eSLluís Vilanova DISAS_TARGET_4,
4277fc6f5eSLluís Vilanova DISAS_TARGET_5,
4377fc6f5eSLluís Vilanova DISAS_TARGET_6,
4477fc6f5eSLluís Vilanova DISAS_TARGET_7,
4577fc6f5eSLluís Vilanova DISAS_TARGET_8,
4677fc6f5eSLluís Vilanova DISAS_TARGET_9,
4777fc6f5eSLluís Vilanova DISAS_TARGET_10,
4877fc6f5eSLluís Vilanova DISAS_TARGET_11,
4977fc6f5eSLluís Vilanova } DisasJumpType;
5077fc6f5eSLluís Vilanova
51bb2e0039SLluís Vilanova /**
52bb2e0039SLluís Vilanova * DisasContextBase:
53bb2e0039SLluís Vilanova * @tb: Translation block for this disassembly.
54bb2e0039SLluís Vilanova * @pc_first: Address of first guest instruction in this TB.
55bb2e0039SLluís Vilanova * @pc_next: Address of next guest instruction in this TB (current during
56bb2e0039SLluís Vilanova * disassembly).
57bb2e0039SLluís Vilanova * @is_jmp: What instruction to disassemble next.
58bb2e0039SLluís Vilanova * @num_insns: Number of translated instructions (including current).
59b542683dSEmilio G. Cota * @max_insns: Maximum number of instructions to be translated in this TB.
6028a4f0baSRichard Henderson * @plugin_enabled: TCG plugin enabled in this TB.
61b3f05b8cSRichard Henderson * @fake_insn: True if translator_fake_ldb used.
62e7face70SRichard Henderson * @insn_start: The last op emitted by the insn_start hook,
63e7face70SRichard Henderson * which is expected to be INDEX_op_insn_start.
64bb2e0039SLluís Vilanova *
65bb2e0039SLluís Vilanova * Architecture-agnostic disassembly context.
66bb2e0039SLluís Vilanova */
674c833c60SRichard Henderson struct DisasContextBase {
6850627f1bSRichard Henderson TranslationBlock *tb;
6985c19af6SAnton Johansson vaddr pc_first;
7085c19af6SAnton Johansson vaddr pc_next;
71bb2e0039SLluís Vilanova DisasJumpType is_jmp;
72b542683dSEmilio G. Cota int num_insns;
73b542683dSEmilio G. Cota int max_insns;
7428a4f0baSRichard Henderson bool plugin_enabled;
75b3f05b8cSRichard Henderson bool fake_insn;
76028119c8SRichard Henderson uint8_t code_mmuidx;
77e7face70SRichard Henderson struct TCGOp *insn_start;
7850627f1bSRichard Henderson void *host_addr[2];
79ba3fb2a7SRichard Henderson
80ba3fb2a7SRichard Henderson /*
81ba3fb2a7SRichard Henderson * Record insn data that we cannot read directly from host memory.
82ba3fb2a7SRichard Henderson * There are only two reasons we cannot use host memory:
83ba3fb2a7SRichard Henderson * (1) We are executing from I/O,
84ba3fb2a7SRichard Henderson * (2) We are executing a synthetic instruction (s390x EX).
85ba3fb2a7SRichard Henderson * In both cases we need record exactly one instruction,
86ba3fb2a7SRichard Henderson * and thus the maximum amount of data we record is limited.
87ba3fb2a7SRichard Henderson */
88ba3fb2a7SRichard Henderson int record_start;
89ba3fb2a7SRichard Henderson int record_len;
90ba3fb2a7SRichard Henderson uint8_t record[32];
914c833c60SRichard Henderson };
92bb2e0039SLluís Vilanova
93bb2e0039SLluís Vilanova /**
94bb2e0039SLluís Vilanova * TranslatorOps:
95bb2e0039SLluís Vilanova * @init_disas_context:
96bb2e0039SLluís Vilanova * Initialize the target-specific portions of DisasContext struct.
97bb2e0039SLluís Vilanova * The generic DisasContextBase has already been initialized.
98bb2e0039SLluís Vilanova *
99bb2e0039SLluís Vilanova * @tb_start:
100bb2e0039SLluís Vilanova * Emit any code required before the start of the main loop,
101bb2e0039SLluís Vilanova * after the generic gen_tb_start().
102bb2e0039SLluís Vilanova *
103bb2e0039SLluís Vilanova * @insn_start:
104bb2e0039SLluís Vilanova * Emit the tcg_gen_insn_start opcode.
105bb2e0039SLluís Vilanova *
106bb2e0039SLluís Vilanova * @translate_insn:
107bb2e0039SLluís Vilanova * Disassemble one instruction and set db->pc_next for the start
108bb2e0039SLluís Vilanova * of the following instruction. Set db->is_jmp as necessary to
109bb2e0039SLluís Vilanova * terminate the main loop.
110bb2e0039SLluís Vilanova *
111bb2e0039SLluís Vilanova * @tb_stop:
112bb2e0039SLluís Vilanova * Emit any opcodes required to exit the TB, based on db->is_jmp.
113bb2e0039SLluís Vilanova *
114bb2e0039SLluís Vilanova * @disas_log:
115bb2e0039SLluís Vilanova * Print instruction disassembly to log.
116bb2e0039SLluís Vilanova */
117bb2e0039SLluís Vilanova typedef struct TranslatorOps {
118b542683dSEmilio G. Cota void (*init_disas_context)(DisasContextBase *db, CPUState *cpu);
119bb2e0039SLluís Vilanova void (*tb_start)(DisasContextBase *db, CPUState *cpu);
120bb2e0039SLluís Vilanova void (*insn_start)(DisasContextBase *db, CPUState *cpu);
121bb2e0039SLluís Vilanova void (*translate_insn)(DisasContextBase *db, CPUState *cpu);
122bb2e0039SLluís Vilanova void (*tb_stop)(DisasContextBase *db, CPUState *cpu);
123b67c567bSRichard Henderson bool (*disas_log)(const DisasContextBase *db, CPUState *cpu, FILE *f);
124bb2e0039SLluís Vilanova } TranslatorOps;
125bb2e0039SLluís Vilanova
126bb2e0039SLluís Vilanova /**
127bb2e0039SLluís Vilanova * translator_loop:
128bb2e0039SLluís Vilanova * @cpu: Target vCPU.
129bb2e0039SLluís Vilanova * @tb: Translation block.
1308b86d6d2SRichard Henderson * @max_insns: Maximum number of insns to translate.
131306c8721SRichard Henderson * @pc: guest virtual program counter address
132306c8721SRichard Henderson * @host_pc: host physical program counter address
133306c8721SRichard Henderson * @ops: Target-specific operations.
134306c8721SRichard Henderson * @db: Disassembly context.
135bb2e0039SLluís Vilanova *
136bb2e0039SLluís Vilanova * Generic translator loop.
137bb2e0039SLluís Vilanova *
138bb2e0039SLluís Vilanova * Translation will stop in the following cases (in order):
139bb2e0039SLluís Vilanova * - When is_jmp set by #TranslatorOps::breakpoint_check.
140bb2e0039SLluís Vilanova * - set to DISAS_TOO_MANY exits after translating one more insn
141bb2e0039SLluís Vilanova * - set to any other value than DISAS_NEXT exits immediately.
142bb2e0039SLluís Vilanova * - When is_jmp set by #TranslatorOps::translate_insn.
143bb2e0039SLluís Vilanova * - set to any value other than DISAS_NEXT exits immediately.
144bb2e0039SLluís Vilanova * - When the TCG operation buffer is full.
145bb2e0039SLluís Vilanova * - When single-stepping is enabled (system-wide or on the current vCPU).
146bb2e0039SLluís Vilanova * - When too many instructions have been translated.
147bb2e0039SLluís Vilanova */
148597f9b2dSRichard Henderson void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns,
149b1c09220SAnton Johansson vaddr pc, void *host_pc, const TranslatorOps *ops,
150b1c09220SAnton Johansson DisasContextBase *db);
151bb2e0039SLluís Vilanova
152d3a2a1d8SRichard Henderson /**
153d3a2a1d8SRichard Henderson * translator_use_goto_tb
154d3a2a1d8SRichard Henderson * @db: Disassembly context
155d3a2a1d8SRichard Henderson * @dest: target pc of the goto
156d3a2a1d8SRichard Henderson *
157d3a2a1d8SRichard Henderson * Return true if goto_tb is allowed between the current TB
158d3a2a1d8SRichard Henderson * and the destination PC.
159d3a2a1d8SRichard Henderson */
160b1c09220SAnton Johansson bool translator_use_goto_tb(DisasContextBase *db, vaddr dest);
161d3a2a1d8SRichard Henderson
162dfd1b812SRichard Henderson /**
163dfd1b812SRichard Henderson * translator_io_start
164dfd1b812SRichard Henderson * @db: Disassembly context
165dfd1b812SRichard Henderson *
166d417e221SPhilippe Mathieu-Daudé * If icount is enabled, set cpu->can_do_io, adjust db->is_jmp to
167dfd1b812SRichard Henderson * DISAS_TOO_MANY if it is still DISAS_NEXT, and return true.
168dfd1b812SRichard Henderson * Otherwise return false.
169dfd1b812SRichard Henderson */
170dfd1b812SRichard Henderson bool translator_io_start(DisasContextBase *db);
171dfd1b812SRichard Henderson
172409c1a0bSEmilio G. Cota /*
173409c1a0bSEmilio G. Cota * Translator Load Functions
174409c1a0bSEmilio G. Cota *
175a6d456dfSRichard Henderson * These are intended to replace the direct usage of the cpu_ld*_code
176a6d456dfSRichard Henderson * functions and are mandatory for front-ends that have been migrated
177a6d456dfSRichard Henderson * to the common translator_loop. These functions are only intended
178a6d456dfSRichard Henderson * to be called from the translation stage and should not be called
179a6d456dfSRichard Henderson * from helper functions. Those functions should be converted to encode
180a6d456dfSRichard Henderson * the relevant information at translation time.
181409c1a0bSEmilio G. Cota */
182409c1a0bSEmilio G. Cota
18380189472SRichard Henderson uint8_t translator_ldub(CPUArchState *env, DisasContextBase *db, vaddr pc);
184*5c43a750SRichard Henderson uint16_t translator_lduw_end(CPUArchState *env, DisasContextBase *db,
185*5c43a750SRichard Henderson vaddr pc, MemOp endian);
186*5c43a750SRichard Henderson uint32_t translator_ldl_end(CPUArchState *env, DisasContextBase *db,
187*5c43a750SRichard Henderson vaddr pc, MemOp endian);
188*5c43a750SRichard Henderson uint64_t translator_ldq_end(CPUArchState *env, DisasContextBase *db,
189*5c43a750SRichard Henderson vaddr pc, MemOp endian);
190*5c43a750SRichard Henderson
191*5c43a750SRichard Henderson #ifdef COMPILING_PER_TARGET
192*5c43a750SRichard Henderson static inline uint16_t
translator_lduw(CPUArchState * env,DisasContextBase * db,vaddr pc)193*5c43a750SRichard Henderson translator_lduw(CPUArchState *env, DisasContextBase *db, vaddr pc)
194*5c43a750SRichard Henderson {
195*5c43a750SRichard Henderson return translator_lduw_end(env, db, pc, MO_TE);
196*5c43a750SRichard Henderson }
197*5c43a750SRichard Henderson
198*5c43a750SRichard Henderson static inline uint32_t
translator_ldl(CPUArchState * env,DisasContextBase * db,vaddr pc)199*5c43a750SRichard Henderson translator_ldl(CPUArchState *env, DisasContextBase *db, vaddr pc)
200*5c43a750SRichard Henderson {
201*5c43a750SRichard Henderson return translator_ldl_end(env, db, pc, MO_TE);
202*5c43a750SRichard Henderson }
203*5c43a750SRichard Henderson
204*5c43a750SRichard Henderson static inline uint64_t
translator_ldq(CPUArchState * env,DisasContextBase * db,vaddr pc)205*5c43a750SRichard Henderson translator_ldq(CPUArchState *env, DisasContextBase *db, vaddr pc)
206*5c43a750SRichard Henderson {
207*5c43a750SRichard Henderson return translator_ldq_end(env, db, pc, MO_TE);
208*5c43a750SRichard Henderson }
20950627f1bSRichard Henderson
21050627f1bSRichard Henderson static inline uint16_t
translator_lduw_swap(CPUArchState * env,DisasContextBase * db,vaddr pc,bool do_swap)21150627f1bSRichard Henderson translator_lduw_swap(CPUArchState *env, DisasContextBase *db,
21280189472SRichard Henderson vaddr pc, bool do_swap)
21350627f1bSRichard Henderson {
214*5c43a750SRichard Henderson return translator_lduw_end(env, db, pc, MO_TE ^ (do_swap * MO_BSWAP));
215409c1a0bSEmilio G. Cota }
216409c1a0bSEmilio G. Cota
21750627f1bSRichard Henderson static inline uint32_t
translator_ldl_swap(CPUArchState * env,DisasContextBase * db,vaddr pc,bool do_swap)21850627f1bSRichard Henderson translator_ldl_swap(CPUArchState *env, DisasContextBase *db,
21980189472SRichard Henderson vaddr pc, bool do_swap)
22050627f1bSRichard Henderson {
221*5c43a750SRichard Henderson return translator_ldl_end(env, db, pc, MO_TE ^ (do_swap * MO_BSWAP));
22250627f1bSRichard Henderson }
223f025692cSIlya Leoshkevich
22450627f1bSRichard Henderson static inline uint64_t
translator_ldq_swap(CPUArchState * env,DisasContextBase * db,vaddr pc,bool do_swap)22550627f1bSRichard Henderson translator_ldq_swap(CPUArchState *env, DisasContextBase *db,
22680189472SRichard Henderson vaddr pc, bool do_swap)
22750627f1bSRichard Henderson {
228*5c43a750SRichard Henderson return translator_ldq_end(env, db, pc, MO_TE ^ (do_swap * MO_BSWAP));
22950627f1bSRichard Henderson }
230*5c43a750SRichard Henderson #endif /* COMPILING_PER_TARGET */
231409c1a0bSEmilio G. Cota
2329fa97e04SAlex Bennée /**
2334c6163eaSRichard Henderson * translator_fake_ld - fake instruction load
23499977aefSRichard Henderson * @db: Disassembly context
2354c6163eaSRichard Henderson * @data: bytes of instruction
2364c6163eaSRichard Henderson * @len: number of bytes
2379fa97e04SAlex Bennée *
2389fa97e04SAlex Bennée * This is a special case helper used where the instruction we are
2399fa97e04SAlex Bennée * about to translate comes from somewhere else (e.g. being
2409fa97e04SAlex Bennée * re-synthesised for s390x "ex"). It ensures we update other areas of
2419fa97e04SAlex Bennée * the translator with details of the executed instruction.
2429fa97e04SAlex Bennée */
2434c6163eaSRichard Henderson void translator_fake_ld(DisasContextBase *db, const void *data, size_t len);
2449fa97e04SAlex Bennée
2453a247368SRichard Henderson /**
2463a247368SRichard Henderson * translator_st
2473a247368SRichard Henderson * @db: disassembly context
2483a247368SRichard Henderson * @dest: address to copy into
2493a247368SRichard Henderson * @addr: virtual address within TB
2503a247368SRichard Henderson * @len: length
2513a247368SRichard Henderson *
2523a247368SRichard Henderson * Copy @len bytes from @addr into @dest.
2533a247368SRichard Henderson * All bytes must have been read during translation.
2543a247368SRichard Henderson * Return true on success or false on failure.
2553a247368SRichard Henderson */
2563a247368SRichard Henderson bool translator_st(const DisasContextBase *db, void *dest,
2573a247368SRichard Henderson vaddr addr, size_t len);
2583a247368SRichard Henderson
2593a247368SRichard Henderson /**
2603a247368SRichard Henderson * translator_st_len
2613a247368SRichard Henderson * @db: disassembly context
2623a247368SRichard Henderson *
2633a247368SRichard Henderson * Return the number of bytes available to copy from the
2643a247368SRichard Henderson * current translation block with translator_st.
2653a247368SRichard Henderson */
2663a247368SRichard Henderson size_t translator_st_len(const DisasContextBase *db);
2673a247368SRichard Henderson
268a9ca97eaSPhilippe Mathieu-Daudé /**
269a9ca97eaSPhilippe Mathieu-Daudé * translator_is_same_page
270a9ca97eaSPhilippe Mathieu-Daudé * @db: disassembly context
271a9ca97eaSPhilippe Mathieu-Daudé * @addr: virtual address within TB
272a9ca97eaSPhilippe Mathieu-Daudé *
273a9ca97eaSPhilippe Mathieu-Daudé * Return whether @addr is on the same page as where disassembly started.
274f3b2b81bSIlya Leoshkevich * Translators can use this to enforce the rule that only single-insn
275f3b2b81bSIlya Leoshkevich * translation blocks are allowed to cross page boundaries.
276f3b2b81bSIlya Leoshkevich */
277a9ca97eaSPhilippe Mathieu-Daudé bool translator_is_same_page(const DisasContextBase *db, vaddr addr);
278f3b2b81bSIlya Leoshkevich
27977fc6f5eSLluís Vilanova #endif /* EXEC__TRANSLATOR_H */
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