1 /* 2 * common defines for all CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef CPU_DEFS_H 20 #define CPU_DEFS_H 21 22 #ifndef COMPILING_PER_TARGET 23 #error cpu.h included from common code 24 #endif 25 26 #include "cpu-param.h" 27 28 #ifndef TARGET_LONG_BITS 29 # error TARGET_LONG_BITS must be defined in cpu-param.h 30 #endif 31 #ifndef TARGET_PHYS_ADDR_SPACE_BITS 32 # error TARGET_PHYS_ADDR_SPACE_BITS must be defined in cpu-param.h 33 #endif 34 #ifndef TARGET_VIRT_ADDR_SPACE_BITS 35 # error TARGET_VIRT_ADDR_SPACE_BITS must be defined in cpu-param.h 36 #endif 37 #ifndef TARGET_PAGE_BITS 38 # ifdef TARGET_PAGE_BITS_VARY 39 # ifndef TARGET_PAGE_BITS_MIN 40 # error TARGET_PAGE_BITS_MIN must be defined in cpu-param.h 41 # endif 42 # else 43 # error TARGET_PAGE_BITS must be defined in cpu-param.h 44 # endif 45 #endif 46 47 #include "exec/target_long.h" 48 49 #if defined(CONFIG_SOFTMMU) && defined(CONFIG_TCG) 50 #define CPU_TLB_DYN_MIN_BITS 6 51 #define CPU_TLB_DYN_DEFAULT_BITS 8 52 53 # if HOST_LONG_BITS == 32 54 /* Make sure we do not require a double-word shift for the TLB load */ 55 # define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS) 56 # else /* HOST_LONG_BITS == 64 */ 57 /* 58 * Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) == 59 * 2**34 == 16G of address space. This is roughly what one would expect a 60 * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel 61 * Skylake's Level-2 STLB has 16 1G entries. 62 * Also, make sure we do not size the TLB past the guest's address space. 63 */ 64 # ifdef TARGET_PAGE_BITS_VARY 65 # define CPU_TLB_DYN_MAX_BITS \ 66 MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) 67 # else 68 # define CPU_TLB_DYN_MAX_BITS \ 69 MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) 70 # endif 71 # endif 72 73 #endif /* CONFIG_SOFTMMU && CONFIG_TCG */ 74 75 #endif 76