1 /* 2 * CPU interfaces that are target independent. 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * SPDX-License-Identifier: LGPL-2.1+ 7 */ 8 #ifndef CPU_COMMON_H 9 #define CPU_COMMON_H 10 11 #include "exec/vaddr.h" 12 #ifndef CONFIG_USER_ONLY 13 #include "exec/hwaddr.h" 14 #endif 15 #include "hw/core/cpu.h" 16 #include "tcg/debug-assert.h" 17 #include "exec/page-protection.h" 18 19 #define EXCP_INTERRUPT 0x10000 /* async interruption */ 20 #define EXCP_HLT 0x10001 /* hlt instruction reached */ 21 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ 22 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ 23 #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */ 24 #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */ 25 26 void cpu_exec_init_all(void); 27 void cpu_exec_step_atomic(CPUState *cpu); 28 29 #define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_size()) 30 31 /* The CPU list lock nests outside page_(un)lock or mmap_(un)lock */ 32 extern QemuMutex qemu_cpu_list_lock; 33 void qemu_init_cpu_list(void); 34 void cpu_list_lock(void); 35 void cpu_list_unlock(void); 36 unsigned int cpu_list_generation_id_get(void); 37 38 int cpu_get_free_index(void); 39 40 void tcg_iommu_init_notifier_list(CPUState *cpu); 41 void tcg_iommu_free_notifier_list(CPUState *cpu); 42 43 #if !defined(CONFIG_USER_ONLY) 44 45 enum device_endian { 46 DEVICE_NATIVE_ENDIAN, 47 DEVICE_BIG_ENDIAN, 48 DEVICE_LITTLE_ENDIAN, 49 }; 50 51 #if HOST_BIG_ENDIAN 52 #define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN 53 #else 54 #define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN 55 #endif 56 57 /* address in the RAM (different from a physical address) */ 58 #if defined(CONFIG_XEN_BACKEND) 59 typedef uint64_t ram_addr_t; 60 # define RAM_ADDR_MAX UINT64_MAX 61 # define RAM_ADDR_FMT "%" PRIx64 62 #else 63 typedef uintptr_t ram_addr_t; 64 # define RAM_ADDR_MAX UINTPTR_MAX 65 # define RAM_ADDR_FMT "%" PRIxPTR 66 #endif 67 68 /* memory API */ 69 70 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); 71 /* This should not be used by devices. */ 72 ram_addr_t qemu_ram_addr_from_host(void *ptr); 73 ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr); 74 RAMBlock *qemu_ram_block_by_name(const char *name); 75 76 /* 77 * Translates a host ptr back to a RAMBlock and an offset in that RAMBlock. 78 * 79 * @ptr: The host pointer to translate. 80 * @round_offset: Whether to round the result offset down to a target page 81 * @offset: Will be set to the offset within the returned RAMBlock. 82 * 83 * Returns: RAMBlock (or NULL if not found) 84 * 85 * By the time this function returns, the returned pointer is not protected 86 * by RCU anymore. If the caller is not within an RCU critical section and 87 * does not hold the BQL, it must have other means of protecting the 88 * pointer, such as a reference to the memory region that owns the RAMBlock. 89 */ 90 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset, 91 ram_addr_t *offset); 92 ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host); 93 void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev); 94 void qemu_ram_unset_idstr(RAMBlock *block); 95 const char *qemu_ram_get_idstr(RAMBlock *rb); 96 void *qemu_ram_get_host_addr(RAMBlock *rb); 97 ram_addr_t qemu_ram_get_offset(RAMBlock *rb); 98 ram_addr_t qemu_ram_get_used_length(RAMBlock *rb); 99 ram_addr_t qemu_ram_get_max_length(RAMBlock *rb); 100 bool qemu_ram_is_shared(RAMBlock *rb); 101 bool qemu_ram_is_noreserve(RAMBlock *rb); 102 bool qemu_ram_is_uf_zeroable(RAMBlock *rb); 103 void qemu_ram_set_uf_zeroable(RAMBlock *rb); 104 bool qemu_ram_is_migratable(RAMBlock *rb); 105 void qemu_ram_set_migratable(RAMBlock *rb); 106 void qemu_ram_unset_migratable(RAMBlock *rb); 107 bool qemu_ram_is_named_file(RAMBlock *rb); 108 int qemu_ram_get_fd(RAMBlock *rb); 109 110 size_t qemu_ram_pagesize(RAMBlock *block); 111 size_t qemu_ram_pagesize_largest(void); 112 113 /** 114 * cpu_address_space_init: 115 * @cpu: CPU to add this address space to 116 * @asidx: integer index of this address space 117 * @prefix: prefix to be used as name of address space 118 * @mr: the root memory region of address space 119 * 120 * Add the specified address space to the CPU's cpu_ases list. 121 * The address space added with @asidx 0 is the one used for the 122 * convenience pointer cpu->as. 123 * The target-specific code which registers ASes is responsible 124 * for defining what semantics address space 0, 1, 2, etc have. 125 * 126 * Before the first call to this function, the caller must set 127 * cpu->num_ases to the total number of address spaces it needs 128 * to support. 129 * 130 * Note that with KVM only one address space is supported. 131 */ 132 void cpu_address_space_init(CPUState *cpu, int asidx, 133 const char *prefix, MemoryRegion *mr); 134 /** 135 * cpu_address_space_destroy: 136 * @cpu: CPU for which address space needs to be destroyed 137 * @asidx: integer index of this address space 138 * 139 * Note that with KVM only one address space is supported. 140 */ 141 void cpu_address_space_destroy(CPUState *cpu, int asidx); 142 143 void cpu_physical_memory_rw(hwaddr addr, void *buf, 144 hwaddr len, bool is_write); 145 static inline void cpu_physical_memory_read(hwaddr addr, 146 void *buf, hwaddr len) 147 { 148 cpu_physical_memory_rw(addr, buf, len, false); 149 } 150 static inline void cpu_physical_memory_write(hwaddr addr, 151 const void *buf, hwaddr len) 152 { 153 cpu_physical_memory_rw(addr, (void *)buf, len, true); 154 } 155 void *cpu_physical_memory_map(hwaddr addr, 156 hwaddr *plen, 157 bool is_write); 158 void cpu_physical_memory_unmap(void *buffer, hwaddr len, 159 bool is_write, hwaddr access_len); 160 161 bool cpu_physical_memory_is_io(hwaddr phys_addr); 162 163 /* Coalesced MMIO regions are areas where write operations can be reordered. 164 * This usually implies that write operations are side-effect free. This allows 165 * batching which can make a major impact on performance when using 166 * virtualization. 167 */ 168 void qemu_flush_coalesced_mmio_buffer(void); 169 170 void cpu_flush_icache_range(hwaddr start, hwaddr len); 171 172 typedef int (RAMBlockIterFunc)(RAMBlock *rb, void *opaque); 173 174 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque); 175 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length); 176 int ram_block_discard_guest_memfd_range(RAMBlock *rb, uint64_t start, 177 size_t length); 178 179 #endif 180 181 /* Returns: 0 on success, -1 on error */ 182 int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, 183 void *ptr, size_t len, bool is_write); 184 185 /* vl.c */ 186 void list_cpus(void); 187 188 #ifdef CONFIG_TCG 189 #include "qemu/atomic.h" 190 191 /** 192 * cpu_unwind_state_data: 193 * @cpu: the cpu context 194 * @host_pc: the host pc within the translation 195 * @data: output data 196 * 197 * Attempt to load the the unwind state for a host pc occurring in 198 * translated code. If @host_pc is not in translated code, the 199 * function returns false; otherwise @data is loaded. 200 * This is the same unwind info as given to restore_state_to_opc. 201 */ 202 bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data); 203 204 /** 205 * cpu_restore_state: 206 * @cpu: the cpu context 207 * @host_pc: the host pc within the translation 208 * @return: true if state was restored, false otherwise 209 * 210 * Attempt to restore the state for a fault occurring in translated 211 * code. If @host_pc is not in translated code no state is 212 * restored and the function returns false. 213 */ 214 bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc); 215 216 /** 217 * cpu_loop_exit_requested: 218 * @cpu: The CPU state to be tested 219 * 220 * Indicate if somebody asked for a return of the CPU to the main loop 221 * (e.g., via cpu_exit() or cpu_interrupt()). 222 * 223 * This is helpful for architectures that support interruptible 224 * instructions. After writing back all state to registers/memory, this 225 * call can be used to check if it makes sense to return to the main loop 226 * or to continue executing the interruptible instruction. 227 */ 228 static inline bool cpu_loop_exit_requested(CPUState *cpu) 229 { 230 return (int32_t)qatomic_read(&cpu->neg.icount_decr.u32) < 0; 231 } 232 233 G_NORETURN void cpu_loop_exit_noexc(CPUState *cpu); 234 G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc); 235 #endif /* CONFIG_TCG */ 236 G_NORETURN void cpu_loop_exit(CPUState *cpu); 237 G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc); 238 239 /* accel/tcg/cpu-exec.c */ 240 int cpu_exec(CPUState *cpu); 241 242 /** 243 * env_archcpu(env) 244 * @env: The architecture environment 245 * 246 * Return the ArchCPU associated with the environment. 247 */ 248 static inline ArchCPU *env_archcpu(CPUArchState *env) 249 { 250 return (void *)env - sizeof(CPUState); 251 } 252 253 /** 254 * env_cpu_const(env) 255 * @env: The architecture environment 256 * 257 * Return the CPUState associated with the environment. 258 */ 259 static inline const CPUState *env_cpu_const(const CPUArchState *env) 260 { 261 return (void *)env - sizeof(CPUState); 262 } 263 264 /** 265 * env_cpu(env) 266 * @env: The architecture environment 267 * 268 * Return the CPUState associated with the environment. 269 */ 270 static inline CPUState *env_cpu(CPUArchState *env) 271 { 272 return (CPUState *)env_cpu_const(env); 273 } 274 275 #ifndef CONFIG_USER_ONLY 276 /** 277 * cpu_mmu_index: 278 * @env: The cpu environment 279 * @ifetch: True for code access, false for data access. 280 * 281 * Return the core mmu index for the current translation regime. 282 * This function is used by generic TCG code paths. 283 * 284 * The user-only version of this function is inline in cpu-all.h, 285 * where it always returns MMU_USER_IDX. 286 */ 287 static inline int cpu_mmu_index(CPUState *cs, bool ifetch) 288 { 289 int ret = cs->cc->mmu_index(cs, ifetch); 290 tcg_debug_assert(ret >= 0 && ret < NB_MMU_MODES); 291 return ret; 292 } 293 #endif /* !CONFIG_USER_ONLY */ 294 295 #endif /* CPU_COMMON_H */ 296