1 /* 2 * TCG CPU-specific operations 3 * 4 * Copyright 2021 SUSE LLC 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 10 #ifndef TCG_CPU_OPS_H 11 #define TCG_CPU_OPS_H 12 13 #include "exec/breakpoint.h" 14 #include "exec/hwaddr.h" 15 #include "exec/memattrs.h" 16 #include "exec/memop.h" 17 #include "exec/mmu-access-type.h" 18 #include "exec/vaddr.h" 19 #include "tcg/tcg-mo.h" 20 21 struct TCGCPUOps { 22 /** 23 * mttcg_supported: multi-threaded TCG is supported 24 * 25 * Target (TCG frontend) supports: 26 * - atomic instructions 27 * - memory ordering primitives (barriers) 28 */ 29 bool mttcg_supported; 30 31 /** 32 * @guest_default_memory_order: default barrier that is required 33 * for the guest memory ordering. 34 */ 35 TCGBar guest_default_memory_order; 36 37 /** 38 * @initialize: Initialize TCG state 39 * 40 * Called when the first CPU is realized. 41 */ 42 void (*initialize)(void); 43 /** 44 * @translate_code: Translate guest instructions to TCGOps 45 * @cpu: cpu context 46 * @tb: translation block 47 * @max_insns: max number of instructions to translate 48 * @pc: guest virtual program counter address 49 * @host_pc: host physical program counter address 50 * 51 * This function must be provided by the target, which should create 52 * the target-specific DisasContext, and then invoke translator_loop. 53 */ 54 void (*translate_code)(CPUState *cpu, TranslationBlock *tb, 55 int *max_insns, vaddr pc, void *host_pc); 56 /** 57 * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock 58 * 59 * This is called when we abandon execution of a TB before starting it, 60 * and must set all parts of the CPU state which the previous TB in the 61 * chain may not have updated. 62 * By default, when this is NULL, a call is made to @set_pc(tb->pc). 63 * 64 * If more state needs to be restored, the target must implement a 65 * function to restore all the state, and register it here. 66 */ 67 void (*synchronize_from_tb)(CPUState *cpu, const TranslationBlock *tb); 68 /** 69 * @restore_state_to_opc: Synchronize state from INDEX_op_start_insn 70 * 71 * This is called when we unwind state in the middle of a TB, 72 * usually before raising an exception. Set all part of the CPU 73 * state which are tracked insn-by-insn in the target-specific 74 * arguments to start_insn, passed as @data. 75 */ 76 void (*restore_state_to_opc)(CPUState *cpu, const TranslationBlock *tb, 77 const uint64_t *data); 78 79 /** @cpu_exec_enter: Callback for cpu_exec preparation */ 80 void (*cpu_exec_enter)(CPUState *cpu); 81 /** @cpu_exec_exit: Callback for cpu_exec cleanup */ 82 void (*cpu_exec_exit)(CPUState *cpu); 83 /** @debug_excp_handler: Callback for handling debug exceptions */ 84 void (*debug_excp_handler)(CPUState *cpu); 85 86 /** @mmu_index: Callback for choosing softmmu mmu index */ 87 int (*mmu_index)(CPUState *cpu, bool ifetch); 88 89 #ifdef CONFIG_USER_ONLY 90 /** 91 * @fake_user_interrupt: Callback for 'fake exception' handling. 92 * 93 * Simulate 'fake exception' which will be handled outside the 94 * cpu execution loop (hack for x86 user mode). 95 */ 96 void (*fake_user_interrupt)(CPUState *cpu); 97 98 /** 99 * record_sigsegv: 100 * @cpu: cpu context 101 * @addr: faulting guest address 102 * @access_type: access was read/write/execute 103 * @maperr: true for invalid page, false for permission fault 104 * @ra: host pc for unwinding 105 * 106 * We are about to raise SIGSEGV with si_code set for @maperr, 107 * and si_addr set for @addr. Record anything further needed 108 * for the signal ucontext_t. 109 * 110 * If the emulated kernel does not provide anything to the signal 111 * handler with anything besides the user context registers, and 112 * the siginfo_t, then this hook need do nothing and may be omitted. 113 * Otherwise, record the data and return; the caller will raise 114 * the signal, unwind the cpu state, and return to the main loop. 115 * 116 * If it is simpler to re-use the sysemu tlb_fill code, @ra is provided 117 * so that a "normal" cpu exception can be raised. In this case, 118 * the signal must be raised by the architecture cpu_loop. 119 */ 120 void (*record_sigsegv)(CPUState *cpu, vaddr addr, 121 MMUAccessType access_type, 122 bool maperr, uintptr_t ra); 123 /** 124 * record_sigbus: 125 * @cpu: cpu context 126 * @addr: misaligned guest address 127 * @access_type: access was read/write/execute 128 * @ra: host pc for unwinding 129 * 130 * We are about to raise SIGBUS with si_code BUS_ADRALN, 131 * and si_addr set for @addr. Record anything further needed 132 * for the signal ucontext_t. 133 * 134 * If the emulated kernel does not provide the signal handler with 135 * anything besides the user context registers, and the siginfo_t, 136 * then this hook need do nothing and may be omitted. 137 * Otherwise, record the data and return; the caller will raise 138 * the signal, unwind the cpu state, and return to the main loop. 139 * 140 * If it is simpler to re-use the sysemu do_unaligned_access code, 141 * @ra is provided so that a "normal" cpu exception can be raised. 142 * In this case, the signal must be raised by the architecture cpu_loop. 143 */ 144 void (*record_sigbus)(CPUState *cpu, vaddr addr, 145 MMUAccessType access_type, uintptr_t ra); 146 #else 147 /** @do_interrupt: Callback for interrupt handling. */ 148 void (*do_interrupt)(CPUState *cpu); 149 /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */ 150 bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); 151 /** 152 * @cpu_exec_halt: Callback for handling halt in cpu_exec. 153 * 154 * The target CPU should do any special processing here that it needs 155 * to do when the CPU is in the halted state. 156 * 157 * Return true to indicate that the CPU should now leave halt, false 158 * if it should remain in the halted state. (This should generally 159 * be the same value that cpu_has_work() would return.) 160 * 161 * This method must be provided. If the target does not need to 162 * do anything special for halt, the same function used for its 163 * SysemuCPUOps::has_work method can be used here, as they have the 164 * same function signature. 165 */ 166 bool (*cpu_exec_halt)(CPUState *cpu); 167 /** 168 * @tlb_fill_align: Handle a softmmu tlb miss 169 * @cpu: cpu context 170 * @out: output page properties 171 * @addr: virtual address 172 * @access_type: read, write or execute 173 * @mmu_idx: mmu context 174 * @memop: memory operation for the access 175 * @size: memory access size, or 0 for whole page 176 * @probe: test only, no fault 177 * @ra: host return address for exception unwind 178 * 179 * If the access is valid, fill in @out and return true. 180 * Otherwise if probe is true, return false. 181 * Otherwise raise an exception and do not return. 182 * 183 * The alignment check for the access is deferred to this hook, 184 * so that the target can determine the priority of any alignment 185 * fault with respect to other potential faults from paging. 186 * Zero may be passed for @memop to skip any alignment check 187 * for non-memory-access operations such as probing. 188 */ 189 bool (*tlb_fill_align)(CPUState *cpu, CPUTLBEntryFull *out, vaddr addr, 190 MMUAccessType access_type, int mmu_idx, 191 MemOp memop, int size, bool probe, uintptr_t ra); 192 /** 193 * @tlb_fill: Handle a softmmu tlb miss 194 * 195 * If the access is valid, call tlb_set_page and return true; 196 * if the access is invalid and probe is true, return false; 197 * otherwise raise an exception and do not return. 198 */ 199 bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, 200 MMUAccessType access_type, int mmu_idx, 201 bool probe, uintptr_t retaddr); 202 /** 203 * @do_transaction_failed: Callback for handling failed memory transactions 204 * (ie bus faults or external aborts; not MMU faults) 205 */ 206 void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr, 207 unsigned size, MMUAccessType access_type, 208 int mmu_idx, MemTxAttrs attrs, 209 MemTxResult response, uintptr_t retaddr); 210 /** 211 * @do_unaligned_access: Callback for unaligned access handling 212 * The callback must exit via raising an exception. 213 */ 214 G_NORETURN void (*do_unaligned_access)(CPUState *cpu, vaddr addr, 215 MMUAccessType access_type, 216 int mmu_idx, uintptr_t retaddr); 217 218 /** 219 * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM 220 */ 221 vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len); 222 223 /** 224 * @debug_check_watchpoint: return true if the architectural 225 * watchpoint whose address has matched should really fire, used by ARM 226 * and RISC-V 227 */ 228 bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); 229 230 /** 231 * @debug_check_breakpoint: return true if the architectural 232 * breakpoint whose PC has matched should really fire. 233 */ 234 bool (*debug_check_breakpoint)(CPUState *cpu); 235 236 /** 237 * @io_recompile_replay_branch: Callback for cpu_io_recompile. 238 * 239 * The cpu has been stopped, and cpu_restore_state_from_tb has been 240 * called. If the faulting instruction is in a delay slot, and the 241 * target architecture requires re-execution of the branch, then 242 * adjust the cpu state as required and return true. 243 */ 244 bool (*io_recompile_replay_branch)(CPUState *cpu, 245 const TranslationBlock *tb); 246 /** 247 * @need_replay_interrupt: Return %true if @interrupt_request 248 * needs to be recorded for replay purposes. 249 */ 250 bool (*need_replay_interrupt)(int interrupt_request); 251 #endif /* !CONFIG_USER_ONLY */ 252 }; 253 254 #if defined(CONFIG_USER_ONLY) 255 256 static inline void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, 257 MemTxAttrs atr, int fl, uintptr_t ra) 258 { 259 } 260 261 static inline int cpu_watchpoint_address_matches(CPUState *cpu, 262 vaddr addr, vaddr len) 263 { 264 return 0; 265 } 266 267 #else 268 269 /** 270 * cpu_check_watchpoint: 271 * @cpu: cpu context 272 * @addr: guest virtual address 273 * @len: access length 274 * @attrs: memory access attributes 275 * @flags: watchpoint access type 276 * @ra: unwind return address 277 * 278 * Check for a watchpoint hit in [addr, addr+len) of the type 279 * specified by @flags. Exit via exception with a hit. 280 */ 281 void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, 282 MemTxAttrs attrs, int flags, uintptr_t ra); 283 284 /** 285 * cpu_watchpoint_address_matches: 286 * @cpu: cpu context 287 * @addr: guest virtual address 288 * @len: access length 289 * 290 * Return the watchpoint flags that apply to [addr, addr+len). 291 * If no watchpoint is registered for the range, the result is 0. 292 */ 293 int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len); 294 295 #endif 296 297 #endif /* TCG_CPU_OPS_H */ 298