1 /* 2 * TCG CPU-specific operations 3 * 4 * Copyright 2021 SUSE LLC 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 10 #ifndef TCG_CPU_OPS_H 11 #define TCG_CPU_OPS_H 12 13 #include "exec/breakpoint.h" 14 #include "exec/hwaddr.h" 15 #include "exec/memattrs.h" 16 #include "exec/memop.h" 17 #include "exec/mmu-access-type.h" 18 #include "exec/vaddr.h" 19 20 struct TCGCPUOps { 21 /** 22 * @initialize: Initialize TCG state 23 * 24 * Called when the first CPU is realized. 25 */ 26 void (*initialize)(void); 27 /** 28 * @translate_code: Translate guest instructions to TCGOps 29 * @cpu: cpu context 30 * @tb: translation block 31 * @max_insns: max number of instructions to translate 32 * @pc: guest virtual program counter address 33 * @host_pc: host physical program counter address 34 * 35 * This function must be provided by the target, which should create 36 * the target-specific DisasContext, and then invoke translator_loop. 37 */ 38 void (*translate_code)(CPUState *cpu, TranslationBlock *tb, 39 int *max_insns, vaddr pc, void *host_pc); 40 /** 41 * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock 42 * 43 * This is called when we abandon execution of a TB before starting it, 44 * and must set all parts of the CPU state which the previous TB in the 45 * chain may not have updated. 46 * By default, when this is NULL, a call is made to @set_pc(tb->pc). 47 * 48 * If more state needs to be restored, the target must implement a 49 * function to restore all the state, and register it here. 50 */ 51 void (*synchronize_from_tb)(CPUState *cpu, const TranslationBlock *tb); 52 /** 53 * @restore_state_to_opc: Synchronize state from INDEX_op_start_insn 54 * 55 * This is called when we unwind state in the middle of a TB, 56 * usually before raising an exception. Set all part of the CPU 57 * state which are tracked insn-by-insn in the target-specific 58 * arguments to start_insn, passed as @data. 59 */ 60 void (*restore_state_to_opc)(CPUState *cpu, const TranslationBlock *tb, 61 const uint64_t *data); 62 63 /** @cpu_exec_enter: Callback for cpu_exec preparation */ 64 void (*cpu_exec_enter)(CPUState *cpu); 65 /** @cpu_exec_exit: Callback for cpu_exec cleanup */ 66 void (*cpu_exec_exit)(CPUState *cpu); 67 /** @debug_excp_handler: Callback for handling debug exceptions */ 68 void (*debug_excp_handler)(CPUState *cpu); 69 70 #ifdef CONFIG_USER_ONLY 71 /** 72 * @fake_user_interrupt: Callback for 'fake exception' handling. 73 * 74 * Simulate 'fake exception' which will be handled outside the 75 * cpu execution loop (hack for x86 user mode). 76 */ 77 void (*fake_user_interrupt)(CPUState *cpu); 78 79 /** 80 * record_sigsegv: 81 * @cpu: cpu context 82 * @addr: faulting guest address 83 * @access_type: access was read/write/execute 84 * @maperr: true for invalid page, false for permission fault 85 * @ra: host pc for unwinding 86 * 87 * We are about to raise SIGSEGV with si_code set for @maperr, 88 * and si_addr set for @addr. Record anything further needed 89 * for the signal ucontext_t. 90 * 91 * If the emulated kernel does not provide anything to the signal 92 * handler with anything besides the user context registers, and 93 * the siginfo_t, then this hook need do nothing and may be omitted. 94 * Otherwise, record the data and return; the caller will raise 95 * the signal, unwind the cpu state, and return to the main loop. 96 * 97 * If it is simpler to re-use the sysemu tlb_fill code, @ra is provided 98 * so that a "normal" cpu exception can be raised. In this case, 99 * the signal must be raised by the architecture cpu_loop. 100 */ 101 void (*record_sigsegv)(CPUState *cpu, vaddr addr, 102 MMUAccessType access_type, 103 bool maperr, uintptr_t ra); 104 /** 105 * record_sigbus: 106 * @cpu: cpu context 107 * @addr: misaligned guest address 108 * @access_type: access was read/write/execute 109 * @ra: host pc for unwinding 110 * 111 * We are about to raise SIGBUS with si_code BUS_ADRALN, 112 * and si_addr set for @addr. Record anything further needed 113 * for the signal ucontext_t. 114 * 115 * If the emulated kernel does not provide the signal handler with 116 * anything besides the user context registers, and the siginfo_t, 117 * then this hook need do nothing and may be omitted. 118 * Otherwise, record the data and return; the caller will raise 119 * the signal, unwind the cpu state, and return to the main loop. 120 * 121 * If it is simpler to re-use the sysemu do_unaligned_access code, 122 * @ra is provided so that a "normal" cpu exception can be raised. 123 * In this case, the signal must be raised by the architecture cpu_loop. 124 */ 125 void (*record_sigbus)(CPUState *cpu, vaddr addr, 126 MMUAccessType access_type, uintptr_t ra); 127 #else 128 /** @do_interrupt: Callback for interrupt handling. */ 129 void (*do_interrupt)(CPUState *cpu); 130 /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */ 131 bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); 132 /** 133 * @cpu_exec_halt: Callback for handling halt in cpu_exec. 134 * 135 * The target CPU should do any special processing here that it needs 136 * to do when the CPU is in the halted state. 137 * 138 * Return true to indicate that the CPU should now leave halt, false 139 * if it should remain in the halted state. (This should generally 140 * be the same value that cpu_has_work() would return.) 141 * 142 * This method must be provided. If the target does not need to 143 * do anything special for halt, the same function used for its 144 * CPUClass::has_work method can be used here, as they have the 145 * same function signature. 146 */ 147 bool (*cpu_exec_halt)(CPUState *cpu); 148 /** 149 * @tlb_fill_align: Handle a softmmu tlb miss 150 * @cpu: cpu context 151 * @out: output page properties 152 * @addr: virtual address 153 * @access_type: read, write or execute 154 * @mmu_idx: mmu context 155 * @memop: memory operation for the access 156 * @size: memory access size, or 0 for whole page 157 * @probe: test only, no fault 158 * @ra: host return address for exception unwind 159 * 160 * If the access is valid, fill in @out and return true. 161 * Otherwise if probe is true, return false. 162 * Otherwise raise an exception and do not return. 163 * 164 * The alignment check for the access is deferred to this hook, 165 * so that the target can determine the priority of any alignment 166 * fault with respect to other potential faults from paging. 167 * Zero may be passed for @memop to skip any alignment check 168 * for non-memory-access operations such as probing. 169 */ 170 bool (*tlb_fill_align)(CPUState *cpu, CPUTLBEntryFull *out, vaddr addr, 171 MMUAccessType access_type, int mmu_idx, 172 MemOp memop, int size, bool probe, uintptr_t ra); 173 /** 174 * @tlb_fill: Handle a softmmu tlb miss 175 * 176 * If the access is valid, call tlb_set_page and return true; 177 * if the access is invalid and probe is true, return false; 178 * otherwise raise an exception and do not return. 179 */ 180 bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, 181 MMUAccessType access_type, int mmu_idx, 182 bool probe, uintptr_t retaddr); 183 /** 184 * @do_transaction_failed: Callback for handling failed memory transactions 185 * (ie bus faults or external aborts; not MMU faults) 186 */ 187 void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr, 188 unsigned size, MMUAccessType access_type, 189 int mmu_idx, MemTxAttrs attrs, 190 MemTxResult response, uintptr_t retaddr); 191 /** 192 * @do_unaligned_access: Callback for unaligned access handling 193 * The callback must exit via raising an exception. 194 */ 195 G_NORETURN void (*do_unaligned_access)(CPUState *cpu, vaddr addr, 196 MMUAccessType access_type, 197 int mmu_idx, uintptr_t retaddr); 198 199 /** 200 * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM 201 */ 202 vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len); 203 204 /** 205 * @debug_check_watchpoint: return true if the architectural 206 * watchpoint whose address has matched should really fire, used by ARM 207 * and RISC-V 208 */ 209 bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); 210 211 /** 212 * @debug_check_breakpoint: return true if the architectural 213 * breakpoint whose PC has matched should really fire. 214 */ 215 bool (*debug_check_breakpoint)(CPUState *cpu); 216 217 /** 218 * @io_recompile_replay_branch: Callback for cpu_io_recompile. 219 * 220 * The cpu has been stopped, and cpu_restore_state_from_tb has been 221 * called. If the faulting instruction is in a delay slot, and the 222 * target architecture requires re-execution of the branch, then 223 * adjust the cpu state as required and return true. 224 */ 225 bool (*io_recompile_replay_branch)(CPUState *cpu, 226 const TranslationBlock *tb); 227 /** 228 * @need_replay_interrupt: Return %true if @interrupt_request 229 * needs to be recorded for replay purposes. 230 */ 231 bool (*need_replay_interrupt)(int interrupt_request); 232 #endif /* !CONFIG_USER_ONLY */ 233 }; 234 235 #if defined(CONFIG_USER_ONLY) 236 237 static inline void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, 238 MemTxAttrs atr, int fl, uintptr_t ra) 239 { 240 } 241 242 static inline int cpu_watchpoint_address_matches(CPUState *cpu, 243 vaddr addr, vaddr len) 244 { 245 return 0; 246 } 247 248 #else 249 250 /** 251 * cpu_check_watchpoint: 252 * @cpu: cpu context 253 * @addr: guest virtual address 254 * @len: access length 255 * @attrs: memory access attributes 256 * @flags: watchpoint access type 257 * @ra: unwind return address 258 * 259 * Check for a watchpoint hit in [addr, addr+len) of the type 260 * specified by @flags. Exit via exception with a hit. 261 */ 262 void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, 263 MemTxAttrs attrs, int flags, uintptr_t ra); 264 265 /** 266 * cpu_watchpoint_address_matches: 267 * @cpu: cpu context 268 * @addr: guest virtual address 269 * @len: access length 270 * 271 * Return the watchpoint flags that apply to [addr, addr+len). 272 * If no watchpoint is registered for the range, the result is 0. 273 */ 274 int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len); 275 276 #endif 277 278 #endif /* TCG_CPU_OPS_H */ 279