1 /* 2 * TCG CPU-specific operations 3 * 4 * Copyright 2021 SUSE LLC 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 10 #ifndef TCG_CPU_OPS_H 11 #define TCG_CPU_OPS_H 12 13 #include "exec/breakpoint.h" 14 #include "exec/hwaddr.h" 15 #include "exec/memattrs.h" 16 #include "exec/memop.h" 17 #include "exec/mmu-access-type.h" 18 #include "exec/vaddr.h" 19 #include "accel/tcg/tb-cpu-state.h" 20 #include "tcg/tcg-mo.h" 21 22 TCGTBCPUState cpu_get_tb_cpu_state(CPUState *cs); 23 24 struct TCGCPUOps { 25 /** 26 * mttcg_supported: multi-threaded TCG is supported 27 * 28 * Target (TCG frontend) supports: 29 * - atomic instructions 30 * - memory ordering primitives (barriers) 31 */ 32 bool mttcg_supported; 33 34 /** 35 * @precise_smc: Stores which modify code within the current TB force 36 * the TB to exit; the next executed instruction will see 37 * the result of the store. 38 */ 39 bool precise_smc; 40 41 /** 42 * @guest_default_memory_order: default barrier that is required 43 * for the guest memory ordering. 44 */ 45 TCGBar guest_default_memory_order; 46 47 /** 48 * @initialize: Initialize TCG state 49 * 50 * Called when the first CPU is realized. 51 */ 52 void (*initialize)(void); 53 /** 54 * @translate_code: Translate guest instructions to TCGOps 55 * @cpu: cpu context 56 * @tb: translation block 57 * @max_insns: max number of instructions to translate 58 * @pc: guest virtual program counter address 59 * @host_pc: host physical program counter address 60 * 61 * This function must be provided by the target, which should create 62 * the target-specific DisasContext, and then invoke translator_loop. 63 */ 64 void (*translate_code)(CPUState *cpu, TranslationBlock *tb, 65 int *max_insns, vaddr pc, void *host_pc); 66 /** 67 * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock 68 * 69 * This is called when we abandon execution of a TB before starting it, 70 * and must set all parts of the CPU state which the previous TB in the 71 * chain may not have updated. 72 * By default, when this is NULL, a call is made to @set_pc(tb->pc). 73 * 74 * If more state needs to be restored, the target must implement a 75 * function to restore all the state, and register it here. 76 */ 77 void (*synchronize_from_tb)(CPUState *cpu, const TranslationBlock *tb); 78 /** 79 * @restore_state_to_opc: Synchronize state from INDEX_op_start_insn 80 * 81 * This is called when we unwind state in the middle of a TB, 82 * usually before raising an exception. Set all part of the CPU 83 * state which are tracked insn-by-insn in the target-specific 84 * arguments to start_insn, passed as @data. 85 */ 86 void (*restore_state_to_opc)(CPUState *cpu, const TranslationBlock *tb, 87 const uint64_t *data); 88 89 /** @cpu_exec_enter: Callback for cpu_exec preparation */ 90 void (*cpu_exec_enter)(CPUState *cpu); 91 /** @cpu_exec_exit: Callback for cpu_exec cleanup */ 92 void (*cpu_exec_exit)(CPUState *cpu); 93 /** @debug_excp_handler: Callback for handling debug exceptions */ 94 void (*debug_excp_handler)(CPUState *cpu); 95 96 /** @mmu_index: Callback for choosing softmmu mmu index */ 97 int (*mmu_index)(CPUState *cpu, bool ifetch); 98 99 #ifdef CONFIG_USER_ONLY 100 /** 101 * @fake_user_interrupt: Callback for 'fake exception' handling. 102 * 103 * Simulate 'fake exception' which will be handled outside the 104 * cpu execution loop (hack for x86 user mode). 105 */ 106 void (*fake_user_interrupt)(CPUState *cpu); 107 108 /** 109 * record_sigsegv: 110 * @cpu: cpu context 111 * @addr: faulting guest address 112 * @access_type: access was read/write/execute 113 * @maperr: true for invalid page, false for permission fault 114 * @ra: host pc for unwinding 115 * 116 * We are about to raise SIGSEGV with si_code set for @maperr, 117 * and si_addr set for @addr. Record anything further needed 118 * for the signal ucontext_t. 119 * 120 * If the emulated kernel does not provide anything to the signal 121 * handler with anything besides the user context registers, and 122 * the siginfo_t, then this hook need do nothing and may be omitted. 123 * Otherwise, record the data and return; the caller will raise 124 * the signal, unwind the cpu state, and return to the main loop. 125 * 126 * If it is simpler to re-use the sysemu tlb_fill code, @ra is provided 127 * so that a "normal" cpu exception can be raised. In this case, 128 * the signal must be raised by the architecture cpu_loop. 129 */ 130 void (*record_sigsegv)(CPUState *cpu, vaddr addr, 131 MMUAccessType access_type, 132 bool maperr, uintptr_t ra); 133 /** 134 * record_sigbus: 135 * @cpu: cpu context 136 * @addr: misaligned guest address 137 * @access_type: access was read/write/execute 138 * @ra: host pc for unwinding 139 * 140 * We are about to raise SIGBUS with si_code BUS_ADRALN, 141 * and si_addr set for @addr. Record anything further needed 142 * for the signal ucontext_t. 143 * 144 * If the emulated kernel does not provide the signal handler with 145 * anything besides the user context registers, and the siginfo_t, 146 * then this hook need do nothing and may be omitted. 147 * Otherwise, record the data and return; the caller will raise 148 * the signal, unwind the cpu state, and return to the main loop. 149 * 150 * If it is simpler to re-use the sysemu do_unaligned_access code, 151 * @ra is provided so that a "normal" cpu exception can be raised. 152 * In this case, the signal must be raised by the architecture cpu_loop. 153 */ 154 void (*record_sigbus)(CPUState *cpu, vaddr addr, 155 MMUAccessType access_type, uintptr_t ra); 156 #else 157 /** @do_interrupt: Callback for interrupt handling. */ 158 void (*do_interrupt)(CPUState *cpu); 159 /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */ 160 bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); 161 /** @cpu_exec_reset: Callback for reset in cpu_exec. */ 162 void (*cpu_exec_reset)(CPUState *cpu); 163 /** 164 * @cpu_exec_halt: Callback for handling halt in cpu_exec. 165 * 166 * The target CPU should do any special processing here that it needs 167 * to do when the CPU is in the halted state. 168 * 169 * Return true to indicate that the CPU should now leave halt, false 170 * if it should remain in the halted state. (This should generally 171 * be the same value that cpu_has_work() would return.) 172 * 173 * This method must be provided. If the target does not need to 174 * do anything special for halt, the same function used for its 175 * SysemuCPUOps::has_work method can be used here, as they have the 176 * same function signature. 177 */ 178 bool (*cpu_exec_halt)(CPUState *cpu); 179 /** 180 * @tlb_fill_align: Handle a softmmu tlb miss 181 * @cpu: cpu context 182 * @out: output page properties 183 * @addr: virtual address 184 * @access_type: read, write or execute 185 * @mmu_idx: mmu context 186 * @memop: memory operation for the access 187 * @size: memory access size, or 0 for whole page 188 * @probe: test only, no fault 189 * @ra: host return address for exception unwind 190 * 191 * If the access is valid, fill in @out and return true. 192 * Otherwise if probe is true, return false. 193 * Otherwise raise an exception and do not return. 194 * 195 * The alignment check for the access is deferred to this hook, 196 * so that the target can determine the priority of any alignment 197 * fault with respect to other potential faults from paging. 198 * Zero may be passed for @memop to skip any alignment check 199 * for non-memory-access operations such as probing. 200 */ 201 bool (*tlb_fill_align)(CPUState *cpu, CPUTLBEntryFull *out, vaddr addr, 202 MMUAccessType access_type, int mmu_idx, 203 MemOp memop, int size, bool probe, uintptr_t ra); 204 /** 205 * @tlb_fill: Handle a softmmu tlb miss 206 * 207 * If the access is valid, call tlb_set_page and return true; 208 * if the access is invalid and probe is true, return false; 209 * otherwise raise an exception and do not return. 210 */ 211 bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, 212 MMUAccessType access_type, int mmu_idx, 213 bool probe, uintptr_t retaddr); 214 /** 215 * @do_transaction_failed: Callback for handling failed memory transactions 216 * (ie bus faults or external aborts; not MMU faults) 217 */ 218 void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr, 219 unsigned size, MMUAccessType access_type, 220 int mmu_idx, MemTxAttrs attrs, 221 MemTxResult response, uintptr_t retaddr); 222 /** 223 * @do_unaligned_access: Callback for unaligned access handling 224 * The callback must exit via raising an exception. 225 */ 226 G_NORETURN void (*do_unaligned_access)(CPUState *cpu, vaddr addr, 227 MMUAccessType access_type, 228 int mmu_idx, uintptr_t retaddr); 229 230 /** 231 * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM 232 */ 233 vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len); 234 235 /** 236 * @debug_check_watchpoint: return true if the architectural 237 * watchpoint whose address has matched should really fire, used by ARM 238 * and RISC-V 239 */ 240 bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); 241 242 /** 243 * @debug_check_breakpoint: return true if the architectural 244 * breakpoint whose PC has matched should really fire. 245 */ 246 bool (*debug_check_breakpoint)(CPUState *cpu); 247 248 /** 249 * @io_recompile_replay_branch: Callback for cpu_io_recompile. 250 * 251 * The cpu has been stopped, and cpu_restore_state_from_tb has been 252 * called. If the faulting instruction is in a delay slot, and the 253 * target architecture requires re-execution of the branch, then 254 * adjust the cpu state as required and return true. 255 */ 256 bool (*io_recompile_replay_branch)(CPUState *cpu, 257 const TranslationBlock *tb); 258 /** 259 * @need_replay_interrupt: Return %true if @interrupt_request 260 * needs to be recorded for replay purposes. 261 */ 262 bool (*need_replay_interrupt)(int interrupt_request); 263 #endif /* !CONFIG_USER_ONLY */ 264 }; 265 266 #if defined(CONFIG_USER_ONLY) 267 268 static inline void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, 269 MemTxAttrs atr, int fl, uintptr_t ra) 270 { 271 } 272 273 static inline int cpu_watchpoint_address_matches(CPUState *cpu, 274 vaddr addr, vaddr len) 275 { 276 return 0; 277 } 278 279 #else 280 281 /** 282 * cpu_check_watchpoint: 283 * @cpu: cpu context 284 * @addr: guest virtual address 285 * @len: access length 286 * @attrs: memory access attributes 287 * @flags: watchpoint access type 288 * @ra: unwind return address 289 * 290 * Check for a watchpoint hit in [addr, addr+len) of the type 291 * specified by @flags. Exit via exception with a hit. 292 */ 293 void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, 294 MemTxAttrs attrs, int flags, uintptr_t ra); 295 296 /** 297 * cpu_watchpoint_address_matches: 298 * @cpu: cpu context 299 * @addr: guest virtual address 300 * @len: access length 301 * 302 * Return the watchpoint flags that apply to [addr, addr+len). 303 * If no watchpoint is registered for the range, the result is 0. 304 */ 305 int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len); 306 307 #endif 308 309 #endif /* TCG_CPU_OPS_H */ 310