xref: /qemu/include/accel/tcg/cpu-ops.h (revision fa947a667fceab02f9f85fc99f54aebcc9ae6b51)
178271684SClaudio Fontana /*
278271684SClaudio Fontana  * TCG CPU-specific operations
378271684SClaudio Fontana  *
478271684SClaudio Fontana  * Copyright 2021 SUSE LLC
578271684SClaudio Fontana  *
678271684SClaudio Fontana  * This work is licensed under the terms of the GNU GPL, version 2 or later.
778271684SClaudio Fontana  * See the COPYING file in the top-level directory.
878271684SClaudio Fontana  */
978271684SClaudio Fontana 
1078271684SClaudio Fontana #ifndef TCG_CPU_OPS_H
1178271684SClaudio Fontana #define TCG_CPU_OPS_H
1278271684SClaudio Fontana 
1378271684SClaudio Fontana #include "hw/core/cpu.h"
1478271684SClaudio Fontana 
1578271684SClaudio Fontana struct TCGCPUOps {
1678271684SClaudio Fontana     /**
1778271684SClaudio Fontana      * @initialize: Initalize TCG state
1878271684SClaudio Fontana      *
1978271684SClaudio Fontana      * Called when the first CPU is realized.
2078271684SClaudio Fontana      */
2178271684SClaudio Fontana     void (*initialize)(void);
2278271684SClaudio Fontana     /**
2378271684SClaudio Fontana      * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock
2478271684SClaudio Fontana      *
2578271684SClaudio Fontana      * This is called when we abandon execution of a TB before starting it,
2678271684SClaudio Fontana      * and must set all parts of the CPU state which the previous TB in the
2778271684SClaudio Fontana      * chain may not have updated.
2878271684SClaudio Fontana      * By default, when this is NULL, a call is made to @set_pc(tb->pc).
2978271684SClaudio Fontana      *
3078271684SClaudio Fontana      * If more state needs to be restored, the target must implement a
3178271684SClaudio Fontana      * function to restore all the state, and register it here.
3278271684SClaudio Fontana      */
338349d2aeSRichard Henderson     void (*synchronize_from_tb)(CPUState *cpu, const TranslationBlock *tb);
3478271684SClaudio Fontana     /** @cpu_exec_enter: Callback for cpu_exec preparation */
3578271684SClaudio Fontana     void (*cpu_exec_enter)(CPUState *cpu);
3678271684SClaudio Fontana     /** @cpu_exec_exit: Callback for cpu_exec cleanup */
3778271684SClaudio Fontana     void (*cpu_exec_exit)(CPUState *cpu);
3878271684SClaudio Fontana     /**
3978271684SClaudio Fontana      * @tlb_fill: Handle a softmmu tlb miss or user-only address fault
4078271684SClaudio Fontana      *
4178271684SClaudio Fontana      * For system mode, if the access is valid, call tlb_set_page
4278271684SClaudio Fontana      * and return true; if the access is invalid, and probe is
4378271684SClaudio Fontana      * true, return false; otherwise raise an exception and do
4478271684SClaudio Fontana      * not return.  For user-only mode, always raise an exception
4578271684SClaudio Fontana      * and do not return.
4678271684SClaudio Fontana      */
4778271684SClaudio Fontana     bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
4878271684SClaudio Fontana                      MMUAccessType access_type, int mmu_idx,
4978271684SClaudio Fontana                      bool probe, uintptr_t retaddr);
5078271684SClaudio Fontana     /** @debug_excp_handler: Callback for handling debug exceptions */
5178271684SClaudio Fontana     void (*debug_excp_handler)(CPUState *cpu);
5278271684SClaudio Fontana 
5378271684SClaudio Fontana #ifdef NEED_CPU_H
5412096421SPhilippe Mathieu-Daudé #if defined(CONFIG_USER_ONLY) && defined(TARGET_I386)
5512096421SPhilippe Mathieu-Daudé     /**
5612096421SPhilippe Mathieu-Daudé      * @fake_user_interrupt: Callback for 'fake exception' handling.
5712096421SPhilippe Mathieu-Daudé      *
5812096421SPhilippe Mathieu-Daudé      * Simulate 'fake exception' which will be handled outside the
5912096421SPhilippe Mathieu-Daudé      * cpu execution loop (hack for x86 user mode).
6012096421SPhilippe Mathieu-Daudé      */
6112096421SPhilippe Mathieu-Daudé     void (*fake_user_interrupt)(CPUState *cpu);
6212096421SPhilippe Mathieu-Daudé #else
6312096421SPhilippe Mathieu-Daudé     /**
6412096421SPhilippe Mathieu-Daudé      * @do_interrupt: Callback for interrupt handling.
6512096421SPhilippe Mathieu-Daudé      */
6612096421SPhilippe Mathieu-Daudé     void (*do_interrupt)(CPUState *cpu);
6712096421SPhilippe Mathieu-Daudé #endif /* !CONFIG_USER_ONLY || !TARGET_I386 */
6878271684SClaudio Fontana #ifdef CONFIG_SOFTMMU
6977c0fc4eSPhilippe Mathieu-Daudé     /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
7077c0fc4eSPhilippe Mathieu-Daudé     bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
7178271684SClaudio Fontana     /**
7278271684SClaudio Fontana      * @do_transaction_failed: Callback for handling failed memory transactions
7378271684SClaudio Fontana      * (ie bus faults or external aborts; not MMU faults)
7478271684SClaudio Fontana      */
7578271684SClaudio Fontana     void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
7678271684SClaudio Fontana                                   unsigned size, MMUAccessType access_type,
7778271684SClaudio Fontana                                   int mmu_idx, MemTxAttrs attrs,
7878271684SClaudio Fontana                                   MemTxResult response, uintptr_t retaddr);
7978271684SClaudio Fontana     /**
8078271684SClaudio Fontana      * @do_unaligned_access: Callback for unaligned access handling
81*fa947a66SRichard Henderson      * The callback must exit via raising an exception.
8278271684SClaudio Fontana      */
8378271684SClaudio Fontana     void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
8478271684SClaudio Fontana                                 MMUAccessType access_type,
85*fa947a66SRichard Henderson                                 int mmu_idx, uintptr_t retaddr) QEMU_NORETURN;
8678271684SClaudio Fontana 
8778271684SClaudio Fontana     /**
8878271684SClaudio Fontana      * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM
8978271684SClaudio Fontana      */
9078271684SClaudio Fontana     vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
9178271684SClaudio Fontana 
9278271684SClaudio Fontana     /**
9378271684SClaudio Fontana      * @debug_check_watchpoint: return true if the architectural
9478271684SClaudio Fontana      * watchpoint whose address has matched should really fire, used by ARM
9578271684SClaudio Fontana      */
9678271684SClaudio Fontana     bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
9778271684SClaudio Fontana 
98d9bcb58aSRichard Henderson     /**
99e3f7c801SRichard Henderson      * @debug_check_breakpoint: return true if the architectural
100e3f7c801SRichard Henderson      * breakpoint whose PC has matched should really fire.
101e3f7c801SRichard Henderson      */
102e3f7c801SRichard Henderson     bool (*debug_check_breakpoint)(CPUState *cpu);
103e3f7c801SRichard Henderson 
104e3f7c801SRichard Henderson     /**
105d9bcb58aSRichard Henderson      * @io_recompile_replay_branch: Callback for cpu_io_recompile.
106d9bcb58aSRichard Henderson      *
107d9bcb58aSRichard Henderson      * The cpu has been stopped, and cpu_restore_state_from_tb has been
108d9bcb58aSRichard Henderson      * called.  If the faulting instruction is in a delay slot, and the
109d9bcb58aSRichard Henderson      * target architecture requires re-execution of the branch, then
110d9bcb58aSRichard Henderson      * adjust the cpu state as required and return true.
111d9bcb58aSRichard Henderson      */
112d9bcb58aSRichard Henderson     bool (*io_recompile_replay_branch)(CPUState *cpu,
113d9bcb58aSRichard Henderson                                        const TranslationBlock *tb);
11478271684SClaudio Fontana #endif /* CONFIG_SOFTMMU */
11578271684SClaudio Fontana #endif /* NEED_CPU_H */
11678271684SClaudio Fontana 
11778271684SClaudio Fontana };
11878271684SClaudio Fontana 
11978271684SClaudio Fontana #endif /* TCG_CPU_OPS_H */
120