xref: /qemu/include/accel/tcg/cpu-ops.h (revision e4a8e093dc74be049f4829831dce76e5edab0003)
178271684SClaudio Fontana /*
278271684SClaudio Fontana  * TCG CPU-specific operations
378271684SClaudio Fontana  *
478271684SClaudio Fontana  * Copyright 2021 SUSE LLC
578271684SClaudio Fontana  *
678271684SClaudio Fontana  * This work is licensed under the terms of the GNU GPL, version 2 or later.
778271684SClaudio Fontana  * See the COPYING file in the top-level directory.
878271684SClaudio Fontana  */
978271684SClaudio Fontana 
1078271684SClaudio Fontana #ifndef TCG_CPU_OPS_H
1178271684SClaudio Fontana #define TCG_CPU_OPS_H
1278271684SClaudio Fontana 
1376d07d32SPhilippe Mathieu-Daudé #include "exec/breakpoint.h"
1476d07d32SPhilippe Mathieu-Daudé #include "exec/hwaddr.h"
1576d07d32SPhilippe Mathieu-Daudé #include "exec/memattrs.h"
16f168808dSRichard Henderson #include "exec/memop.h"
1776d07d32SPhilippe Mathieu-Daudé #include "exec/mmu-access-type.h"
1876d07d32SPhilippe Mathieu-Daudé #include "exec/vaddr.h"
1978271684SClaudio Fontana 
2078271684SClaudio Fontana struct TCGCPUOps {
2178271684SClaudio Fontana     /**
22669dcb60SMichael Tokarev      * @initialize: Initialize TCG state
2378271684SClaudio Fontana      *
2478271684SClaudio Fontana      * Called when the first CPU is realized.
2578271684SClaudio Fontana      */
2678271684SClaudio Fontana     void (*initialize)(void);
2778271684SClaudio Fontana     /**
28*e4a8e093SRichard Henderson      * @translate_code: Translate guest instructions to TCGOps
29*e4a8e093SRichard Henderson      * @cpu: cpu context
30*e4a8e093SRichard Henderson      * @tb: translation block
31*e4a8e093SRichard Henderson      * @max_insns: max number of instructions to translate
32*e4a8e093SRichard Henderson      * @pc: guest virtual program counter address
33*e4a8e093SRichard Henderson      * @host_pc: host physical program counter address
34*e4a8e093SRichard Henderson      *
35*e4a8e093SRichard Henderson      * This function must be provided by the target, which should create
36*e4a8e093SRichard Henderson      * the target-specific DisasContext, and then invoke translator_loop.
37*e4a8e093SRichard Henderson      */
38*e4a8e093SRichard Henderson     void (*translate_code)(CPUState *cpu, TranslationBlock *tb,
39*e4a8e093SRichard Henderson                            int *max_insns, vaddr pc, void *host_pc);
40*e4a8e093SRichard Henderson     /**
4178271684SClaudio Fontana      * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock
4278271684SClaudio Fontana      *
4378271684SClaudio Fontana      * This is called when we abandon execution of a TB before starting it,
4478271684SClaudio Fontana      * and must set all parts of the CPU state which the previous TB in the
4578271684SClaudio Fontana      * chain may not have updated.
4678271684SClaudio Fontana      * By default, when this is NULL, a call is made to @set_pc(tb->pc).
4778271684SClaudio Fontana      *
4878271684SClaudio Fontana      * If more state needs to be restored, the target must implement a
4978271684SClaudio Fontana      * function to restore all the state, and register it here.
5078271684SClaudio Fontana      */
518349d2aeSRichard Henderson     void (*synchronize_from_tb)(CPUState *cpu, const TranslationBlock *tb);
52d2925689SRichard Henderson     /**
53d2925689SRichard Henderson      * @restore_state_to_opc: Synchronize state from INDEX_op_start_insn
54d2925689SRichard Henderson      *
55d2925689SRichard Henderson      * This is called when we unwind state in the middle of a TB,
56d2925689SRichard Henderson      * usually before raising an exception.  Set all part of the CPU
57d2925689SRichard Henderson      * state which are tracked insn-by-insn in the target-specific
58d2925689SRichard Henderson      * arguments to start_insn, passed as @data.
59d2925689SRichard Henderson      */
60d2925689SRichard Henderson     void (*restore_state_to_opc)(CPUState *cpu, const TranslationBlock *tb,
61d2925689SRichard Henderson                                  const uint64_t *data);
62d2925689SRichard Henderson 
6378271684SClaudio Fontana     /** @cpu_exec_enter: Callback for cpu_exec preparation */
6478271684SClaudio Fontana     void (*cpu_exec_enter)(CPUState *cpu);
6578271684SClaudio Fontana     /** @cpu_exec_exit: Callback for cpu_exec cleanup */
6678271684SClaudio Fontana     void (*cpu_exec_exit)(CPUState *cpu);
6778271684SClaudio Fontana     /** @debug_excp_handler: Callback for handling debug exceptions */
6878271684SClaudio Fontana     void (*debug_excp_handler)(CPUState *cpu);
6978271684SClaudio Fontana 
70fd3f7d24SAnton Johansson #ifdef CONFIG_USER_ONLY
7112096421SPhilippe Mathieu-Daudé     /**
7212096421SPhilippe Mathieu-Daudé      * @fake_user_interrupt: Callback for 'fake exception' handling.
7312096421SPhilippe Mathieu-Daudé      *
7412096421SPhilippe Mathieu-Daudé      * Simulate 'fake exception' which will be handled outside the
7512096421SPhilippe Mathieu-Daudé      * cpu execution loop (hack for x86 user mode).
7612096421SPhilippe Mathieu-Daudé      */
7712096421SPhilippe Mathieu-Daudé     void (*fake_user_interrupt)(CPUState *cpu);
78fd3f7d24SAnton Johansson 
7975fe97b4SPhilippe Mathieu-Daudé     /**
8075fe97b4SPhilippe Mathieu-Daudé      * record_sigsegv:
8175fe97b4SPhilippe Mathieu-Daudé      * @cpu: cpu context
8275fe97b4SPhilippe Mathieu-Daudé      * @addr: faulting guest address
8375fe97b4SPhilippe Mathieu-Daudé      * @access_type: access was read/write/execute
8475fe97b4SPhilippe Mathieu-Daudé      * @maperr: true for invalid page, false for permission fault
8575fe97b4SPhilippe Mathieu-Daudé      * @ra: host pc for unwinding
8675fe97b4SPhilippe Mathieu-Daudé      *
8775fe97b4SPhilippe Mathieu-Daudé      * We are about to raise SIGSEGV with si_code set for @maperr,
8875fe97b4SPhilippe Mathieu-Daudé      * and si_addr set for @addr.  Record anything further needed
8975fe97b4SPhilippe Mathieu-Daudé      * for the signal ucontext_t.
9075fe97b4SPhilippe Mathieu-Daudé      *
9175fe97b4SPhilippe Mathieu-Daudé      * If the emulated kernel does not provide anything to the signal
9275fe97b4SPhilippe Mathieu-Daudé      * handler with anything besides the user context registers, and
9375fe97b4SPhilippe Mathieu-Daudé      * the siginfo_t, then this hook need do nothing and may be omitted.
9475fe97b4SPhilippe Mathieu-Daudé      * Otherwise, record the data and return; the caller will raise
9575fe97b4SPhilippe Mathieu-Daudé      * the signal, unwind the cpu state, and return to the main loop.
9675fe97b4SPhilippe Mathieu-Daudé      *
9775fe97b4SPhilippe Mathieu-Daudé      * If it is simpler to re-use the sysemu tlb_fill code, @ra is provided
9875fe97b4SPhilippe Mathieu-Daudé      * so that a "normal" cpu exception can be raised.  In this case,
9975fe97b4SPhilippe Mathieu-Daudé      * the signal must be raised by the architecture cpu_loop.
10075fe97b4SPhilippe Mathieu-Daudé      */
10175fe97b4SPhilippe Mathieu-Daudé     void (*record_sigsegv)(CPUState *cpu, vaddr addr,
10275fe97b4SPhilippe Mathieu-Daudé                            MMUAccessType access_type,
10375fe97b4SPhilippe Mathieu-Daudé                            bool maperr, uintptr_t ra);
10475fe97b4SPhilippe Mathieu-Daudé     /**
10575fe97b4SPhilippe Mathieu-Daudé      * record_sigbus:
10675fe97b4SPhilippe Mathieu-Daudé      * @cpu: cpu context
10775fe97b4SPhilippe Mathieu-Daudé      * @addr: misaligned guest address
10875fe97b4SPhilippe Mathieu-Daudé      * @access_type: access was read/write/execute
10975fe97b4SPhilippe Mathieu-Daudé      * @ra: host pc for unwinding
11075fe97b4SPhilippe Mathieu-Daudé      *
11175fe97b4SPhilippe Mathieu-Daudé      * We are about to raise SIGBUS with si_code BUS_ADRALN,
11275fe97b4SPhilippe Mathieu-Daudé      * and si_addr set for @addr.  Record anything further needed
11375fe97b4SPhilippe Mathieu-Daudé      * for the signal ucontext_t.
11475fe97b4SPhilippe Mathieu-Daudé      *
11575fe97b4SPhilippe Mathieu-Daudé      * If the emulated kernel does not provide the signal handler with
11675fe97b4SPhilippe Mathieu-Daudé      * anything besides the user context registers, and the siginfo_t,
11775fe97b4SPhilippe Mathieu-Daudé      * then this hook need do nothing and may be omitted.
11875fe97b4SPhilippe Mathieu-Daudé      * Otherwise, record the data and return; the caller will raise
11975fe97b4SPhilippe Mathieu-Daudé      * the signal, unwind the cpu state, and return to the main loop.
12075fe97b4SPhilippe Mathieu-Daudé      *
12175fe97b4SPhilippe Mathieu-Daudé      * If it is simpler to re-use the sysemu do_unaligned_access code,
12275fe97b4SPhilippe Mathieu-Daudé      * @ra is provided so that a "normal" cpu exception can be raised.
12375fe97b4SPhilippe Mathieu-Daudé      * In this case, the signal must be raised by the architecture cpu_loop.
12475fe97b4SPhilippe Mathieu-Daudé      */
12575fe97b4SPhilippe Mathieu-Daudé     void (*record_sigbus)(CPUState *cpu, vaddr addr,
12675fe97b4SPhilippe Mathieu-Daudé                           MMUAccessType access_type, uintptr_t ra);
12775fe97b4SPhilippe Mathieu-Daudé #else
128b11cdf27SAnton Johansson     /** @do_interrupt: Callback for interrupt handling.  */
129b11cdf27SAnton Johansson     void (*do_interrupt)(CPUState *cpu);
13077c0fc4eSPhilippe Mathieu-Daudé     /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
13177c0fc4eSPhilippe Mathieu-Daudé     bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
132408b2b3dSPeter Maydell     /**
133408b2b3dSPeter Maydell      * @cpu_exec_halt: Callback for handling halt in cpu_exec.
134408b2b3dSPeter Maydell      *
135408b2b3dSPeter Maydell      * The target CPU should do any special processing here that it needs
136408b2b3dSPeter Maydell      * to do when the CPU is in the halted state.
137408b2b3dSPeter Maydell      *
138408b2b3dSPeter Maydell      * Return true to indicate that the CPU should now leave halt, false
1390487c631SPeter Maydell      * if it should remain in the halted state. (This should generally
1400487c631SPeter Maydell      * be the same value that cpu_has_work() would return.)
141408b2b3dSPeter Maydell      *
1420487c631SPeter Maydell      * This method must be provided. If the target does not need to
1430487c631SPeter Maydell      * do anything special for halt, the same function used for its
1440487c631SPeter Maydell      * CPUClass::has_work method can be used here, as they have the
1450487c631SPeter Maydell      * same function signature.
146408b2b3dSPeter Maydell      */
147408b2b3dSPeter Maydell     bool (*cpu_exec_halt)(CPUState *cpu);
14878271684SClaudio Fontana     /**
149f168808dSRichard Henderson      * @tlb_fill_align: Handle a softmmu tlb miss
150f168808dSRichard Henderson      * @cpu: cpu context
151f168808dSRichard Henderson      * @out: output page properties
152f168808dSRichard Henderson      * @addr: virtual address
153f168808dSRichard Henderson      * @access_type: read, write or execute
154f168808dSRichard Henderson      * @mmu_idx: mmu context
155f168808dSRichard Henderson      * @memop: memory operation for the access
156f168808dSRichard Henderson      * @size: memory access size, or 0 for whole page
157f168808dSRichard Henderson      * @probe: test only, no fault
158f168808dSRichard Henderson      * @ra: host return address for exception unwind
159f168808dSRichard Henderson      *
160f168808dSRichard Henderson      * If the access is valid, fill in @out and return true.
161f168808dSRichard Henderson      * Otherwise if probe is true, return false.
162f168808dSRichard Henderson      * Otherwise raise an exception and do not return.
163f168808dSRichard Henderson      *
164f168808dSRichard Henderson      * The alignment check for the access is deferred to this hook,
165f168808dSRichard Henderson      * so that the target can determine the priority of any alignment
166f168808dSRichard Henderson      * fault with respect to other potential faults from paging.
167f168808dSRichard Henderson      * Zero may be passed for @memop to skip any alignment check
168f168808dSRichard Henderson      * for non-memory-access operations such as probing.
169f168808dSRichard Henderson      */
170f168808dSRichard Henderson     bool (*tlb_fill_align)(CPUState *cpu, CPUTLBEntryFull *out, vaddr addr,
171f168808dSRichard Henderson                            MMUAccessType access_type, int mmu_idx,
172f168808dSRichard Henderson                            MemOp memop, int size, bool probe, uintptr_t ra);
173f168808dSRichard Henderson     /**
174eeca7dc5SRichard Henderson      * @tlb_fill: Handle a softmmu tlb miss
175eeca7dc5SRichard Henderson      *
176eeca7dc5SRichard Henderson      * If the access is valid, call tlb_set_page and return true;
177eeca7dc5SRichard Henderson      * if the access is invalid and probe is true, return false;
178eeca7dc5SRichard Henderson      * otherwise raise an exception and do not return.
179eeca7dc5SRichard Henderson      */
180eeca7dc5SRichard Henderson     bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
181eeca7dc5SRichard Henderson                      MMUAccessType access_type, int mmu_idx,
182eeca7dc5SRichard Henderson                      bool probe, uintptr_t retaddr);
183eeca7dc5SRichard Henderson     /**
18478271684SClaudio Fontana      * @do_transaction_failed: Callback for handling failed memory transactions
18578271684SClaudio Fontana      * (ie bus faults or external aborts; not MMU faults)
18678271684SClaudio Fontana      */
18778271684SClaudio Fontana     void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
18878271684SClaudio Fontana                                   unsigned size, MMUAccessType access_type,
18978271684SClaudio Fontana                                   int mmu_idx, MemTxAttrs attrs,
19078271684SClaudio Fontana                                   MemTxResult response, uintptr_t retaddr);
19178271684SClaudio Fontana     /**
19278271684SClaudio Fontana      * @do_unaligned_access: Callback for unaligned access handling
193fa947a66SRichard Henderson      * The callback must exit via raising an exception.
19478271684SClaudio Fontana      */
1958905770bSMarc-André Lureau     G_NORETURN void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
19678271684SClaudio Fontana                                            MMUAccessType access_type,
1978905770bSMarc-André Lureau                                            int mmu_idx, uintptr_t retaddr);
19878271684SClaudio Fontana 
19978271684SClaudio Fontana     /**
20078271684SClaudio Fontana      * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM
20178271684SClaudio Fontana      */
20278271684SClaudio Fontana     vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
20378271684SClaudio Fontana 
20478271684SClaudio Fontana     /**
20578271684SClaudio Fontana      * @debug_check_watchpoint: return true if the architectural
20678271684SClaudio Fontana      * watchpoint whose address has matched should really fire, used by ARM
207013577deSBin Meng      * and RISC-V
20878271684SClaudio Fontana      */
20978271684SClaudio Fontana     bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
21078271684SClaudio Fontana 
211d9bcb58aSRichard Henderson     /**
212e3f7c801SRichard Henderson      * @debug_check_breakpoint: return true if the architectural
213e3f7c801SRichard Henderson      * breakpoint whose PC has matched should really fire.
214e3f7c801SRichard Henderson      */
215e3f7c801SRichard Henderson     bool (*debug_check_breakpoint)(CPUState *cpu);
216e3f7c801SRichard Henderson 
217e3f7c801SRichard Henderson     /**
218d9bcb58aSRichard Henderson      * @io_recompile_replay_branch: Callback for cpu_io_recompile.
219d9bcb58aSRichard Henderson      *
220d9bcb58aSRichard Henderson      * The cpu has been stopped, and cpu_restore_state_from_tb has been
221d9bcb58aSRichard Henderson      * called.  If the faulting instruction is in a delay slot, and the
222d9bcb58aSRichard Henderson      * target architecture requires re-execution of the branch, then
223d9bcb58aSRichard Henderson      * adjust the cpu state as required and return true.
224d9bcb58aSRichard Henderson      */
225d9bcb58aSRichard Henderson     bool (*io_recompile_replay_branch)(CPUState *cpu,
226d9bcb58aSRichard Henderson                                        const TranslationBlock *tb);
2270fdc69b7SPhilippe Mathieu-Daudé     /**
2280fdc69b7SPhilippe Mathieu-Daudé      * @need_replay_interrupt: Return %true if @interrupt_request
2290fdc69b7SPhilippe Mathieu-Daudé      * needs to be recorded for replay purposes.
2300fdc69b7SPhilippe Mathieu-Daudé      */
2310fdc69b7SPhilippe Mathieu-Daudé     bool (*need_replay_interrupt)(int interrupt_request);
23275fe97b4SPhilippe Mathieu-Daudé #endif /* !CONFIG_USER_ONLY */
23378271684SClaudio Fontana };
23478271684SClaudio Fontana 
2356eece7f5SPhilippe Mathieu-Daudé #if defined(CONFIG_USER_ONLY)
2366eece7f5SPhilippe Mathieu-Daudé 
2376eece7f5SPhilippe Mathieu-Daudé static inline void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
2386eece7f5SPhilippe Mathieu-Daudé                                         MemTxAttrs atr, int fl, uintptr_t ra)
2396eece7f5SPhilippe Mathieu-Daudé {
2406eece7f5SPhilippe Mathieu-Daudé }
2416eece7f5SPhilippe Mathieu-Daudé 
2426eece7f5SPhilippe Mathieu-Daudé static inline int cpu_watchpoint_address_matches(CPUState *cpu,
2436eece7f5SPhilippe Mathieu-Daudé                                                  vaddr addr, vaddr len)
2446eece7f5SPhilippe Mathieu-Daudé {
2456eece7f5SPhilippe Mathieu-Daudé     return 0;
2466eece7f5SPhilippe Mathieu-Daudé }
2476eece7f5SPhilippe Mathieu-Daudé 
2486eece7f5SPhilippe Mathieu-Daudé #else
2496eece7f5SPhilippe Mathieu-Daudé 
2506eece7f5SPhilippe Mathieu-Daudé /**
2516eece7f5SPhilippe Mathieu-Daudé  * cpu_check_watchpoint:
2526eece7f5SPhilippe Mathieu-Daudé  * @cpu: cpu context
2536eece7f5SPhilippe Mathieu-Daudé  * @addr: guest virtual address
2546eece7f5SPhilippe Mathieu-Daudé  * @len: access length
2556eece7f5SPhilippe Mathieu-Daudé  * @attrs: memory access attributes
2566eece7f5SPhilippe Mathieu-Daudé  * @flags: watchpoint access type
2576eece7f5SPhilippe Mathieu-Daudé  * @ra: unwind return address
2586eece7f5SPhilippe Mathieu-Daudé  *
2596eece7f5SPhilippe Mathieu-Daudé  * Check for a watchpoint hit in [addr, addr+len) of the type
2606eece7f5SPhilippe Mathieu-Daudé  * specified by @flags.  Exit via exception with a hit.
2616eece7f5SPhilippe Mathieu-Daudé  */
2626eece7f5SPhilippe Mathieu-Daudé void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
2636eece7f5SPhilippe Mathieu-Daudé                           MemTxAttrs attrs, int flags, uintptr_t ra);
2646eece7f5SPhilippe Mathieu-Daudé 
2656eece7f5SPhilippe Mathieu-Daudé /**
2666eece7f5SPhilippe Mathieu-Daudé  * cpu_watchpoint_address_matches:
2676eece7f5SPhilippe Mathieu-Daudé  * @cpu: cpu context
2686eece7f5SPhilippe Mathieu-Daudé  * @addr: guest virtual address
2696eece7f5SPhilippe Mathieu-Daudé  * @len: access length
2706eece7f5SPhilippe Mathieu-Daudé  *
2716eece7f5SPhilippe Mathieu-Daudé  * Return the watchpoint flags that apply to [addr, addr+len).
2726eece7f5SPhilippe Mathieu-Daudé  * If no watchpoint is registered for the range, the result is 0.
2736eece7f5SPhilippe Mathieu-Daudé  */
2746eece7f5SPhilippe Mathieu-Daudé int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len);
2756eece7f5SPhilippe Mathieu-Daudé 
2766eece7f5SPhilippe Mathieu-Daudé #endif
2776eece7f5SPhilippe Mathieu-Daudé 
27878271684SClaudio Fontana #endif /* TCG_CPU_OPS_H */
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