xref: /qemu/hw/xtensa/virt.c (revision d9e8553bc8821d72cb72ca95f76b2d8ff6eb628a)
1*d9e8553bSMax Filippov /*
2*d9e8553bSMax Filippov  * Copyright (c) 2019, Max Filippov, Open Source and Linux Lab.
3*d9e8553bSMax Filippov  * All rights reserved.
4*d9e8553bSMax Filippov  *
5*d9e8553bSMax Filippov  * Redistribution and use in source and binary forms, with or without
6*d9e8553bSMax Filippov  * modification, are permitted provided that the following conditions are met:
7*d9e8553bSMax Filippov  *     * Redistributions of source code must retain the above copyright
8*d9e8553bSMax Filippov  *       notice, this list of conditions and the following disclaimer.
9*d9e8553bSMax Filippov  *     * Redistributions in binary form must reproduce the above copyright
10*d9e8553bSMax Filippov  *       notice, this list of conditions and the following disclaimer in the
11*d9e8553bSMax Filippov  *       documentation and/or other materials provided with the distribution.
12*d9e8553bSMax Filippov  *     * Neither the name of the Open Source and Linux Lab nor the
13*d9e8553bSMax Filippov  *       names of its contributors may be used to endorse or promote products
14*d9e8553bSMax Filippov  *       derived from this software without specific prior written permission.
15*d9e8553bSMax Filippov  *
16*d9e8553bSMax Filippov  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17*d9e8553bSMax Filippov  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18*d9e8553bSMax Filippov  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19*d9e8553bSMax Filippov  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20*d9e8553bSMax Filippov  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21*d9e8553bSMax Filippov  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22*d9e8553bSMax Filippov  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23*d9e8553bSMax Filippov  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24*d9e8553bSMax Filippov  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25*d9e8553bSMax Filippov  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26*d9e8553bSMax Filippov  */
27*d9e8553bSMax Filippov 
28*d9e8553bSMax Filippov #include "qemu/osdep.h"
29*d9e8553bSMax Filippov #include "qapi/error.h"
30*d9e8553bSMax Filippov #include "cpu.h"
31*d9e8553bSMax Filippov #include "sysemu/reset.h"
32*d9e8553bSMax Filippov #include "sysemu/sysemu.h"
33*d9e8553bSMax Filippov #include "hw/boards.h"
34*d9e8553bSMax Filippov #include "hw/loader.h"
35*d9e8553bSMax Filippov #include "hw/pci-host/gpex.h"
36*d9e8553bSMax Filippov #include "net/net.h"
37*d9e8553bSMax Filippov #include "elf.h"
38*d9e8553bSMax Filippov #include "exec/memory.h"
39*d9e8553bSMax Filippov #include "exec/address-spaces.h"
40*d9e8553bSMax Filippov #include "qemu/error-report.h"
41*d9e8553bSMax Filippov #include "xtensa_memory.h"
42*d9e8553bSMax Filippov #include "xtensa_sim.h"
43*d9e8553bSMax Filippov 
44*d9e8553bSMax Filippov static void create_pcie(CPUXtensaState *env, int irq_base, hwaddr addr_base)
45*d9e8553bSMax Filippov {
46*d9e8553bSMax Filippov     hwaddr base_ecam = addr_base + 0x00100000;
47*d9e8553bSMax Filippov     hwaddr size_ecam =             0x03f00000;
48*d9e8553bSMax Filippov     hwaddr base_pio  = addr_base + 0x00000000;
49*d9e8553bSMax Filippov     hwaddr size_pio  =             0x00010000;
50*d9e8553bSMax Filippov     hwaddr base_mmio = addr_base + 0x04000000;
51*d9e8553bSMax Filippov     hwaddr size_mmio =             0x08000000;
52*d9e8553bSMax Filippov 
53*d9e8553bSMax Filippov     MemoryRegion *ecam_alias;
54*d9e8553bSMax Filippov     MemoryRegion *ecam_reg;
55*d9e8553bSMax Filippov     MemoryRegion *pio_alias;
56*d9e8553bSMax Filippov     MemoryRegion *pio_reg;
57*d9e8553bSMax Filippov     MemoryRegion *mmio_alias;
58*d9e8553bSMax Filippov     MemoryRegion *mmio_reg;
59*d9e8553bSMax Filippov 
60*d9e8553bSMax Filippov     DeviceState *dev;
61*d9e8553bSMax Filippov     PCIHostState *pci;
62*d9e8553bSMax Filippov     qemu_irq *extints;
63*d9e8553bSMax Filippov     int i;
64*d9e8553bSMax Filippov 
65*d9e8553bSMax Filippov     dev = qdev_create(NULL, TYPE_GPEX_HOST);
66*d9e8553bSMax Filippov     qdev_init_nofail(dev);
67*d9e8553bSMax Filippov 
68*d9e8553bSMax Filippov     /* Map only the first size_ecam bytes of ECAM space. */
69*d9e8553bSMax Filippov     ecam_alias = g_new0(MemoryRegion, 1);
70*d9e8553bSMax Filippov     ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
71*d9e8553bSMax Filippov     memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
72*d9e8553bSMax Filippov                              ecam_reg, 0, size_ecam);
73*d9e8553bSMax Filippov     memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
74*d9e8553bSMax Filippov 
75*d9e8553bSMax Filippov     /*
76*d9e8553bSMax Filippov      * Map the MMIO window into system address space so as to expose
77*d9e8553bSMax Filippov      * the section of PCI MMIO space which starts at the same base address
78*d9e8553bSMax Filippov      * (ie 1:1 mapping for that part of PCI MMIO space visible through
79*d9e8553bSMax Filippov      * the window).
80*d9e8553bSMax Filippov      */
81*d9e8553bSMax Filippov     mmio_alias = g_new0(MemoryRegion, 1);
82*d9e8553bSMax Filippov     mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
83*d9e8553bSMax Filippov     memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
84*d9e8553bSMax Filippov                              mmio_reg, base_mmio, size_mmio);
85*d9e8553bSMax Filippov     memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
86*d9e8553bSMax Filippov 
87*d9e8553bSMax Filippov     /* Map IO port space. */
88*d9e8553bSMax Filippov     pio_alias = g_new0(MemoryRegion, 1);
89*d9e8553bSMax Filippov     pio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 2);
90*d9e8553bSMax Filippov     memory_region_init_alias(pio_alias, OBJECT(dev), "pcie-pio",
91*d9e8553bSMax Filippov                              pio_reg, 0, size_pio);
92*d9e8553bSMax Filippov     memory_region_add_subregion(get_system_memory(), base_pio, pio_alias);
93*d9e8553bSMax Filippov 
94*d9e8553bSMax Filippov     /* Connect IRQ lines. */
95*d9e8553bSMax Filippov     extints = xtensa_get_extints(env);
96*d9e8553bSMax Filippov 
97*d9e8553bSMax Filippov     for (i = 0; i < GPEX_NUM_IRQS; i++) {
98*d9e8553bSMax Filippov         void *q = extints[irq_base + i];
99*d9e8553bSMax Filippov 
100*d9e8553bSMax Filippov         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, q);
101*d9e8553bSMax Filippov         gpex_set_irq_num(GPEX_HOST(dev), i, irq_base + i);
102*d9e8553bSMax Filippov     }
103*d9e8553bSMax Filippov 
104*d9e8553bSMax Filippov     pci = PCI_HOST_BRIDGE(dev);
105*d9e8553bSMax Filippov     if (pci->bus) {
106*d9e8553bSMax Filippov         for (i = 0; i < nb_nics; i++) {
107*d9e8553bSMax Filippov             NICInfo *nd = &nd_table[i];
108*d9e8553bSMax Filippov 
109*d9e8553bSMax Filippov             if (!nd->model) {
110*d9e8553bSMax Filippov                 nd->model = g_strdup("virtio");
111*d9e8553bSMax Filippov             }
112*d9e8553bSMax Filippov 
113*d9e8553bSMax Filippov             pci_nic_init_nofail(nd, pci->bus, nd->model, NULL);
114*d9e8553bSMax Filippov         }
115*d9e8553bSMax Filippov     }
116*d9e8553bSMax Filippov }
117*d9e8553bSMax Filippov 
118*d9e8553bSMax Filippov static void xtensa_virt_init(MachineState *machine)
119*d9e8553bSMax Filippov {
120*d9e8553bSMax Filippov     XtensaCPU *cpu = xtensa_sim_common_init(machine);
121*d9e8553bSMax Filippov     CPUXtensaState *env = &cpu->env;
122*d9e8553bSMax Filippov 
123*d9e8553bSMax Filippov     create_pcie(env, 0, 0xf0000000);
124*d9e8553bSMax Filippov     xtensa_sim_load_kernel(cpu, machine);
125*d9e8553bSMax Filippov }
126*d9e8553bSMax Filippov 
127*d9e8553bSMax Filippov static void xtensa_virt_machine_init(MachineClass *mc)
128*d9e8553bSMax Filippov {
129*d9e8553bSMax Filippov     mc->desc = "virt machine (" XTENSA_DEFAULT_CPU_MODEL ")";
130*d9e8553bSMax Filippov     mc->init = xtensa_virt_init;
131*d9e8553bSMax Filippov     mc->max_cpus = 32;
132*d9e8553bSMax Filippov     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
133*d9e8553bSMax Filippov }
134*d9e8553bSMax Filippov 
135*d9e8553bSMax Filippov DEFINE_MACHINE("virt", xtensa_virt_machine_init)
136