1 /* 2 * ASPEED Watchdog Controller 3 * 4 * Copyright (C) 2016-2017 IBM Corp. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 12 #include "qapi/error.h" 13 #include "qemu/log.h" 14 #include "qemu/module.h" 15 #include "qemu/timer.h" 16 #include "sysemu/watchdog.h" 17 #include "hw/misc/aspeed_scu.h" 18 #include "hw/qdev-properties.h" 19 #include "hw/sysbus.h" 20 #include "hw/watchdog/wdt_aspeed.h" 21 #include "migration/vmstate.h" 22 23 #define WDT_STATUS (0x00 / 4) 24 #define WDT_RELOAD_VALUE (0x04 / 4) 25 #define WDT_RESTART (0x08 / 4) 26 #define WDT_CTRL (0x0C / 4) 27 #define WDT_CTRL_RESET_MODE_SOC (0x00 << 5) 28 #define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5) 29 #define WDT_CTRL_1MHZ_CLK BIT(4) 30 #define WDT_CTRL_WDT_EXT BIT(3) 31 #define WDT_CTRL_WDT_INTR BIT(2) 32 #define WDT_CTRL_RESET_SYSTEM BIT(1) 33 #define WDT_CTRL_ENABLE BIT(0) 34 #define WDT_RESET_WIDTH (0x18 / 4) 35 #define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31) 36 #define WDT_POLARITY_MASK (0xFF << 24) 37 #define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24) 38 #define WDT_ACTIVE_LOW_MAGIC (0x5A << 24) 39 #define WDT_RESET_WIDTH_PUSH_PULL BIT(30) 40 #define WDT_DRIVE_TYPE_MASK (0xFF << 24) 41 #define WDT_PUSH_PULL_MAGIC (0xA8 << 24) 42 #define WDT_OPEN_DRAIN_MAGIC (0x8A << 24) 43 44 #define WDT_TIMEOUT_STATUS (0x10 / 4) 45 #define WDT_TIMEOUT_CLEAR (0x14 / 4) 46 47 #define WDT_RESTART_MAGIC 0x4755 48 49 #define SCU_RESET_CONTROL1 (0x04 / 4) 50 #define SCU_RESET_SDRAM BIT(0) 51 52 static bool aspeed_wdt_is_enabled(const AspeedWDTState *s) 53 { 54 return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE; 55 } 56 57 static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size) 58 { 59 AspeedWDTState *s = ASPEED_WDT(opaque); 60 61 offset >>= 2; 62 63 switch (offset) { 64 case WDT_STATUS: 65 return s->regs[WDT_STATUS]; 66 case WDT_RELOAD_VALUE: 67 return s->regs[WDT_RELOAD_VALUE]; 68 case WDT_RESTART: 69 qemu_log_mask(LOG_GUEST_ERROR, 70 "%s: read from write-only reg at offset 0x%" 71 HWADDR_PRIx "\n", __func__, offset); 72 return 0; 73 case WDT_CTRL: 74 return s->regs[WDT_CTRL]; 75 case WDT_RESET_WIDTH: 76 return s->regs[WDT_RESET_WIDTH]; 77 case WDT_TIMEOUT_STATUS: 78 case WDT_TIMEOUT_CLEAR: 79 qemu_log_mask(LOG_UNIMP, 80 "%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n", 81 __func__, offset); 82 return 0; 83 default: 84 qemu_log_mask(LOG_GUEST_ERROR, 85 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", 86 __func__, offset); 87 return 0; 88 } 89 90 } 91 92 static void aspeed_wdt_reload(AspeedWDTState *s, bool pclk) 93 { 94 uint64_t reload; 95 96 if (pclk) { 97 reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND, 98 s->pclk_freq); 99 } else { 100 reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL; 101 } 102 103 if (aspeed_wdt_is_enabled(s)) { 104 timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload); 105 } 106 } 107 108 static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data, 109 unsigned size) 110 { 111 AspeedWDTState *s = ASPEED_WDT(opaque); 112 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(s); 113 bool enable = data & WDT_CTRL_ENABLE; 114 115 offset >>= 2; 116 117 switch (offset) { 118 case WDT_STATUS: 119 qemu_log_mask(LOG_GUEST_ERROR, 120 "%s: write to read-only reg at offset 0x%" 121 HWADDR_PRIx "\n", __func__, offset); 122 break; 123 case WDT_RELOAD_VALUE: 124 s->regs[WDT_RELOAD_VALUE] = data; 125 break; 126 case WDT_RESTART: 127 if ((data & 0xFFFF) == WDT_RESTART_MAGIC) { 128 s->regs[WDT_STATUS] = s->regs[WDT_RELOAD_VALUE]; 129 aspeed_wdt_reload(s, !(s->regs[WDT_CTRL] & WDT_CTRL_1MHZ_CLK)); 130 } 131 break; 132 case WDT_CTRL: 133 if (enable && !aspeed_wdt_is_enabled(s)) { 134 s->regs[WDT_CTRL] = data; 135 aspeed_wdt_reload(s, !(data & WDT_CTRL_1MHZ_CLK)); 136 } else if (!enable && aspeed_wdt_is_enabled(s)) { 137 s->regs[WDT_CTRL] = data; 138 timer_del(s->timer); 139 } 140 break; 141 case WDT_RESET_WIDTH: 142 if (awc->reset_pulse) { 143 awc->reset_pulse(s, data & WDT_POLARITY_MASK); 144 } 145 s->regs[WDT_RESET_WIDTH] &= ~awc->ext_pulse_width_mask; 146 s->regs[WDT_RESET_WIDTH] |= data & awc->ext_pulse_width_mask; 147 break; 148 149 case WDT_TIMEOUT_STATUS: 150 case WDT_TIMEOUT_CLEAR: 151 qemu_log_mask(LOG_UNIMP, 152 "%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n", 153 __func__, offset); 154 break; 155 default: 156 qemu_log_mask(LOG_GUEST_ERROR, 157 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", 158 __func__, offset); 159 } 160 return; 161 } 162 163 static WatchdogTimerModel model = { 164 .wdt_name = TYPE_ASPEED_WDT, 165 .wdt_description = "Aspeed watchdog device", 166 }; 167 168 static const VMStateDescription vmstate_aspeed_wdt = { 169 .name = "vmstate_aspeed_wdt", 170 .version_id = 0, 171 .minimum_version_id = 0, 172 .fields = (VMStateField[]) { 173 VMSTATE_TIMER_PTR(timer, AspeedWDTState), 174 VMSTATE_UINT32_ARRAY(regs, AspeedWDTState, ASPEED_WDT_REGS_MAX), 175 VMSTATE_END_OF_LIST() 176 } 177 }; 178 179 static const MemoryRegionOps aspeed_wdt_ops = { 180 .read = aspeed_wdt_read, 181 .write = aspeed_wdt_write, 182 .endianness = DEVICE_LITTLE_ENDIAN, 183 .valid.min_access_size = 4, 184 .valid.max_access_size = 4, 185 .valid.unaligned = false, 186 }; 187 188 static void aspeed_wdt_reset(DeviceState *dev) 189 { 190 AspeedWDTState *s = ASPEED_WDT(dev); 191 192 s->regs[WDT_STATUS] = 0x3EF1480; 193 s->regs[WDT_RELOAD_VALUE] = 0x03EF1480; 194 s->regs[WDT_RESTART] = 0; 195 s->regs[WDT_CTRL] = 0; 196 s->regs[WDT_RESET_WIDTH] = 0xFF; 197 198 timer_del(s->timer); 199 } 200 201 static void aspeed_wdt_timer_expired(void *dev) 202 { 203 AspeedWDTState *s = ASPEED_WDT(dev); 204 uint32_t reset_ctrl_reg = ASPEED_WDT_GET_CLASS(s)->reset_ctrl_reg; 205 206 /* Do not reset on SDRAM controller reset */ 207 if (s->scu->regs[reset_ctrl_reg] & SCU_RESET_SDRAM) { 208 timer_del(s->timer); 209 s->regs[WDT_CTRL] = 0; 210 return; 211 } 212 213 qemu_log_mask(CPU_LOG_RESET, "Watchdog timer expired.\n"); 214 watchdog_perform_action(); 215 timer_del(s->timer); 216 } 217 218 #define PCLK_HZ 24000000 219 220 static void aspeed_wdt_realize(DeviceState *dev, Error **errp) 221 { 222 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 223 AspeedWDTState *s = ASPEED_WDT(dev); 224 Error *err = NULL; 225 Object *obj; 226 227 obj = object_property_get_link(OBJECT(dev), "scu", &err); 228 if (!obj) { 229 error_propagate(errp, err); 230 error_prepend(errp, "required link 'scu' not found: "); 231 return; 232 } 233 s->scu = ASPEED_SCU(obj); 234 235 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired, dev); 236 237 /* FIXME: This setting should be derived from the SCU hw strapping 238 * register SCU70 239 */ 240 s->pclk_freq = PCLK_HZ; 241 242 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s, 243 TYPE_ASPEED_WDT, ASPEED_WDT_REGS_MAX * 4); 244 sysbus_init_mmio(sbd, &s->iomem); 245 } 246 247 static void aspeed_wdt_class_init(ObjectClass *klass, void *data) 248 { 249 DeviceClass *dc = DEVICE_CLASS(klass); 250 251 dc->desc = "ASPEED Watchdog Controller"; 252 dc->realize = aspeed_wdt_realize; 253 dc->reset = aspeed_wdt_reset; 254 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 255 dc->vmsd = &vmstate_aspeed_wdt; 256 } 257 258 static const TypeInfo aspeed_wdt_info = { 259 .parent = TYPE_SYS_BUS_DEVICE, 260 .name = TYPE_ASPEED_WDT, 261 .instance_size = sizeof(AspeedWDTState), 262 .class_init = aspeed_wdt_class_init, 263 .class_size = sizeof(AspeedWDTClass), 264 .abstract = true, 265 }; 266 267 static void aspeed_2400_wdt_class_init(ObjectClass *klass, void *data) 268 { 269 DeviceClass *dc = DEVICE_CLASS(klass); 270 AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass); 271 272 dc->desc = "ASPEED 2400 Watchdog Controller"; 273 awc->offset = 0x20; 274 awc->ext_pulse_width_mask = 0xff; 275 awc->reset_ctrl_reg = SCU_RESET_CONTROL1; 276 } 277 278 static const TypeInfo aspeed_2400_wdt_info = { 279 .name = TYPE_ASPEED_2400_WDT, 280 .parent = TYPE_ASPEED_WDT, 281 .instance_size = sizeof(AspeedWDTState), 282 .class_init = aspeed_2400_wdt_class_init, 283 }; 284 285 static void aspeed_2500_wdt_reset_pulse(AspeedWDTState *s, uint32_t property) 286 { 287 if (property) { 288 if (property == WDT_ACTIVE_HIGH_MAGIC) { 289 s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_ACTIVE_HIGH; 290 } else if (property == WDT_ACTIVE_LOW_MAGIC) { 291 s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_ACTIVE_HIGH; 292 } else if (property == WDT_PUSH_PULL_MAGIC) { 293 s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_PUSH_PULL; 294 } else if (property == WDT_OPEN_DRAIN_MAGIC) { 295 s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_PUSH_PULL; 296 } 297 } 298 } 299 300 static void aspeed_2500_wdt_class_init(ObjectClass *klass, void *data) 301 { 302 DeviceClass *dc = DEVICE_CLASS(klass); 303 AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass); 304 305 dc->desc = "ASPEED 2500 Watchdog Controller"; 306 awc->offset = 0x20; 307 awc->ext_pulse_width_mask = 0xfffff; 308 awc->reset_ctrl_reg = SCU_RESET_CONTROL1; 309 awc->reset_pulse = aspeed_2500_wdt_reset_pulse; 310 } 311 312 static const TypeInfo aspeed_2500_wdt_info = { 313 .name = TYPE_ASPEED_2500_WDT, 314 .parent = TYPE_ASPEED_WDT, 315 .instance_size = sizeof(AspeedWDTState), 316 .class_init = aspeed_2500_wdt_class_init, 317 }; 318 319 static void wdt_aspeed_register_types(void) 320 { 321 watchdog_add_model(&model); 322 type_register_static(&aspeed_wdt_info); 323 type_register_static(&aspeed_2400_wdt_info); 324 type_register_static(&aspeed_2500_wdt_info); 325 } 326 327 type_init(wdt_aspeed_register_types) 328