1 /* 2 * vfio based device assignment support - PCI devices 3 * 4 * Copyright Red Hat, Inc. 2012-2015 5 * 6 * Authors: 7 * Alex Williamson <alex.williamson@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2. See 10 * the COPYING file in the top-level directory. 11 */ 12 #ifndef HW_VFIO_VFIO_PCI_H 13 #define HW_VFIO_VFIO_PCI_H 14 15 #include "system/memory.h" 16 #include "hw/pci/pci_device.h" 17 #include "hw/vfio/vfio-device.h" 18 #include "hw/vfio/vfio-region.h" 19 #include "qemu/event_notifier.h" 20 #include "qemu/queue.h" 21 #include "qemu/timer.h" 22 #include "qom/object.h" 23 #include "system/kvm.h" 24 #include "vfio-display.h" 25 26 #define PCI_ANY_ID (~0) 27 28 struct VFIOPCIDevice; 29 30 typedef struct VFIOIOEventFD { 31 QLIST_ENTRY(VFIOIOEventFD) next; 32 MemoryRegion *mr; 33 hwaddr addr; 34 unsigned size; 35 uint64_t data; 36 EventNotifier e; 37 VFIORegion *region; 38 hwaddr region_addr; 39 bool dynamic; /* Added runtime, removed on device reset */ 40 bool vfio; 41 } VFIOIOEventFD; 42 43 typedef struct VFIOQuirk { 44 QLIST_ENTRY(VFIOQuirk) next; 45 void *data; 46 QLIST_HEAD(, VFIOIOEventFD) ioeventfds; 47 int nr_mem; 48 MemoryRegion *mem; 49 void (*reset)(struct VFIOPCIDevice *vdev, struct VFIOQuirk *quirk); 50 } VFIOQuirk; 51 52 typedef struct VFIOBAR { 53 VFIORegion region; 54 MemoryRegion *mr; 55 size_t size; 56 uint8_t type; 57 bool ioport; 58 bool mem64; 59 QLIST_HEAD(, VFIOQuirk) quirks; 60 } VFIOBAR; 61 62 typedef struct VFIOVGARegion { 63 MemoryRegion mem; 64 off_t offset; 65 int nr; 66 QLIST_HEAD(, VFIOQuirk) quirks; 67 } VFIOVGARegion; 68 69 typedef struct VFIOVGA { 70 off_t fd_offset; 71 int fd; 72 VFIOVGARegion region[QEMU_PCI_VGA_NUM_REGIONS]; 73 } VFIOVGA; 74 75 typedef struct VFIOINTx { 76 bool pending; /* interrupt pending */ 77 bool kvm_accel; /* set when QEMU bypass through KVM enabled */ 78 uint8_t pin; /* which pin to pull for qemu_set_irq */ 79 EventNotifier interrupt; /* eventfd triggered on interrupt */ 80 EventNotifier unmask; /* eventfd for unmask on QEMU bypass */ 81 PCIINTxRoute route; /* routing info for QEMU bypass */ 82 uint32_t mmap_timeout; /* delay to re-enable mmaps after interrupt */ 83 QEMUTimer *mmap_timer; /* enable mmaps after periods w/o interrupts */ 84 } VFIOINTx; 85 86 typedef struct VFIOMSIVector { 87 /* 88 * Two interrupt paths are configured per vector. The first, is only used 89 * for interrupts injected via QEMU. This is typically the non-accel path, 90 * but may also be used when we want QEMU to handle masking and pending 91 * bits. The KVM path bypasses QEMU and is therefore higher performance, 92 * but requires masking at the device. virq is used to track the MSI route 93 * through KVM, thus kvm_interrupt is only available when virq is set to a 94 * valid (>= 0) value. 95 */ 96 EventNotifier interrupt; 97 EventNotifier kvm_interrupt; 98 struct VFIOPCIDevice *vdev; /* back pointer to device */ 99 int virq; 100 bool use; 101 } VFIOMSIVector; 102 103 enum { 104 VFIO_INT_NONE = 0, 105 VFIO_INT_INTx = 1, 106 VFIO_INT_MSI = 2, 107 VFIO_INT_MSIX = 3, 108 }; 109 110 /* Cache of MSI-X setup */ 111 typedef struct VFIOMSIXInfo { 112 uint8_t table_bar; 113 uint8_t pba_bar; 114 uint16_t entries; 115 uint32_t table_offset; 116 uint32_t pba_offset; 117 unsigned long *pending; 118 bool noresize; 119 } VFIOMSIXInfo; 120 121 #define TYPE_VFIO_PCI "vfio-pci" 122 OBJECT_DECLARE_SIMPLE_TYPE(VFIOPCIDevice, VFIO_PCI) 123 124 struct VFIOPCIDevice { 125 PCIDevice pdev; 126 VFIODevice vbasedev; 127 VFIOINTx intx; 128 unsigned int config_size; 129 uint8_t *emulated_config_bits; /* QEMU emulated bits, little-endian */ 130 off_t config_offset; /* Offset of config space region within device fd */ 131 unsigned int rom_size; 132 off_t rom_offset; /* Offset of ROM region within device fd */ 133 void *rom; 134 int msi_cap_size; 135 VFIOMSIVector *msi_vectors; 136 VFIOMSIXInfo *msix; 137 int nr_vectors; /* Number of MSI/MSIX vectors currently in use */ 138 int interrupt; /* Current interrupt type */ 139 VFIOBAR bars[PCI_NUM_REGIONS - 1]; /* No ROM */ 140 VFIOVGA *vga; /* 0xa0000, 0x3b0, 0x3c0 */ 141 void *igd_opregion; 142 PCIHostDeviceAddress host; 143 QemuUUID vf_token; 144 EventNotifier err_notifier; 145 EventNotifier req_notifier; 146 int (*resetfn)(struct VFIOPCIDevice *); 147 uint32_t vendor_id; 148 uint32_t device_id; 149 uint32_t sub_vendor_id; 150 uint32_t sub_device_id; 151 uint32_t features; 152 #define VFIO_FEATURE_ENABLE_VGA_BIT 0 153 #define VFIO_FEATURE_ENABLE_VGA (1 << VFIO_FEATURE_ENABLE_VGA_BIT) 154 #define VFIO_FEATURE_ENABLE_REQ_BIT 1 155 #define VFIO_FEATURE_ENABLE_REQ (1 << VFIO_FEATURE_ENABLE_REQ_BIT) 156 #define VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT 2 157 #define VFIO_FEATURE_ENABLE_IGD_OPREGION \ 158 (1 << VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT) 159 #define VFIO_FEATURE_ENABLE_IGD_LPC_BIT 3 160 #define VFIO_FEATURE_ENABLE_IGD_LPC \ 161 (1 << VFIO_FEATURE_ENABLE_IGD_LPC_BIT) 162 OnOffAuto display; 163 uint32_t display_xres; 164 uint32_t display_yres; 165 int32_t bootindex; 166 OnOffAuto igd_legacy_mode; 167 uint32_t igd_gms; 168 OffAutoPCIBAR msix_relo; 169 uint8_t nv_gpudirect_clique; 170 bool pci_aer; 171 bool req_enabled; 172 bool has_flr; 173 bool has_pm_reset; 174 bool rom_read_failed; 175 bool no_kvm_intx; 176 bool no_kvm_msi; 177 bool no_kvm_msix; 178 bool no_geforce_quirks; 179 bool no_kvm_ioeventfd; 180 bool no_vfio_ioeventfd; 181 bool enable_ramfb; 182 OnOffAuto ramfb_migrate; 183 bool defer_kvm_irq_routing; 184 bool clear_parent_atomics_on_exit; 185 bool skip_vsc_check; 186 VFIODisplay *dpy; 187 Notifier irqchip_change_notifier; 188 }; 189 190 /* Use uin32_t for vendor & device so PCI_ANY_ID expands and cannot match hw */ 191 static inline bool vfio_pci_is(VFIOPCIDevice *vdev, uint32_t vendor, uint32_t device) 192 { 193 return (vendor == PCI_ANY_ID || vendor == vdev->vendor_id) && 194 (device == PCI_ANY_ID || device == vdev->device_id); 195 } 196 197 static inline bool vfio_is_vga(VFIOPCIDevice *vdev) 198 { 199 PCIDevice *pdev = &vdev->pdev; 200 uint16_t class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); 201 202 return class == PCI_CLASS_DISPLAY_VGA; 203 } 204 205 uint32_t vfio_pci_read_config(PCIDevice *pdev, uint32_t addr, int len); 206 void vfio_pci_write_config(PCIDevice *pdev, 207 uint32_t addr, uint32_t val, int len); 208 209 uint64_t vfio_vga_read(void *opaque, hwaddr addr, unsigned size); 210 void vfio_vga_write(void *opaque, hwaddr addr, uint64_t data, unsigned size); 211 212 bool vfio_opt_rom_in_denylist(VFIOPCIDevice *vdev); 213 bool vfio_config_quirk_setup(VFIOPCIDevice *vdev, Error **errp); 214 void vfio_vga_quirk_setup(VFIOPCIDevice *vdev); 215 void vfio_vga_quirk_exit(VFIOPCIDevice *vdev); 216 void vfio_vga_quirk_finalize(VFIOPCIDevice *vdev); 217 void vfio_bar_quirk_setup(VFIOPCIDevice *vdev, int nr); 218 void vfio_bar_quirk_exit(VFIOPCIDevice *vdev, int nr); 219 void vfio_bar_quirk_finalize(VFIOPCIDevice *vdev, int nr); 220 void vfio_setup_resetfn_quirk(VFIOPCIDevice *vdev); 221 bool vfio_add_virt_caps(VFIOPCIDevice *vdev, Error **errp); 222 void vfio_quirk_reset(VFIOPCIDevice *vdev); 223 VFIOQuirk *vfio_quirk_alloc(int nr_mem); 224 void vfio_probe_igd_bar0_quirk(VFIOPCIDevice *vdev, int nr); 225 bool vfio_probe_igd_config_quirk(VFIOPCIDevice *vdev, Error **errp); 226 227 extern const PropertyInfo qdev_prop_nv_gpudirect_clique; 228 229 void vfio_pci_pre_reset(VFIOPCIDevice *vdev); 230 void vfio_pci_post_reset(VFIOPCIDevice *vdev); 231 bool vfio_pci_host_match(PCIHostDeviceAddress *addr, const char *name); 232 int vfio_pci_get_pci_hot_reset_info(VFIOPCIDevice *vdev, 233 struct vfio_pci_hot_reset_info **info_p); 234 235 bool vfio_populate_vga(VFIOPCIDevice *vdev, Error **errp); 236 237 void vfio_display_reset(VFIOPCIDevice *vdev); 238 bool vfio_display_probe(VFIOPCIDevice *vdev, Error **errp); 239 void vfio_display_finalize(VFIOPCIDevice *vdev); 240 241 extern const VMStateDescription vfio_display_vmstate; 242 243 #endif /* HW_VFIO_VFIO_PCI_H */ 244