1 /* 2 * vfio based device assignment support - PCI devices 3 * 4 * Copyright Red Hat, Inc. 2012-2015 5 * 6 * Authors: 7 * Alex Williamson <alex.williamson@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2. See 10 * the COPYING file in the top-level directory. 11 */ 12 #ifndef HW_VFIO_VFIO_PCI_H 13 #define HW_VFIO_VFIO_PCI_H 14 15 #include "system/memory.h" 16 #include "hw/pci/pci_device.h" 17 #include "hw/vfio/vfio-common.h" 18 #include "qemu/event_notifier.h" 19 #include "qemu/queue.h" 20 #include "qemu/timer.h" 21 #include "qom/object.h" 22 #include "system/kvm.h" 23 #include "vfio-display.h" 24 25 #define PCI_ANY_ID (~0) 26 27 struct VFIOPCIDevice; 28 29 typedef struct VFIOIOEventFD { 30 QLIST_ENTRY(VFIOIOEventFD) next; 31 MemoryRegion *mr; 32 hwaddr addr; 33 unsigned size; 34 uint64_t data; 35 EventNotifier e; 36 VFIORegion *region; 37 hwaddr region_addr; 38 bool dynamic; /* Added runtime, removed on device reset */ 39 bool vfio; 40 } VFIOIOEventFD; 41 42 typedef struct VFIOQuirk { 43 QLIST_ENTRY(VFIOQuirk) next; 44 void *data; 45 QLIST_HEAD(, VFIOIOEventFD) ioeventfds; 46 int nr_mem; 47 MemoryRegion *mem; 48 void (*reset)(struct VFIOPCIDevice *vdev, struct VFIOQuirk *quirk); 49 } VFIOQuirk; 50 51 typedef struct VFIOBAR { 52 VFIORegion region; 53 MemoryRegion *mr; 54 size_t size; 55 uint8_t type; 56 bool ioport; 57 bool mem64; 58 QLIST_HEAD(, VFIOQuirk) quirks; 59 } VFIOBAR; 60 61 typedef struct VFIOVGARegion { 62 MemoryRegion mem; 63 off_t offset; 64 int nr; 65 QLIST_HEAD(, VFIOQuirk) quirks; 66 } VFIOVGARegion; 67 68 typedef struct VFIOVGA { 69 off_t fd_offset; 70 int fd; 71 VFIOVGARegion region[QEMU_PCI_VGA_NUM_REGIONS]; 72 } VFIOVGA; 73 74 typedef struct VFIOINTx { 75 bool pending; /* interrupt pending */ 76 bool kvm_accel; /* set when QEMU bypass through KVM enabled */ 77 uint8_t pin; /* which pin to pull for qemu_set_irq */ 78 EventNotifier interrupt; /* eventfd triggered on interrupt */ 79 EventNotifier unmask; /* eventfd for unmask on QEMU bypass */ 80 PCIINTxRoute route; /* routing info for QEMU bypass */ 81 uint32_t mmap_timeout; /* delay to re-enable mmaps after interrupt */ 82 QEMUTimer *mmap_timer; /* enable mmaps after periods w/o interrupts */ 83 } VFIOINTx; 84 85 typedef struct VFIOMSIVector { 86 /* 87 * Two interrupt paths are configured per vector. The first, is only used 88 * for interrupts injected via QEMU. This is typically the non-accel path, 89 * but may also be used when we want QEMU to handle masking and pending 90 * bits. The KVM path bypasses QEMU and is therefore higher performance, 91 * but requires masking at the device. virq is used to track the MSI route 92 * through KVM, thus kvm_interrupt is only available when virq is set to a 93 * valid (>= 0) value. 94 */ 95 EventNotifier interrupt; 96 EventNotifier kvm_interrupt; 97 struct VFIOPCIDevice *vdev; /* back pointer to device */ 98 int virq; 99 bool use; 100 } VFIOMSIVector; 101 102 enum { 103 VFIO_INT_NONE = 0, 104 VFIO_INT_INTx = 1, 105 VFIO_INT_MSI = 2, 106 VFIO_INT_MSIX = 3, 107 }; 108 109 /* Cache of MSI-X setup */ 110 typedef struct VFIOMSIXInfo { 111 uint8_t table_bar; 112 uint8_t pba_bar; 113 uint16_t entries; 114 uint32_t table_offset; 115 uint32_t pba_offset; 116 unsigned long *pending; 117 bool noresize; 118 } VFIOMSIXInfo; 119 120 #define TYPE_VFIO_PCI "vfio-pci" 121 OBJECT_DECLARE_SIMPLE_TYPE(VFIOPCIDevice, VFIO_PCI) 122 123 struct VFIOPCIDevice { 124 PCIDevice pdev; 125 VFIODevice vbasedev; 126 VFIOINTx intx; 127 unsigned int config_size; 128 uint8_t *emulated_config_bits; /* QEMU emulated bits, little-endian */ 129 off_t config_offset; /* Offset of config space region within device fd */ 130 unsigned int rom_size; 131 off_t rom_offset; /* Offset of ROM region within device fd */ 132 void *rom; 133 int msi_cap_size; 134 VFIOMSIVector *msi_vectors; 135 VFIOMSIXInfo *msix; 136 int nr_vectors; /* Number of MSI/MSIX vectors currently in use */ 137 int interrupt; /* Current interrupt type */ 138 VFIOBAR bars[PCI_NUM_REGIONS - 1]; /* No ROM */ 139 VFIOVGA *vga; /* 0xa0000, 0x3b0, 0x3c0 */ 140 void *igd_opregion; 141 PCIHostDeviceAddress host; 142 QemuUUID vf_token; 143 EventNotifier err_notifier; 144 EventNotifier req_notifier; 145 int (*resetfn)(struct VFIOPCIDevice *); 146 uint32_t vendor_id; 147 uint32_t device_id; 148 uint32_t sub_vendor_id; 149 uint32_t sub_device_id; 150 uint32_t features; 151 #define VFIO_FEATURE_ENABLE_VGA_BIT 0 152 #define VFIO_FEATURE_ENABLE_VGA (1 << VFIO_FEATURE_ENABLE_VGA_BIT) 153 #define VFIO_FEATURE_ENABLE_REQ_BIT 1 154 #define VFIO_FEATURE_ENABLE_REQ (1 << VFIO_FEATURE_ENABLE_REQ_BIT) 155 #define VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT 2 156 #define VFIO_FEATURE_ENABLE_IGD_OPREGION \ 157 (1 << VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT) 158 #define VFIO_FEATURE_ENABLE_IGD_LPC_BIT 3 159 #define VFIO_FEATURE_ENABLE_IGD_LPC \ 160 (1 << VFIO_FEATURE_ENABLE_IGD_LPC_BIT) 161 OnOffAuto display; 162 uint32_t display_xres; 163 uint32_t display_yres; 164 int32_t bootindex; 165 OnOffAuto igd_legacy_mode; 166 uint32_t igd_gms; 167 OffAutoPCIBAR msix_relo; 168 uint8_t nv_gpudirect_clique; 169 bool pci_aer; 170 bool req_enabled; 171 bool has_flr; 172 bool has_pm_reset; 173 bool rom_read_failed; 174 bool no_kvm_intx; 175 bool no_kvm_msi; 176 bool no_kvm_msix; 177 bool no_geforce_quirks; 178 bool no_kvm_ioeventfd; 179 bool no_vfio_ioeventfd; 180 bool enable_ramfb; 181 OnOffAuto ramfb_migrate; 182 bool defer_kvm_irq_routing; 183 bool clear_parent_atomics_on_exit; 184 bool skip_vsc_check; 185 VFIODisplay *dpy; 186 Notifier irqchip_change_notifier; 187 }; 188 189 /* Use uin32_t for vendor & device so PCI_ANY_ID expands and cannot match hw */ 190 static inline bool vfio_pci_is(VFIOPCIDevice *vdev, uint32_t vendor, uint32_t device) 191 { 192 return (vendor == PCI_ANY_ID || vendor == vdev->vendor_id) && 193 (device == PCI_ANY_ID || device == vdev->device_id); 194 } 195 196 static inline bool vfio_is_vga(VFIOPCIDevice *vdev) 197 { 198 PCIDevice *pdev = &vdev->pdev; 199 uint16_t class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); 200 201 return class == PCI_CLASS_DISPLAY_VGA; 202 } 203 204 uint32_t vfio_pci_read_config(PCIDevice *pdev, uint32_t addr, int len); 205 void vfio_pci_write_config(PCIDevice *pdev, 206 uint32_t addr, uint32_t val, int len); 207 208 uint64_t vfio_vga_read(void *opaque, hwaddr addr, unsigned size); 209 void vfio_vga_write(void *opaque, hwaddr addr, uint64_t data, unsigned size); 210 211 bool vfio_opt_rom_in_denylist(VFIOPCIDevice *vdev); 212 bool vfio_config_quirk_setup(VFIOPCIDevice *vdev, Error **errp); 213 void vfio_vga_quirk_setup(VFIOPCIDevice *vdev); 214 void vfio_vga_quirk_exit(VFIOPCIDevice *vdev); 215 void vfio_vga_quirk_finalize(VFIOPCIDevice *vdev); 216 void vfio_bar_quirk_setup(VFIOPCIDevice *vdev, int nr); 217 void vfio_bar_quirk_exit(VFIOPCIDevice *vdev, int nr); 218 void vfio_bar_quirk_finalize(VFIOPCIDevice *vdev, int nr); 219 void vfio_setup_resetfn_quirk(VFIOPCIDevice *vdev); 220 bool vfio_add_virt_caps(VFIOPCIDevice *vdev, Error **errp); 221 void vfio_quirk_reset(VFIOPCIDevice *vdev); 222 VFIOQuirk *vfio_quirk_alloc(int nr_mem); 223 void vfio_probe_igd_bar0_quirk(VFIOPCIDevice *vdev, int nr); 224 bool vfio_probe_igd_config_quirk(VFIOPCIDevice *vdev, Error **errp); 225 226 extern const PropertyInfo qdev_prop_nv_gpudirect_clique; 227 228 void vfio_pci_pre_reset(VFIOPCIDevice *vdev); 229 void vfio_pci_post_reset(VFIOPCIDevice *vdev); 230 bool vfio_pci_host_match(PCIHostDeviceAddress *addr, const char *name); 231 int vfio_pci_get_pci_hot_reset_info(VFIOPCIDevice *vdev, 232 struct vfio_pci_hot_reset_info **info_p); 233 234 bool vfio_populate_vga(VFIOPCIDevice *vdev, Error **errp); 235 236 void vfio_display_reset(VFIOPCIDevice *vdev); 237 bool vfio_display_probe(VFIOPCIDevice *vdev, Error **errp); 238 void vfio_display_finalize(VFIOPCIDevice *vdev); 239 240 extern const VMStateDescription vfio_display_vmstate; 241 242 #endif /* HW_VFIO_VFIO_PCI_H */ 243