1 /* 2 * vfio based device assignment support - PCI devices 3 * 4 * Copyright Red Hat, Inc. 2012-2015 5 * 6 * Authors: 7 * Alex Williamson <alex.williamson@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2. See 10 * the COPYING file in the top-level directory. 11 */ 12 #ifndef HW_VFIO_VFIO_PCI_H 13 #define HW_VFIO_VFIO_PCI_H 14 15 #include "qemu-common.h" 16 #include "exec/memory.h" 17 #include "hw/pci/pci.h" 18 #include "hw/vfio/vfio-common.h" 19 #include "qemu/event_notifier.h" 20 #include "qemu/queue.h" 21 #include "qemu/timer.h" 22 23 #define PCI_ANY_ID (~0) 24 25 struct VFIOPCIDevice; 26 27 typedef struct VFIOQuirk { 28 QLIST_ENTRY(VFIOQuirk) next; 29 void *data; 30 int nr_mem; 31 MemoryRegion *mem; 32 void (*reset)(struct VFIOPCIDevice *vdev, struct VFIOQuirk *quirk); 33 } VFIOQuirk; 34 35 typedef struct VFIOBAR { 36 VFIORegion region; 37 MemoryRegion *mr; 38 size_t size; 39 uint8_t type; 40 bool ioport; 41 bool mem64; 42 QLIST_HEAD(, VFIOQuirk) quirks; 43 } VFIOBAR; 44 45 typedef struct VFIOVGARegion { 46 MemoryRegion mem; 47 off_t offset; 48 int nr; 49 QLIST_HEAD(, VFIOQuirk) quirks; 50 } VFIOVGARegion; 51 52 typedef struct VFIOVGA { 53 off_t fd_offset; 54 int fd; 55 VFIOVGARegion region[QEMU_PCI_VGA_NUM_REGIONS]; 56 } VFIOVGA; 57 58 typedef struct VFIOINTx { 59 bool pending; /* interrupt pending */ 60 bool kvm_accel; /* set when QEMU bypass through KVM enabled */ 61 uint8_t pin; /* which pin to pull for qemu_set_irq */ 62 EventNotifier interrupt; /* eventfd triggered on interrupt */ 63 EventNotifier unmask; /* eventfd for unmask on QEMU bypass */ 64 PCIINTxRoute route; /* routing info for QEMU bypass */ 65 uint32_t mmap_timeout; /* delay to re-enable mmaps after interrupt */ 66 QEMUTimer *mmap_timer; /* enable mmaps after periods w/o interrupts */ 67 } VFIOINTx; 68 69 typedef struct VFIOMSIVector { 70 /* 71 * Two interrupt paths are configured per vector. The first, is only used 72 * for interrupts injected via QEMU. This is typically the non-accel path, 73 * but may also be used when we want QEMU to handle masking and pending 74 * bits. The KVM path bypasses QEMU and is therefore higher performance, 75 * but requires masking at the device. virq is used to track the MSI route 76 * through KVM, thus kvm_interrupt is only available when virq is set to a 77 * valid (>= 0) value. 78 */ 79 EventNotifier interrupt; 80 EventNotifier kvm_interrupt; 81 struct VFIOPCIDevice *vdev; /* back pointer to device */ 82 int virq; 83 bool use; 84 } VFIOMSIVector; 85 86 enum { 87 VFIO_INT_NONE = 0, 88 VFIO_INT_INTx = 1, 89 VFIO_INT_MSI = 2, 90 VFIO_INT_MSIX = 3, 91 }; 92 93 /* Cache of MSI-X setup */ 94 typedef struct VFIOMSIXInfo { 95 uint8_t table_bar; 96 uint8_t pba_bar; 97 uint16_t entries; 98 uint32_t table_offset; 99 uint32_t pba_offset; 100 unsigned long *pending; 101 } VFIOMSIXInfo; 102 103 typedef struct VFIOPCIDevice { 104 PCIDevice pdev; 105 VFIODevice vbasedev; 106 VFIOINTx intx; 107 unsigned int config_size; 108 uint8_t *emulated_config_bits; /* QEMU emulated bits, little-endian */ 109 off_t config_offset; /* Offset of config space region within device fd */ 110 unsigned int rom_size; 111 off_t rom_offset; /* Offset of ROM region within device fd */ 112 void *rom; 113 int msi_cap_size; 114 VFIOMSIVector *msi_vectors; 115 VFIOMSIXInfo *msix; 116 int nr_vectors; /* Number of MSI/MSIX vectors currently in use */ 117 int interrupt; /* Current interrupt type */ 118 VFIOBAR bars[PCI_NUM_REGIONS - 1]; /* No ROM */ 119 VFIOVGA *vga; /* 0xa0000, 0x3b0, 0x3c0 */ 120 void *igd_opregion; 121 PCIHostDeviceAddress host; 122 EventNotifier err_notifier; 123 EventNotifier req_notifier; 124 int (*resetfn)(struct VFIOPCIDevice *); 125 uint32_t vendor_id; 126 uint32_t device_id; 127 uint32_t sub_vendor_id; 128 uint32_t sub_device_id; 129 uint32_t features; 130 #define VFIO_FEATURE_ENABLE_VGA_BIT 0 131 #define VFIO_FEATURE_ENABLE_VGA (1 << VFIO_FEATURE_ENABLE_VGA_BIT) 132 #define VFIO_FEATURE_ENABLE_REQ_BIT 1 133 #define VFIO_FEATURE_ENABLE_REQ (1 << VFIO_FEATURE_ENABLE_REQ_BIT) 134 #define VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT 2 135 #define VFIO_FEATURE_ENABLE_IGD_OPREGION \ 136 (1 << VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT) 137 OnOffAuto display; 138 int32_t bootindex; 139 uint32_t igd_gms; 140 OffAutoPCIBAR msix_relo; 141 uint8_t pm_cap; 142 uint8_t nv_gpudirect_clique; 143 bool pci_aer; 144 bool req_enabled; 145 bool has_flr; 146 bool has_pm_reset; 147 bool rom_read_failed; 148 bool no_kvm_intx; 149 bool no_kvm_msi; 150 bool no_kvm_msix; 151 bool no_geforce_quirks; 152 VFIODisplay *dpy; 153 } VFIOPCIDevice; 154 155 uint32_t vfio_pci_read_config(PCIDevice *pdev, uint32_t addr, int len); 156 void vfio_pci_write_config(PCIDevice *pdev, 157 uint32_t addr, uint32_t val, int len); 158 159 uint64_t vfio_vga_read(void *opaque, hwaddr addr, unsigned size); 160 void vfio_vga_write(void *opaque, hwaddr addr, uint64_t data, unsigned size); 161 162 bool vfio_blacklist_opt_rom(VFIOPCIDevice *vdev); 163 void vfio_vga_quirk_setup(VFIOPCIDevice *vdev); 164 void vfio_vga_quirk_exit(VFIOPCIDevice *vdev); 165 void vfio_vga_quirk_finalize(VFIOPCIDevice *vdev); 166 void vfio_bar_quirk_setup(VFIOPCIDevice *vdev, int nr); 167 void vfio_bar_quirk_exit(VFIOPCIDevice *vdev, int nr); 168 void vfio_bar_quirk_finalize(VFIOPCIDevice *vdev, int nr); 169 void vfio_setup_resetfn_quirk(VFIOPCIDevice *vdev); 170 int vfio_add_virt_caps(VFIOPCIDevice *vdev, Error **errp); 171 void vfio_quirk_reset(VFIOPCIDevice *vdev); 172 173 extern const PropertyInfo qdev_prop_nv_gpudirect_clique; 174 175 int vfio_populate_vga(VFIOPCIDevice *vdev, Error **errp); 176 177 int vfio_pci_igd_opregion_init(VFIOPCIDevice *vdev, 178 struct vfio_region_info *info, 179 Error **errp); 180 181 void vfio_display_reset(VFIOPCIDevice *vdev); 182 int vfio_display_probe(VFIOPCIDevice *vdev, Error **errp); 183 void vfio_display_finalize(VFIOPCIDevice *vdev); 184 185 #endif /* HW_VFIO_VFIO_PCI_H */ 186