1 /* 2 * IGD device quirks 3 * 4 * Copyright Red Hat, Inc. 2016 5 * 6 * Authors: 7 * Alex Williamson <alex.williamson@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2. See 10 * the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qemu/units.h" 15 #include "qemu/error-report.h" 16 #include "qapi/error.h" 17 #include "qapi/qmp/qerror.h" 18 #include "hw/boards.h" 19 #include "hw/hw.h" 20 #include "hw/nvram/fw_cfg.h" 21 #include "pci.h" 22 #include "pci-quirks.h" 23 #include "trace.h" 24 25 /* 26 * Intel IGD support 27 * 28 * Obviously IGD is not a discrete device, this is evidenced not only by it 29 * being integrated into the CPU, but by the various chipset and BIOS 30 * dependencies that it brings along with it. Intel is trying to move away 31 * from this and Broadwell and newer devices can run in what Intel calls 32 * "Universal Pass-Through" mode, or UPT. Theoretically in UPT mode, nothing 33 * more is required beyond assigning the IGD device to a VM. There are 34 * however support limitations to this mode. It only supports IGD as a 35 * secondary graphics device in the VM and it doesn't officially support any 36 * physical outputs. 37 * 38 * The code here attempts to enable what we'll call legacy mode assignment, 39 * IGD retains most of the capabilities we expect for it to have on bare 40 * metal. To enable this mode, the IGD device must be assigned to the VM 41 * at PCI address 00:02.0, it must have a ROM, it very likely needs VGA 42 * support, we must have VM BIOS support for reserving and populating some 43 * of the required tables, and we need to tweak the chipset with revisions 44 * and IDs and an LPC/ISA bridge device. The intention is to make all of 45 * this happen automatically by installing the device at the correct VM PCI 46 * bus address. If any of the conditions are not met, we cross our fingers 47 * and hope the user knows better. 48 * 49 * NB - It is possible to enable physical outputs in UPT mode by supplying 50 * an OpRegion table. We don't do this by default because the guest driver 51 * behaves differently if an OpRegion is provided and no monitor is attached 52 * vs no OpRegion and a monitor being attached or not. Effectively, if a 53 * headless setup is desired, the OpRegion gets in the way of that. 54 */ 55 56 /* 57 * This presumes the device is already known to be an Intel VGA device, so we 58 * take liberties in which device ID bits match which generation. This should 59 * not be taken as an indication that all the devices are supported, or even 60 * supportable, some of them don't even support VT-d. 61 * See linux:include/drm/i915_pciids.h for IDs. 62 */ 63 static int igd_gen(VFIOPCIDevice *vdev) 64 { 65 /* 66 * Device IDs for Broxton/Apollo Lake are 0x0a84, 0x1a84, 0x1a85, 0x5a84 67 * and 0x5a85, match bit 11:1 here 68 * Prefix 0x0a is taken by Haswell, this rule should be matched first. 69 */ 70 if ((vdev->device_id & 0xffe) == 0xa84) { 71 return 9; 72 } 73 74 switch (vdev->device_id & 0xff00) { 75 case 0x0100: /* SandyBridge, IvyBridge */ 76 return 6; 77 case 0x0400: /* Haswell */ 78 case 0x0a00: /* Haswell */ 79 case 0x0c00: /* Haswell */ 80 case 0x0d00: /* Haswell */ 81 case 0x0f00: /* Valleyview/Bay Trail */ 82 return 7; 83 case 0x1600: /* Broadwell */ 84 case 0x2200: /* Cherryview */ 85 return 8; 86 case 0x1900: /* Skylake */ 87 case 0x3100: /* Gemini Lake */ 88 case 0x5900: /* Kaby Lake */ 89 case 0x3e00: /* Coffee Lake */ 90 case 0x9B00: /* Comet Lake */ 91 return 9; 92 case 0x8A00: /* Ice Lake */ 93 case 0x4500: /* Elkhart Lake */ 94 case 0x4E00: /* Jasper Lake */ 95 return 11; 96 case 0x9A00: /* Tiger Lake */ 97 case 0x4C00: /* Rocket Lake */ 98 case 0x4600: /* Alder Lake */ 99 case 0xA700: /* Raptor Lake */ 100 return 12; 101 } 102 103 /* 104 * Unfortunately, Intel changes it's specification quite often. This makes 105 * it impossible to use a suitable default value for unknown devices. 106 */ 107 return -1; 108 } 109 110 #define IGD_ASLS 0xfc /* ASL Storage Register */ 111 #define IGD_GMCH 0x50 /* Graphics Control Register */ 112 #define IGD_BDSM 0x5c /* Base Data of Stolen Memory */ 113 #define IGD_BDSM_GEN11 0xc0 /* Base Data of Stolen Memory of gen 11 and later */ 114 115 #define IGD_GMCH_GEN6_GMS_SHIFT 3 /* SNB_GMCH in i915 */ 116 #define IGD_GMCH_GEN6_GMS_MASK 0x1f 117 #define IGD_GMCH_GEN8_GMS_SHIFT 8 /* BDW_GMCH in i915 */ 118 #define IGD_GMCH_GEN8_GMS_MASK 0xff 119 120 static uint64_t igd_stolen_memory_size(int gen, uint32_t gmch) 121 { 122 uint64_t gms; 123 124 if (gen < 8) { 125 gms = (gmch >> IGD_GMCH_GEN6_GMS_SHIFT) & IGD_GMCH_GEN6_GMS_MASK; 126 } else { 127 gms = (gmch >> IGD_GMCH_GEN8_GMS_SHIFT) & IGD_GMCH_GEN8_GMS_MASK; 128 } 129 130 if (gen < 9) { 131 return gms * 32 * MiB; 132 } else { 133 if (gms < 0xf0) { 134 return gms * 32 * MiB; 135 } else { 136 return (gms - 0xf0 + 1) * 4 * MiB; 137 } 138 } 139 140 return 0; 141 } 142 143 /* 144 * The OpRegion includes the Video BIOS Table, which seems important for 145 * telling the driver what sort of outputs it has. Without this, the device 146 * may work in the guest, but we may not get output. This also requires BIOS 147 * support to reserve and populate a section of guest memory sufficient for 148 * the table and to write the base address of that memory to the ASLS register 149 * of the IGD device. 150 */ 151 static bool vfio_pci_igd_opregion_init(VFIOPCIDevice *vdev, 152 struct vfio_region_info *info, 153 Error **errp) 154 { 155 int ret; 156 157 vdev->igd_opregion = g_malloc0(info->size); 158 ret = pread(vdev->vbasedev.fd, vdev->igd_opregion, 159 info->size, info->offset); 160 if (ret != info->size) { 161 error_setg(errp, "failed to read IGD OpRegion"); 162 g_free(vdev->igd_opregion); 163 vdev->igd_opregion = NULL; 164 return false; 165 } 166 167 /* 168 * Provide fw_cfg with a copy of the OpRegion which the VM firmware is to 169 * allocate 32bit reserved memory for, copy these contents into, and write 170 * the reserved memory base address to the device ASLS register at 0xFC. 171 * Alignment of this reserved region seems flexible, but using a 4k page 172 * alignment seems to work well. This interface assumes a single IGD 173 * device, which may be at VM address 00:02.0 in legacy mode or another 174 * address in UPT mode. 175 * 176 * NB, there may be future use cases discovered where the VM should have 177 * direct interaction with the host OpRegion, in which case the write to 178 * the ASLS register would trigger MemoryRegion setup to enable that. 179 */ 180 fw_cfg_add_file(fw_cfg_find(), "etc/igd-opregion", 181 vdev->igd_opregion, info->size); 182 183 trace_vfio_pci_igd_opregion_enabled(vdev->vbasedev.name); 184 185 pci_set_long(vdev->pdev.config + IGD_ASLS, 0); 186 pci_set_long(vdev->pdev.wmask + IGD_ASLS, ~0); 187 pci_set_long(vdev->emulated_config_bits + IGD_ASLS, ~0); 188 189 return true; 190 } 191 192 static bool vfio_pci_igd_setup_opregion(VFIOPCIDevice *vdev, Error **errp) 193 { 194 g_autofree struct vfio_region_info *opregion = NULL; 195 int ret; 196 197 /* Hotplugging is not supported for opregion access */ 198 if (vdev->pdev.qdev.hotplugged) { 199 error_setg(errp, "IGD OpRegion is not supported on hotplugged device"); 200 return false; 201 } 202 203 ret = vfio_device_get_region_info_type(&vdev->vbasedev, 204 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL, 205 VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION, &opregion); 206 if (ret) { 207 error_setg_errno(errp, -ret, 208 "Device does not supports IGD OpRegion feature"); 209 return false; 210 } 211 212 if (!vfio_pci_igd_opregion_init(vdev, opregion, errp)) { 213 return false; 214 } 215 216 return true; 217 } 218 219 /* 220 * The rather short list of registers that we copy from the host devices. 221 * The LPC/ISA bridge values are definitely needed to support the vBIOS, the 222 * host bridge values may or may not be needed depending on the guest OS. 223 * Since we're only munging revision and subsystem values on the host bridge, 224 * we don't require our own device. The LPC/ISA bridge needs to be our very 225 * own though. 226 */ 227 typedef struct { 228 uint8_t offset; 229 uint8_t len; 230 } IGDHostInfo; 231 232 static const IGDHostInfo igd_host_bridge_infos[] = { 233 {PCI_REVISION_ID, 2}, 234 {PCI_SUBSYSTEM_VENDOR_ID, 2}, 235 {PCI_SUBSYSTEM_ID, 2}, 236 }; 237 238 static const IGDHostInfo igd_lpc_bridge_infos[] = { 239 {PCI_VENDOR_ID, 2}, 240 {PCI_DEVICE_ID, 2}, 241 {PCI_REVISION_ID, 2}, 242 {PCI_SUBSYSTEM_VENDOR_ID, 2}, 243 {PCI_SUBSYSTEM_ID, 2}, 244 }; 245 246 static int vfio_pci_igd_copy(VFIOPCIDevice *vdev, PCIDevice *pdev, 247 struct vfio_region_info *info, 248 const IGDHostInfo *list, int len) 249 { 250 int i, ret; 251 252 for (i = 0; i < len; i++) { 253 ret = pread(vdev->vbasedev.fd, pdev->config + list[i].offset, 254 list[i].len, info->offset + list[i].offset); 255 if (ret != list[i].len) { 256 error_report("IGD copy failed: %m"); 257 return -errno; 258 } 259 } 260 261 return 0; 262 } 263 264 /* 265 * Stuff a few values into the host bridge. 266 */ 267 static int vfio_pci_igd_host_init(VFIOPCIDevice *vdev, 268 struct vfio_region_info *info) 269 { 270 PCIBus *bus; 271 PCIDevice *host_bridge; 272 int ret; 273 274 bus = pci_device_root_bus(&vdev->pdev); 275 host_bridge = pci_find_device(bus, 0, PCI_DEVFN(0, 0)); 276 277 if (!host_bridge) { 278 error_report("Can't find host bridge"); 279 return -ENODEV; 280 } 281 282 ret = vfio_pci_igd_copy(vdev, host_bridge, info, igd_host_bridge_infos, 283 ARRAY_SIZE(igd_host_bridge_infos)); 284 if (!ret) { 285 trace_vfio_pci_igd_host_bridge_enabled(vdev->vbasedev.name); 286 } 287 288 return ret; 289 } 290 291 /* 292 * IGD LPC/ISA bridge support code. The vBIOS needs this, but we can't write 293 * arbitrary values into just any bridge, so we must create our own. We try 294 * to handle if the user has created it for us, which they might want to do 295 * to enable multifunction so we don't occupy the whole PCI slot. 296 */ 297 static void vfio_pci_igd_lpc_bridge_realize(PCIDevice *pdev, Error **errp) 298 { 299 if (pdev->devfn != PCI_DEVFN(0x1f, 0)) { 300 error_setg(errp, "VFIO dummy ISA/LPC bridge must have address 1f.0"); 301 } 302 } 303 304 static void vfio_pci_igd_lpc_bridge_class_init(ObjectClass *klass, 305 const void *data) 306 { 307 DeviceClass *dc = DEVICE_CLASS(klass); 308 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 309 310 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 311 dc->desc = "VFIO dummy ISA/LPC bridge for IGD assignment"; 312 dc->hotpluggable = false; 313 k->realize = vfio_pci_igd_lpc_bridge_realize; 314 k->class_id = PCI_CLASS_BRIDGE_ISA; 315 } 316 317 static const TypeInfo vfio_pci_igd_lpc_bridge_info = { 318 .name = "vfio-pci-igd-lpc-bridge", 319 .parent = TYPE_PCI_DEVICE, 320 .class_init = vfio_pci_igd_lpc_bridge_class_init, 321 .interfaces = (const InterfaceInfo[]) { 322 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 323 { }, 324 }, 325 }; 326 327 static void vfio_pci_igd_register_types(void) 328 { 329 type_register_static(&vfio_pci_igd_lpc_bridge_info); 330 } 331 332 type_init(vfio_pci_igd_register_types) 333 334 static int vfio_pci_igd_lpc_init(VFIOPCIDevice *vdev, 335 struct vfio_region_info *info) 336 { 337 PCIDevice *lpc_bridge; 338 int ret; 339 340 lpc_bridge = pci_find_device(pci_device_root_bus(&vdev->pdev), 341 0, PCI_DEVFN(0x1f, 0)); 342 if (!lpc_bridge) { 343 lpc_bridge = pci_create_simple(pci_device_root_bus(&vdev->pdev), 344 PCI_DEVFN(0x1f, 0), "vfio-pci-igd-lpc-bridge"); 345 } 346 347 ret = vfio_pci_igd_copy(vdev, lpc_bridge, info, igd_lpc_bridge_infos, 348 ARRAY_SIZE(igd_lpc_bridge_infos)); 349 if (!ret) { 350 trace_vfio_pci_igd_lpc_bridge_enabled(vdev->vbasedev.name); 351 } 352 353 return ret; 354 } 355 356 static bool vfio_pci_igd_setup_lpc_bridge(VFIOPCIDevice *vdev, Error **errp) 357 { 358 g_autofree struct vfio_region_info *host = NULL; 359 g_autofree struct vfio_region_info *lpc = NULL; 360 PCIDevice *lpc_bridge; 361 int ret; 362 363 /* 364 * Copying IDs or creating new devices are not supported on hotplug 365 */ 366 if (vdev->pdev.qdev.hotplugged) { 367 error_setg(errp, "IGD LPC is not supported on hotplugged device"); 368 return false; 369 } 370 371 /* 372 * We need to create an LPC/ISA bridge at PCI bus address 00:1f.0 that we 373 * can stuff host values into, so if there's already one there and it's not 374 * one we can hack on, this quirk is no-go. Sorry Q35. 375 */ 376 lpc_bridge = pci_find_device(pci_device_root_bus(&vdev->pdev), 377 0, PCI_DEVFN(0x1f, 0)); 378 if (lpc_bridge && !object_dynamic_cast(OBJECT(lpc_bridge), 379 "vfio-pci-igd-lpc-bridge")) { 380 error_setg(errp, 381 "Cannot create LPC bridge due to existing device at 1f.0"); 382 return false; 383 } 384 385 /* 386 * Check whether we have all the vfio device specific regions to 387 * support LPC quirk (added in Linux v4.6). 388 */ 389 ret = vfio_device_get_region_info_type(&vdev->vbasedev, 390 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL, 391 VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG, &lpc); 392 if (ret) { 393 error_setg(errp, "IGD LPC bridge access is not supported by kernel"); 394 return false; 395 } 396 397 ret = vfio_device_get_region_info_type(&vdev->vbasedev, 398 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL, 399 VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG, &host); 400 if (ret) { 401 error_setg(errp, "IGD host bridge access is not supported by kernel"); 402 return false; 403 } 404 405 /* Create/modify LPC bridge */ 406 ret = vfio_pci_igd_lpc_init(vdev, lpc); 407 if (ret) { 408 error_setg(errp, "Failed to create/modify LPC bridge for IGD"); 409 return false; 410 } 411 412 /* Stuff some host values into the VM PCI host bridge */ 413 ret = vfio_pci_igd_host_init(vdev, host); 414 if (ret) { 415 error_setg(errp, "Failed to modify host bridge for IGD"); 416 return false; 417 } 418 419 return true; 420 } 421 422 #define IGD_GGC_MMIO_OFFSET 0x108040 423 #define IGD_BDSM_MMIO_OFFSET 0x1080C0 424 425 void vfio_probe_igd_bar0_quirk(VFIOPCIDevice *vdev, int nr) 426 { 427 VFIOQuirk *ggc_quirk, *bdsm_quirk; 428 VFIOConfigMirrorQuirk *ggc_mirror, *bdsm_mirror; 429 int gen; 430 431 /* 432 * This must be an Intel VGA device at address 00:02.0 for us to even 433 * consider enabling legacy mode. Some driver have dependencies on the PCI 434 * bus address. 435 */ 436 if (!vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, PCI_ANY_ID) || 437 !vfio_is_vga(vdev) || nr != 0) { 438 return; 439 } 440 441 /* 442 * Only on IGD devices of gen 11 and above, the BDSM register is mirrored 443 * into MMIO space and read from MMIO space by the Windows driver. 444 */ 445 gen = igd_gen(vdev); 446 if (gen < 6) { 447 return; 448 } 449 450 ggc_quirk = vfio_quirk_alloc(1); 451 ggc_mirror = ggc_quirk->data = g_malloc0(sizeof(*ggc_mirror)); 452 ggc_mirror->mem = ggc_quirk->mem; 453 ggc_mirror->vdev = vdev; 454 ggc_mirror->bar = nr; 455 ggc_mirror->offset = IGD_GGC_MMIO_OFFSET; 456 ggc_mirror->config_offset = IGD_GMCH; 457 458 memory_region_init_io(ggc_mirror->mem, OBJECT(vdev), 459 &vfio_generic_mirror_quirk, ggc_mirror, 460 "vfio-igd-ggc-quirk", 2); 461 memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, 462 ggc_mirror->offset, ggc_mirror->mem, 463 1); 464 465 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, ggc_quirk, next); 466 467 bdsm_quirk = vfio_quirk_alloc(1); 468 bdsm_mirror = bdsm_quirk->data = g_malloc0(sizeof(*bdsm_mirror)); 469 bdsm_mirror->mem = bdsm_quirk->mem; 470 bdsm_mirror->vdev = vdev; 471 bdsm_mirror->bar = nr; 472 bdsm_mirror->offset = IGD_BDSM_MMIO_OFFSET; 473 bdsm_mirror->config_offset = (gen < 11) ? IGD_BDSM : IGD_BDSM_GEN11; 474 475 memory_region_init_io(bdsm_mirror->mem, OBJECT(vdev), 476 &vfio_generic_mirror_quirk, bdsm_mirror, 477 "vfio-igd-bdsm-quirk", (gen < 11) ? 4 : 8); 478 memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, 479 bdsm_mirror->offset, bdsm_mirror->mem, 480 1); 481 482 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, bdsm_quirk, next); 483 } 484 485 static bool vfio_pci_igd_config_quirk(VFIOPCIDevice *vdev, Error **errp) 486 { 487 int ret, gen; 488 uint64_t gms_size; 489 uint64_t *bdsm_size; 490 uint32_t gmch; 491 bool legacy_mode_enabled = false; 492 Error *err = NULL; 493 494 /* 495 * This must be an Intel VGA device at address 00:02.0 for us to even 496 * consider enabling legacy mode. The vBIOS has dependencies on the 497 * PCI bus address. 498 */ 499 if (!vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, PCI_ANY_ID) || 500 !vfio_is_vga(vdev)) { 501 return true; 502 } 503 504 /* 505 * IGD is not a standard, they like to change their specs often. We 506 * only attempt to support back to SandBridge and we hope that newer 507 * devices maintain compatibility with generation 8. 508 */ 509 gen = igd_gen(vdev); 510 if (gen == -1) { 511 error_report("IGD device %s is unsupported in legacy mode, " 512 "try SandyBridge or newer", vdev->vbasedev.name); 513 return true; 514 } 515 516 gmch = vfio_pci_read_config(&vdev->pdev, IGD_GMCH, 4); 517 518 /* 519 * For backward compatibility, enable legacy mode when 520 * - Device geneation is 6 to 9 (including both) 521 * - Machine type is i440fx (pc_piix) 522 * - IGD device is at guest BDF 00:02.0 523 * - Not manually disabled by x-igd-legacy-mode=off 524 */ 525 if ((vdev->igd_legacy_mode != ON_OFF_AUTO_OFF) && 526 (gen >= 6 && gen <= 9) && 527 !strcmp(MACHINE_GET_CLASS(qdev_get_machine())->family, "pc_piix") && 528 (&vdev->pdev == pci_find_device(pci_device_root_bus(&vdev->pdev), 529 0, PCI_DEVFN(0x2, 0)))) { 530 /* 531 * IGD legacy mode requires: 532 * - VBIOS in ROM BAR or file 533 * - VGA IO/MMIO ranges are claimed by IGD 534 * - OpRegion 535 * - Same LPC bridge and Host bridge VID/DID/SVID/SSID as host 536 */ 537 g_autofree struct vfio_region_info *rom = NULL; 538 539 legacy_mode_enabled = true; 540 info_report("IGD legacy mode enabled, " 541 "use x-igd-legacy-mode=off to disable it if unwanted."); 542 543 /* 544 * Most of what we're doing here is to enable the ROM to run, so if 545 * there's no ROM, there's no point in setting up this quirk. 546 * NB. We only seem to get BIOS ROMs, so UEFI VM would need CSM support. 547 */ 548 ret = vfio_device_get_region_info(&vdev->vbasedev, 549 VFIO_PCI_ROM_REGION_INDEX, &rom); 550 if ((ret || !rom->size) && !vdev->pdev.romfile) { 551 error_setg(&err, "Device has no ROM"); 552 goto error; 553 } 554 555 /* 556 * If IGD VGA Disable is clear (expected) and VGA is not already 557 * enabled, try to enable it. Probably shouldn't be using legacy mode 558 * without VGA, but also no point in us enabling VGA if disabled in 559 * hardware. 560 */ 561 if (!(gmch & 0x2) && !vdev->vga && !vfio_populate_vga(vdev, &err)) { 562 error_setg(&err, "Unable to enable VGA access"); 563 goto error; 564 } 565 566 /* Enable OpRegion and LPC bridge quirk */ 567 vdev->features |= VFIO_FEATURE_ENABLE_IGD_OPREGION; 568 vdev->features |= VFIO_FEATURE_ENABLE_IGD_LPC; 569 } else if (vdev->igd_legacy_mode == ON_OFF_AUTO_ON) { 570 error_setg(&err, 571 "Machine is not i440fx, assigned BDF is not 00:02.0, " 572 "or device %04x (gen %d) doesn't support legacy mode", 573 vdev->device_id, gen); 574 goto error; 575 } 576 577 /* Setup OpRegion access */ 578 if ((vdev->features & VFIO_FEATURE_ENABLE_IGD_OPREGION) && 579 !vfio_pci_igd_setup_opregion(vdev, errp)) { 580 goto error; 581 } 582 583 /* Setup LPC bridge / Host bridge PCI IDs */ 584 if ((vdev->features & VFIO_FEATURE_ENABLE_IGD_LPC) && 585 !vfio_pci_igd_setup_lpc_bridge(vdev, errp)) { 586 goto error; 587 } 588 589 /* 590 * Allow user to override dsm size using x-igd-gms option, in multiples of 591 * 32MiB. This option should only be used when the desired size cannot be 592 * set from DVMT Pre-Allocated option in host BIOS. 593 */ 594 if (vdev->igd_gms) { 595 if (gen < 8) { 596 if (vdev->igd_gms <= 0x10) { 597 gmch &= ~(IGD_GMCH_GEN6_GMS_MASK << IGD_GMCH_GEN6_GMS_SHIFT); 598 gmch |= vdev->igd_gms << IGD_GMCH_GEN6_GMS_SHIFT; 599 } else { 600 error_report(QERR_INVALID_PARAMETER_VALUE, 601 "x-igd-gms", "0~0x10"); 602 } 603 } else { 604 if (vdev->igd_gms <= 0x40) { 605 gmch &= ~(IGD_GMCH_GEN8_GMS_MASK << IGD_GMCH_GEN8_GMS_SHIFT); 606 gmch |= vdev->igd_gms << IGD_GMCH_GEN8_GMS_SHIFT; 607 } else { 608 error_report(QERR_INVALID_PARAMETER_VALUE, 609 "x-igd-gms", "0~0x40"); 610 } 611 } 612 } 613 614 gms_size = igd_stolen_memory_size(gen, gmch); 615 616 /* 617 * Request reserved memory for stolen memory via fw_cfg. VM firmware 618 * must allocate a 1MB aligned reserved memory region below 4GB with 619 * the requested size (in bytes) for use by the Intel PCI class VGA 620 * device at VM address 00:02.0. The base address of this reserved 621 * memory region must be written to the device BDSM register at PCI 622 * config offset 0x5C. 623 */ 624 bdsm_size = g_malloc(sizeof(*bdsm_size)); 625 *bdsm_size = cpu_to_le64(gms_size); 626 fw_cfg_add_file(fw_cfg_find(), "etc/igd-bdsm-size", 627 bdsm_size, sizeof(*bdsm_size)); 628 629 /* GMCH is read-only, emulated */ 630 pci_set_long(vdev->pdev.config + IGD_GMCH, gmch); 631 pci_set_long(vdev->pdev.wmask + IGD_GMCH, 0); 632 pci_set_long(vdev->emulated_config_bits + IGD_GMCH, ~0); 633 634 /* BDSM is read-write, emulated. The BIOS needs to be able to write it */ 635 if (gen < 11) { 636 pci_set_long(vdev->pdev.config + IGD_BDSM, 0); 637 pci_set_long(vdev->pdev.wmask + IGD_BDSM, ~0); 638 pci_set_long(vdev->emulated_config_bits + IGD_BDSM, ~0); 639 } else { 640 pci_set_quad(vdev->pdev.config + IGD_BDSM_GEN11, 0); 641 pci_set_quad(vdev->pdev.wmask + IGD_BDSM_GEN11, ~0); 642 pci_set_quad(vdev->emulated_config_bits + IGD_BDSM_GEN11, ~0); 643 } 644 645 trace_vfio_pci_igd_bdsm_enabled(vdev->vbasedev.name, (gms_size / MiB)); 646 647 return true; 648 649 error: 650 /* 651 * When legacy mode is implicity enabled, continue on error, 652 * to keep compatibility 653 */ 654 if (legacy_mode_enabled && (vdev->igd_legacy_mode == ON_OFF_AUTO_AUTO)) { 655 error_report_err(err); 656 error_report("IGD legacy mode disabled"); 657 return true; 658 } 659 660 error_propagate(errp, err); 661 return false; 662 } 663 664 /* 665 * KVMGT/GVT-g vGPU exposes an emulated OpRegion. So far, users have to specify 666 * x-igd-opregion=on to enable the access. 667 * TODO: Check VID/DID and enable opregion access automatically 668 */ 669 static bool vfio_pci_kvmgt_config_quirk(VFIOPCIDevice *vdev, Error **errp) 670 { 671 if ((vdev->features & VFIO_FEATURE_ENABLE_IGD_OPREGION) && 672 !vfio_pci_igd_setup_opregion(vdev, errp)) { 673 return false; 674 } 675 676 return true; 677 } 678 679 bool vfio_probe_igd_config_quirk(VFIOPCIDevice *vdev, Error **errp) 680 { 681 /* KVMGT/GVT-g vGPU is exposed as mdev */ 682 if (vdev->vbasedev.mdev) { 683 return vfio_pci_kvmgt_config_quirk(vdev, errp); 684 } 685 686 return vfio_pci_igd_config_quirk(vdev, errp); 687 } 688