1 /* 2 * IGD device quirks 3 * 4 * Copyright Red Hat, Inc. 2016 5 * 6 * Authors: 7 * Alex Williamson <alex.williamson@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2. See 10 * the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qemu/units.h" 15 #include "qemu/error-report.h" 16 #include "qapi/error.h" 17 #include "qapi/qmp/qerror.h" 18 #include "hw/hw.h" 19 #include "hw/nvram/fw_cfg.h" 20 #include "pci.h" 21 #include "pci-quirks.h" 22 #include "trace.h" 23 24 /* 25 * Intel IGD support 26 * 27 * Obviously IGD is not a discrete device, this is evidenced not only by it 28 * being integrated into the CPU, but by the various chipset and BIOS 29 * dependencies that it brings along with it. Intel is trying to move away 30 * from this and Broadwell and newer devices can run in what Intel calls 31 * "Universal Pass-Through" mode, or UPT. Theoretically in UPT mode, nothing 32 * more is required beyond assigning the IGD device to a VM. There are 33 * however support limitations to this mode. It only supports IGD as a 34 * secondary graphics device in the VM and it doesn't officially support any 35 * physical outputs. 36 * 37 * The code here attempts to enable what we'll call legacy mode assignment, 38 * IGD retains most of the capabilities we expect for it to have on bare 39 * metal. To enable this mode, the IGD device must be assigned to the VM 40 * at PCI address 00:02.0, it must have a ROM, it very likely needs VGA 41 * support, we must have VM BIOS support for reserving and populating some 42 * of the required tables, and we need to tweak the chipset with revisions 43 * and IDs and an LPC/ISA bridge device. The intention is to make all of 44 * this happen automatically by installing the device at the correct VM PCI 45 * bus address. If any of the conditions are not met, we cross our fingers 46 * and hope the user knows better. 47 * 48 * NB - It is possible to enable physical outputs in UPT mode by supplying 49 * an OpRegion table. We don't do this by default because the guest driver 50 * behaves differently if an OpRegion is provided and no monitor is attached 51 * vs no OpRegion and a monitor being attached or not. Effectively, if a 52 * headless setup is desired, the OpRegion gets in the way of that. 53 */ 54 55 /* 56 * This presumes the device is already known to be an Intel VGA device, so we 57 * take liberties in which device ID bits match which generation. This should 58 * not be taken as an indication that all the devices are supported, or even 59 * supportable, some of them don't even support VT-d. 60 * See linux:include/drm/i915_pciids.h for IDs. 61 */ 62 static int igd_gen(VFIOPCIDevice *vdev) 63 { 64 /* 65 * Device IDs for Broxton/Apollo Lake are 0x0a84, 0x1a84, 0x1a85, 0x5a84 66 * and 0x5a85, match bit 11:1 here 67 * Prefix 0x0a is taken by Haswell, this rule should be matched first. 68 */ 69 if ((vdev->device_id & 0xffe) == 0xa84) { 70 return 9; 71 } 72 73 switch (vdev->device_id & 0xff00) { 74 case 0x0100: /* SandyBridge, IvyBridge */ 75 return 6; 76 case 0x0400: /* Haswell */ 77 case 0x0a00: /* Haswell */ 78 case 0x0c00: /* Haswell */ 79 case 0x0d00: /* Haswell */ 80 case 0x0f00: /* Valleyview/Bay Trail */ 81 return 7; 82 case 0x1600: /* Broadwell */ 83 case 0x2200: /* Cherryview */ 84 return 8; 85 case 0x1900: /* Skylake */ 86 case 0x3100: /* Gemini Lake */ 87 case 0x5900: /* Kaby Lake */ 88 case 0x3e00: /* Coffee Lake */ 89 case 0x9B00: /* Comet Lake */ 90 return 9; 91 case 0x8A00: /* Ice Lake */ 92 case 0x4500: /* Elkhart Lake */ 93 case 0x4E00: /* Jasper Lake */ 94 return 11; 95 case 0x9A00: /* Tiger Lake */ 96 case 0x4C00: /* Rocket Lake */ 97 case 0x4600: /* Alder Lake */ 98 case 0xA700: /* Raptor Lake */ 99 return 12; 100 } 101 102 /* 103 * Unfortunately, Intel changes it's specification quite often. This makes 104 * it impossible to use a suitable default value for unknown devices. 105 */ 106 return -1; 107 } 108 109 #define IGD_ASLS 0xfc /* ASL Storage Register */ 110 #define IGD_GMCH 0x50 /* Graphics Control Register */ 111 #define IGD_BDSM 0x5c /* Base Data of Stolen Memory */ 112 #define IGD_BDSM_GEN11 0xc0 /* Base Data of Stolen Memory of gen 11 and later */ 113 114 #define IGD_GMCH_GEN6_GMS_SHIFT 3 /* SNB_GMCH in i915 */ 115 #define IGD_GMCH_GEN6_GMS_MASK 0x1f 116 #define IGD_GMCH_GEN8_GMS_SHIFT 8 /* BDW_GMCH in i915 */ 117 #define IGD_GMCH_GEN8_GMS_MASK 0xff 118 119 static uint64_t igd_stolen_memory_size(int gen, uint32_t gmch) 120 { 121 uint64_t gms; 122 123 if (gen < 8) { 124 gms = (gmch >> IGD_GMCH_GEN6_GMS_SHIFT) & IGD_GMCH_GEN6_GMS_MASK; 125 } else { 126 gms = (gmch >> IGD_GMCH_GEN8_GMS_SHIFT) & IGD_GMCH_GEN8_GMS_MASK; 127 } 128 129 if (gen < 9) { 130 return gms * 32 * MiB; 131 } else { 132 if (gms < 0xf0) { 133 return gms * 32 * MiB; 134 } else { 135 return (gms - 0xf0 + 1) * 4 * MiB; 136 } 137 } 138 139 return 0; 140 } 141 142 /* 143 * The OpRegion includes the Video BIOS Table, which seems important for 144 * telling the driver what sort of outputs it has. Without this, the device 145 * may work in the guest, but we may not get output. This also requires BIOS 146 * support to reserve and populate a section of guest memory sufficient for 147 * the table and to write the base address of that memory to the ASLS register 148 * of the IGD device. 149 */ 150 static bool vfio_pci_igd_opregion_init(VFIOPCIDevice *vdev, 151 struct vfio_region_info *info, 152 Error **errp) 153 { 154 int ret; 155 156 vdev->igd_opregion = g_malloc0(info->size); 157 ret = pread(vdev->vbasedev.fd, vdev->igd_opregion, 158 info->size, info->offset); 159 if (ret != info->size) { 160 error_setg(errp, "failed to read IGD OpRegion"); 161 g_free(vdev->igd_opregion); 162 vdev->igd_opregion = NULL; 163 return false; 164 } 165 166 /* 167 * Provide fw_cfg with a copy of the OpRegion which the VM firmware is to 168 * allocate 32bit reserved memory for, copy these contents into, and write 169 * the reserved memory base address to the device ASLS register at 0xFC. 170 * Alignment of this reserved region seems flexible, but using a 4k page 171 * alignment seems to work well. This interface assumes a single IGD 172 * device, which may be at VM address 00:02.0 in legacy mode or another 173 * address in UPT mode. 174 * 175 * NB, there may be future use cases discovered where the VM should have 176 * direct interaction with the host OpRegion, in which case the write to 177 * the ASLS register would trigger MemoryRegion setup to enable that. 178 */ 179 fw_cfg_add_file(fw_cfg_find(), "etc/igd-opregion", 180 vdev->igd_opregion, info->size); 181 182 trace_vfio_pci_igd_opregion_enabled(vdev->vbasedev.name); 183 184 pci_set_long(vdev->pdev.config + IGD_ASLS, 0); 185 pci_set_long(vdev->pdev.wmask + IGD_ASLS, ~0); 186 pci_set_long(vdev->emulated_config_bits + IGD_ASLS, ~0); 187 188 return true; 189 } 190 191 bool vfio_pci_igd_setup_opregion(VFIOPCIDevice *vdev, Error **errp) 192 { 193 g_autofree struct vfio_region_info *opregion = NULL; 194 int ret; 195 196 /* Hotplugging is not supported for opregion access */ 197 if (vdev->pdev.qdev.hotplugged) { 198 error_setg(errp, "IGD OpRegion is not supported on hotplugged device"); 199 return false; 200 } 201 202 ret = vfio_get_dev_region_info(&vdev->vbasedev, 203 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL, 204 VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION, &opregion); 205 if (ret) { 206 error_setg_errno(errp, -ret, 207 "Device does not supports IGD OpRegion feature"); 208 return false; 209 } 210 211 if (!vfio_pci_igd_opregion_init(vdev, opregion, errp)) { 212 return false; 213 } 214 215 return true; 216 } 217 218 /* 219 * The rather short list of registers that we copy from the host devices. 220 * The LPC/ISA bridge values are definitely needed to support the vBIOS, the 221 * host bridge values may or may not be needed depending on the guest OS. 222 * Since we're only munging revision and subsystem values on the host bridge, 223 * we don't require our own device. The LPC/ISA bridge needs to be our very 224 * own though. 225 */ 226 typedef struct { 227 uint8_t offset; 228 uint8_t len; 229 } IGDHostInfo; 230 231 static const IGDHostInfo igd_host_bridge_infos[] = { 232 {PCI_REVISION_ID, 2}, 233 {PCI_SUBSYSTEM_VENDOR_ID, 2}, 234 {PCI_SUBSYSTEM_ID, 2}, 235 }; 236 237 static const IGDHostInfo igd_lpc_bridge_infos[] = { 238 {PCI_VENDOR_ID, 2}, 239 {PCI_DEVICE_ID, 2}, 240 {PCI_REVISION_ID, 2}, 241 {PCI_SUBSYSTEM_VENDOR_ID, 2}, 242 {PCI_SUBSYSTEM_ID, 2}, 243 }; 244 245 static int vfio_pci_igd_copy(VFIOPCIDevice *vdev, PCIDevice *pdev, 246 struct vfio_region_info *info, 247 const IGDHostInfo *list, int len) 248 { 249 int i, ret; 250 251 for (i = 0; i < len; i++) { 252 ret = pread(vdev->vbasedev.fd, pdev->config + list[i].offset, 253 list[i].len, info->offset + list[i].offset); 254 if (ret != list[i].len) { 255 error_report("IGD copy failed: %m"); 256 return -errno; 257 } 258 } 259 260 return 0; 261 } 262 263 /* 264 * Stuff a few values into the host bridge. 265 */ 266 static int vfio_pci_igd_host_init(VFIOPCIDevice *vdev, 267 struct vfio_region_info *info) 268 { 269 PCIBus *bus; 270 PCIDevice *host_bridge; 271 int ret; 272 273 bus = pci_device_root_bus(&vdev->pdev); 274 host_bridge = pci_find_device(bus, 0, PCI_DEVFN(0, 0)); 275 276 if (!host_bridge) { 277 error_report("Can't find host bridge"); 278 return -ENODEV; 279 } 280 281 ret = vfio_pci_igd_copy(vdev, host_bridge, info, igd_host_bridge_infos, 282 ARRAY_SIZE(igd_host_bridge_infos)); 283 if (!ret) { 284 trace_vfio_pci_igd_host_bridge_enabled(vdev->vbasedev.name); 285 } 286 287 return ret; 288 } 289 290 /* 291 * IGD LPC/ISA bridge support code. The vBIOS needs this, but we can't write 292 * arbitrary values into just any bridge, so we must create our own. We try 293 * to handle if the user has created it for us, which they might want to do 294 * to enable multifunction so we don't occupy the whole PCI slot. 295 */ 296 static void vfio_pci_igd_lpc_bridge_realize(PCIDevice *pdev, Error **errp) 297 { 298 if (pdev->devfn != PCI_DEVFN(0x1f, 0)) { 299 error_setg(errp, "VFIO dummy ISA/LPC bridge must have address 1f.0"); 300 } 301 } 302 303 static void vfio_pci_igd_lpc_bridge_class_init(ObjectClass *klass, void *data) 304 { 305 DeviceClass *dc = DEVICE_CLASS(klass); 306 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 307 308 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 309 dc->desc = "VFIO dummy ISA/LPC bridge for IGD assignment"; 310 dc->hotpluggable = false; 311 k->realize = vfio_pci_igd_lpc_bridge_realize; 312 k->class_id = PCI_CLASS_BRIDGE_ISA; 313 } 314 315 static const TypeInfo vfio_pci_igd_lpc_bridge_info = { 316 .name = "vfio-pci-igd-lpc-bridge", 317 .parent = TYPE_PCI_DEVICE, 318 .class_init = vfio_pci_igd_lpc_bridge_class_init, 319 .interfaces = (InterfaceInfo[]) { 320 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 321 { }, 322 }, 323 }; 324 325 static void vfio_pci_igd_register_types(void) 326 { 327 type_register_static(&vfio_pci_igd_lpc_bridge_info); 328 } 329 330 type_init(vfio_pci_igd_register_types) 331 332 static int vfio_pci_igd_lpc_init(VFIOPCIDevice *vdev, 333 struct vfio_region_info *info) 334 { 335 PCIDevice *lpc_bridge; 336 int ret; 337 338 lpc_bridge = pci_find_device(pci_device_root_bus(&vdev->pdev), 339 0, PCI_DEVFN(0x1f, 0)); 340 if (!lpc_bridge) { 341 lpc_bridge = pci_create_simple(pci_device_root_bus(&vdev->pdev), 342 PCI_DEVFN(0x1f, 0), "vfio-pci-igd-lpc-bridge"); 343 } 344 345 ret = vfio_pci_igd_copy(vdev, lpc_bridge, info, igd_lpc_bridge_infos, 346 ARRAY_SIZE(igd_lpc_bridge_infos)); 347 if (!ret) { 348 trace_vfio_pci_igd_lpc_bridge_enabled(vdev->vbasedev.name); 349 } 350 351 return ret; 352 } 353 354 static bool vfio_pci_igd_setup_lpc_bridge(VFIOPCIDevice *vdev, Error **errp) 355 { 356 g_autofree struct vfio_region_info *host = NULL; 357 g_autofree struct vfio_region_info *lpc = NULL; 358 PCIDevice *lpc_bridge; 359 int ret; 360 361 /* 362 * Copying IDs or creating new devices are not supported on hotplug 363 */ 364 if (vdev->pdev.qdev.hotplugged) { 365 error_setg(errp, "IGD LPC is not supported on hotplugged device"); 366 return false; 367 } 368 369 /* 370 * We need to create an LPC/ISA bridge at PCI bus address 00:1f.0 that we 371 * can stuff host values into, so if there's already one there and it's not 372 * one we can hack on, this quirk is no-go. Sorry Q35. 373 */ 374 lpc_bridge = pci_find_device(pci_device_root_bus(&vdev->pdev), 375 0, PCI_DEVFN(0x1f, 0)); 376 if (lpc_bridge && !object_dynamic_cast(OBJECT(lpc_bridge), 377 "vfio-pci-igd-lpc-bridge")) { 378 error_setg(errp, 379 "Cannot create LPC bridge due to existing device at 1f.0"); 380 return false; 381 } 382 383 /* 384 * Check whether we have all the vfio device specific regions to 385 * support LPC quirk (added in Linux v4.6). 386 */ 387 ret = vfio_get_dev_region_info(&vdev->vbasedev, 388 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL, 389 VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG, &lpc); 390 if (ret) { 391 error_setg(errp, "IGD LPC bridge access is not supported by kernel"); 392 return false; 393 } 394 395 ret = vfio_get_dev_region_info(&vdev->vbasedev, 396 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL, 397 VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG, &host); 398 if (ret) { 399 error_setg(errp, "IGD host bridge access is not supported by kernel"); 400 return false; 401 } 402 403 /* Create/modify LPC bridge */ 404 ret = vfio_pci_igd_lpc_init(vdev, lpc); 405 if (ret) { 406 error_setg(errp, "Failed to create/modify LPC bridge for IGD"); 407 return false; 408 } 409 410 /* Stuff some host values into the VM PCI host bridge */ 411 ret = vfio_pci_igd_host_init(vdev, host); 412 if (ret) { 413 error_setg(errp, "Failed to modify host bridge for IGD"); 414 return false; 415 } 416 417 return true; 418 } 419 420 #define IGD_GGC_MMIO_OFFSET 0x108040 421 #define IGD_BDSM_MMIO_OFFSET 0x1080C0 422 423 void vfio_probe_igd_bar0_quirk(VFIOPCIDevice *vdev, int nr) 424 { 425 VFIOQuirk *ggc_quirk, *bdsm_quirk; 426 VFIOConfigMirrorQuirk *ggc_mirror, *bdsm_mirror; 427 int gen; 428 429 /* 430 * This must be an Intel VGA device at address 00:02.0 for us to even 431 * consider enabling legacy mode. Some driver have dependencies on the PCI 432 * bus address. 433 */ 434 if (!vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, PCI_ANY_ID) || 435 !vfio_is_vga(vdev) || nr != 0 || 436 &vdev->pdev != pci_find_device(pci_device_root_bus(&vdev->pdev), 437 0, PCI_DEVFN(0x2, 0))) { 438 return; 439 } 440 441 /* 442 * Only on IGD devices of gen 11 and above, the BDSM register is mirrored 443 * into MMIO space and read from MMIO space by the Windows driver. 444 */ 445 gen = igd_gen(vdev); 446 if (gen < 6) { 447 return; 448 } 449 450 ggc_quirk = vfio_quirk_alloc(1); 451 ggc_mirror = ggc_quirk->data = g_malloc0(sizeof(*ggc_mirror)); 452 ggc_mirror->mem = ggc_quirk->mem; 453 ggc_mirror->vdev = vdev; 454 ggc_mirror->bar = nr; 455 ggc_mirror->offset = IGD_GGC_MMIO_OFFSET; 456 ggc_mirror->config_offset = IGD_GMCH; 457 458 memory_region_init_io(ggc_mirror->mem, OBJECT(vdev), 459 &vfio_generic_mirror_quirk, ggc_mirror, 460 "vfio-igd-ggc-quirk", 2); 461 memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, 462 ggc_mirror->offset, ggc_mirror->mem, 463 1); 464 465 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, ggc_quirk, next); 466 467 bdsm_quirk = vfio_quirk_alloc(1); 468 bdsm_mirror = bdsm_quirk->data = g_malloc0(sizeof(*bdsm_mirror)); 469 bdsm_mirror->mem = bdsm_quirk->mem; 470 bdsm_mirror->vdev = vdev; 471 bdsm_mirror->bar = nr; 472 bdsm_mirror->offset = IGD_BDSM_MMIO_OFFSET; 473 bdsm_mirror->config_offset = (gen < 11) ? IGD_BDSM : IGD_BDSM_GEN11; 474 475 memory_region_init_io(bdsm_mirror->mem, OBJECT(vdev), 476 &vfio_generic_mirror_quirk, bdsm_mirror, 477 "vfio-igd-bdsm-quirk", (gen < 11) ? 4 : 8); 478 memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, 479 bdsm_mirror->offset, bdsm_mirror->mem, 480 1); 481 482 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, bdsm_quirk, next); 483 } 484 485 bool vfio_probe_igd_config_quirk(VFIOPCIDevice *vdev, 486 Error **errp G_GNUC_UNUSED) 487 { 488 g_autofree struct vfio_region_info *rom = NULL; 489 int ret, gen; 490 uint64_t gms_size; 491 uint64_t *bdsm_size; 492 uint32_t gmch; 493 Error *err = NULL; 494 495 /* 496 * This must be an Intel VGA device at address 00:02.0 for us to even 497 * consider enabling legacy mode. The vBIOS has dependencies on the 498 * PCI bus address. 499 */ 500 if (!vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, PCI_ANY_ID) || 501 !vfio_is_vga(vdev) || 502 &vdev->pdev != pci_find_device(pci_device_root_bus(&vdev->pdev), 503 0, PCI_DEVFN(0x2, 0))) { 504 return true; 505 } 506 507 /* 508 * IGD is not a standard, they like to change their specs often. We 509 * only attempt to support back to SandBridge and we hope that newer 510 * devices maintain compatibility with generation 8. 511 */ 512 gen = igd_gen(vdev); 513 if (gen == -1) { 514 error_report("IGD device %s is unsupported in legacy mode, " 515 "try SandyBridge or newer", vdev->vbasedev.name); 516 return true; 517 } 518 519 /* 520 * Most of what we're doing here is to enable the ROM to run, so if 521 * there's no ROM, there's no point in setting up this quirk. 522 * NB. We only seem to get BIOS ROMs, so a UEFI VM would need CSM support. 523 */ 524 ret = vfio_get_region_info(&vdev->vbasedev, 525 VFIO_PCI_ROM_REGION_INDEX, &rom); 526 if ((ret || !rom->size) && !vdev->pdev.romfile) { 527 error_report("IGD device %s has no ROM, legacy mode disabled", 528 vdev->vbasedev.name); 529 return true; 530 } 531 532 /* 533 * Ignore the hotplug corner case, mark the ROM failed, we can't 534 * create the devices we need for legacy mode in the hotplug scenario. 535 */ 536 if (vdev->pdev.qdev.hotplugged) { 537 error_report("IGD device %s hotplugged, ROM disabled, " 538 "legacy mode disabled", vdev->vbasedev.name); 539 vdev->rom_read_failed = true; 540 return true; 541 } 542 543 gmch = vfio_pci_read_config(&vdev->pdev, IGD_GMCH, 4); 544 545 /* 546 * If IGD VGA Disable is clear (expected) and VGA is not already enabled, 547 * try to enable it. Probably shouldn't be using legacy mode without VGA, 548 * but also no point in us enabling VGA if disabled in hardware. 549 */ 550 if (!(gmch & 0x2) && !vdev->vga && !vfio_populate_vga(vdev, &err)) { 551 error_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name); 552 error_report("IGD device %s failed to enable VGA access, " 553 "legacy mode disabled", vdev->vbasedev.name); 554 return true; 555 } 556 557 /* Setup OpRegion access */ 558 if (!vfio_pci_igd_setup_opregion(vdev, &err)) { 559 error_append_hint(&err, "IGD legacy mode disabled\n"); 560 error_report_err(err); 561 return true; 562 } 563 564 /* Setup LPC bridge / Host bridge PCI IDs */ 565 if (!vfio_pci_igd_setup_lpc_bridge(vdev, &err)) { 566 error_append_hint(&err, "IGD legacy mode disabled\n"); 567 error_report_err(err); 568 return true; 569 } 570 571 /* 572 * Allow user to override dsm size using x-igd-gms option, in multiples of 573 * 32MiB. This option should only be used when the desired size cannot be 574 * set from DVMT Pre-Allocated option in host BIOS. 575 */ 576 if (vdev->igd_gms) { 577 if (gen < 8) { 578 if (vdev->igd_gms <= 0x10) { 579 gmch &= ~(IGD_GMCH_GEN6_GMS_MASK << IGD_GMCH_GEN6_GMS_SHIFT); 580 gmch |= vdev->igd_gms << IGD_GMCH_GEN6_GMS_SHIFT; 581 } else { 582 error_report(QERR_INVALID_PARAMETER_VALUE, 583 "x-igd-gms", "0~0x10"); 584 } 585 } else { 586 if (vdev->igd_gms <= 0x40) { 587 gmch &= ~(IGD_GMCH_GEN8_GMS_MASK << IGD_GMCH_GEN8_GMS_SHIFT); 588 gmch |= vdev->igd_gms << IGD_GMCH_GEN8_GMS_SHIFT; 589 } else { 590 error_report(QERR_INVALID_PARAMETER_VALUE, 591 "x-igd-gms", "0~0x40"); 592 } 593 } 594 } 595 596 gms_size = igd_stolen_memory_size(gen, gmch); 597 598 /* 599 * Request reserved memory for stolen memory via fw_cfg. VM firmware 600 * must allocate a 1MB aligned reserved memory region below 4GB with 601 * the requested size (in bytes) for use by the Intel PCI class VGA 602 * device at VM address 00:02.0. The base address of this reserved 603 * memory region must be written to the device BDSM register at PCI 604 * config offset 0x5C. 605 */ 606 bdsm_size = g_malloc(sizeof(*bdsm_size)); 607 *bdsm_size = cpu_to_le64(gms_size); 608 fw_cfg_add_file(fw_cfg_find(), "etc/igd-bdsm-size", 609 bdsm_size, sizeof(*bdsm_size)); 610 611 /* GMCH is read-only, emulated */ 612 pci_set_long(vdev->pdev.config + IGD_GMCH, gmch); 613 pci_set_long(vdev->pdev.wmask + IGD_GMCH, 0); 614 pci_set_long(vdev->emulated_config_bits + IGD_GMCH, ~0); 615 616 /* BDSM is read-write, emulated. The BIOS needs to be able to write it */ 617 if (gen < 11) { 618 pci_set_long(vdev->pdev.config + IGD_BDSM, 0); 619 pci_set_long(vdev->pdev.wmask + IGD_BDSM, ~0); 620 pci_set_long(vdev->emulated_config_bits + IGD_BDSM, ~0); 621 } else { 622 pci_set_quad(vdev->pdev.config + IGD_BDSM_GEN11, 0); 623 pci_set_quad(vdev->pdev.wmask + IGD_BDSM_GEN11, ~0); 624 pci_set_quad(vdev->emulated_config_bits + IGD_BDSM_GEN11, ~0); 625 } 626 627 trace_vfio_pci_igd_bdsm_enabled(vdev->vbasedev.name, (gms_size / MiB)); 628 629 return true; 630 } 631