1 /* 2 * IGD device quirks 3 * 4 * Copyright Red Hat, Inc. 2016 5 * 6 * Authors: 7 * Alex Williamson <alex.williamson@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2. See 10 * the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qemu/units.h" 15 #include "qemu/error-report.h" 16 #include "qapi/error.h" 17 #include "qapi/qmp/qerror.h" 18 #include "hw/boards.h" 19 #include "hw/hw.h" 20 #include "hw/nvram/fw_cfg.h" 21 #include "pci.h" 22 #include "pci-quirks.h" 23 #include "trace.h" 24 25 /* 26 * Intel IGD support 27 * 28 * Obviously IGD is not a discrete device, this is evidenced not only by it 29 * being integrated into the CPU, but by the various chipset and BIOS 30 * dependencies that it brings along with it. Intel is trying to move away 31 * from this and Broadwell and newer devices can run in what Intel calls 32 * "Universal Pass-Through" mode, or UPT. Theoretically in UPT mode, nothing 33 * more is required beyond assigning the IGD device to a VM. There are 34 * however support limitations to this mode. It only supports IGD as a 35 * secondary graphics device in the VM and it doesn't officially support any 36 * physical outputs. 37 * 38 * The code here attempts to enable what we'll call legacy mode assignment, 39 * IGD retains most of the capabilities we expect for it to have on bare 40 * metal. To enable this mode, the IGD device must be assigned to the VM 41 * at PCI address 00:02.0, it must have a ROM, it very likely needs VGA 42 * support, we must have VM BIOS support for reserving and populating some 43 * of the required tables, and we need to tweak the chipset with revisions 44 * and IDs and an LPC/ISA bridge device. The intention is to make all of 45 * this happen automatically by installing the device at the correct VM PCI 46 * bus address. If any of the conditions are not met, we cross our fingers 47 * and hope the user knows better. 48 * 49 * NB - It is possible to enable physical outputs in UPT mode by supplying 50 * an OpRegion table. We don't do this by default because the guest driver 51 * behaves differently if an OpRegion is provided and no monitor is attached 52 * vs no OpRegion and a monitor being attached or not. Effectively, if a 53 * headless setup is desired, the OpRegion gets in the way of that. 54 */ 55 56 /* 57 * This presumes the device is already known to be an Intel VGA device, so we 58 * take liberties in which device ID bits match which generation. This should 59 * not be taken as an indication that all the devices are supported, or even 60 * supportable, some of them don't even support VT-d. 61 * See linux:include/drm/i915_pciids.h for IDs. 62 */ 63 static int igd_gen(VFIOPCIDevice *vdev) 64 { 65 /* 66 * Device IDs for Broxton/Apollo Lake are 0x0a84, 0x1a84, 0x1a85, 0x5a84 67 * and 0x5a85, match bit 11:1 here 68 * Prefix 0x0a is taken by Haswell, this rule should be matched first. 69 */ 70 if ((vdev->device_id & 0xffe) == 0xa84) { 71 return 9; 72 } 73 74 switch (vdev->device_id & 0xff00) { 75 case 0x0100: /* SandyBridge, IvyBridge */ 76 return 6; 77 case 0x0400: /* Haswell */ 78 case 0x0a00: /* Haswell */ 79 case 0x0c00: /* Haswell */ 80 case 0x0d00: /* Haswell */ 81 case 0x0f00: /* Valleyview/Bay Trail */ 82 return 7; 83 case 0x1600: /* Broadwell */ 84 case 0x2200: /* Cherryview */ 85 return 8; 86 case 0x1900: /* Skylake */ 87 case 0x3100: /* Gemini Lake */ 88 case 0x5900: /* Kaby Lake */ 89 case 0x3e00: /* Coffee Lake */ 90 case 0x9B00: /* Comet Lake */ 91 return 9; 92 case 0x8A00: /* Ice Lake */ 93 case 0x4500: /* Elkhart Lake */ 94 case 0x4E00: /* Jasper Lake */ 95 return 11; 96 case 0x9A00: /* Tiger Lake */ 97 case 0x4C00: /* Rocket Lake */ 98 case 0x4600: /* Alder Lake */ 99 case 0xA700: /* Raptor Lake */ 100 return 12; 101 } 102 103 /* 104 * Unfortunately, Intel changes it's specification quite often. This makes 105 * it impossible to use a suitable default value for unknown devices. 106 */ 107 return -1; 108 } 109 110 #define IGD_ASLS 0xfc /* ASL Storage Register */ 111 #define IGD_GMCH 0x50 /* Graphics Control Register */ 112 #define IGD_BDSM 0x5c /* Base Data of Stolen Memory */ 113 #define IGD_BDSM_GEN11 0xc0 /* Base Data of Stolen Memory of gen 11 and later */ 114 115 #define IGD_GMCH_GEN6_GMS_SHIFT 3 /* SNB_GMCH in i915 */ 116 #define IGD_GMCH_GEN6_GMS_MASK 0x1f 117 #define IGD_GMCH_GEN8_GMS_SHIFT 8 /* BDW_GMCH in i915 */ 118 #define IGD_GMCH_GEN8_GMS_MASK 0xff 119 120 static uint64_t igd_stolen_memory_size(int gen, uint32_t gmch) 121 { 122 uint64_t gms; 123 124 if (gen < 8) { 125 gms = (gmch >> IGD_GMCH_GEN6_GMS_SHIFT) & IGD_GMCH_GEN6_GMS_MASK; 126 } else { 127 gms = (gmch >> IGD_GMCH_GEN8_GMS_SHIFT) & IGD_GMCH_GEN8_GMS_MASK; 128 } 129 130 if (gen < 9) { 131 return gms * 32 * MiB; 132 } else { 133 if (gms < 0xf0) { 134 return gms * 32 * MiB; 135 } else { 136 return (gms - 0xf0 + 1) * 4 * MiB; 137 } 138 } 139 140 return 0; 141 } 142 143 /* 144 * The OpRegion includes the Video BIOS Table, which seems important for 145 * telling the driver what sort of outputs it has. Without this, the device 146 * may work in the guest, but we may not get output. This also requires BIOS 147 * support to reserve and populate a section of guest memory sufficient for 148 * the table and to write the base address of that memory to the ASLS register 149 * of the IGD device. 150 */ 151 static bool vfio_pci_igd_opregion_init(VFIOPCIDevice *vdev, 152 struct vfio_region_info *info, 153 Error **errp) 154 { 155 int ret; 156 157 vdev->igd_opregion = g_malloc0(info->size); 158 ret = pread(vdev->vbasedev.fd, vdev->igd_opregion, 159 info->size, info->offset); 160 if (ret != info->size) { 161 error_setg(errp, "failed to read IGD OpRegion"); 162 g_free(vdev->igd_opregion); 163 vdev->igd_opregion = NULL; 164 return false; 165 } 166 167 /* 168 * Provide fw_cfg with a copy of the OpRegion which the VM firmware is to 169 * allocate 32bit reserved memory for, copy these contents into, and write 170 * the reserved memory base address to the device ASLS register at 0xFC. 171 * Alignment of this reserved region seems flexible, but using a 4k page 172 * alignment seems to work well. This interface assumes a single IGD 173 * device, which may be at VM address 00:02.0 in legacy mode or another 174 * address in UPT mode. 175 * 176 * NB, there may be future use cases discovered where the VM should have 177 * direct interaction with the host OpRegion, in which case the write to 178 * the ASLS register would trigger MemoryRegion setup to enable that. 179 */ 180 fw_cfg_add_file(fw_cfg_find(), "etc/igd-opregion", 181 vdev->igd_opregion, info->size); 182 183 trace_vfio_pci_igd_opregion_enabled(vdev->vbasedev.name); 184 185 pci_set_long(vdev->pdev.config + IGD_ASLS, 0); 186 pci_set_long(vdev->pdev.wmask + IGD_ASLS, ~0); 187 pci_set_long(vdev->emulated_config_bits + IGD_ASLS, ~0); 188 189 return true; 190 } 191 192 static bool vfio_pci_igd_setup_opregion(VFIOPCIDevice *vdev, Error **errp) 193 { 194 g_autofree struct vfio_region_info *opregion = NULL; 195 int ret; 196 197 /* Hotplugging is not supported for opregion access */ 198 if (vdev->pdev.qdev.hotplugged) { 199 error_setg(errp, "IGD OpRegion is not supported on hotplugged device"); 200 return false; 201 } 202 203 ret = vfio_get_dev_region_info(&vdev->vbasedev, 204 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL, 205 VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION, &opregion); 206 if (ret) { 207 error_setg_errno(errp, -ret, 208 "Device does not supports IGD OpRegion feature"); 209 return false; 210 } 211 212 if (!vfio_pci_igd_opregion_init(vdev, opregion, errp)) { 213 return false; 214 } 215 216 return true; 217 } 218 219 /* 220 * The rather short list of registers that we copy from the host devices. 221 * The LPC/ISA bridge values are definitely needed to support the vBIOS, the 222 * host bridge values may or may not be needed depending on the guest OS. 223 * Since we're only munging revision and subsystem values on the host bridge, 224 * we don't require our own device. The LPC/ISA bridge needs to be our very 225 * own though. 226 */ 227 typedef struct { 228 uint8_t offset; 229 uint8_t len; 230 } IGDHostInfo; 231 232 static const IGDHostInfo igd_host_bridge_infos[] = { 233 {PCI_REVISION_ID, 2}, 234 {PCI_SUBSYSTEM_VENDOR_ID, 2}, 235 {PCI_SUBSYSTEM_ID, 2}, 236 }; 237 238 static const IGDHostInfo igd_lpc_bridge_infos[] = { 239 {PCI_VENDOR_ID, 2}, 240 {PCI_DEVICE_ID, 2}, 241 {PCI_REVISION_ID, 2}, 242 {PCI_SUBSYSTEM_VENDOR_ID, 2}, 243 {PCI_SUBSYSTEM_ID, 2}, 244 }; 245 246 static int vfio_pci_igd_copy(VFIOPCIDevice *vdev, PCIDevice *pdev, 247 struct vfio_region_info *info, 248 const IGDHostInfo *list, int len) 249 { 250 int i, ret; 251 252 for (i = 0; i < len; i++) { 253 ret = pread(vdev->vbasedev.fd, pdev->config + list[i].offset, 254 list[i].len, info->offset + list[i].offset); 255 if (ret != list[i].len) { 256 error_report("IGD copy failed: %m"); 257 return -errno; 258 } 259 } 260 261 return 0; 262 } 263 264 /* 265 * Stuff a few values into the host bridge. 266 */ 267 static int vfio_pci_igd_host_init(VFIOPCIDevice *vdev, 268 struct vfio_region_info *info) 269 { 270 PCIBus *bus; 271 PCIDevice *host_bridge; 272 int ret; 273 274 bus = pci_device_root_bus(&vdev->pdev); 275 host_bridge = pci_find_device(bus, 0, PCI_DEVFN(0, 0)); 276 277 if (!host_bridge) { 278 error_report("Can't find host bridge"); 279 return -ENODEV; 280 } 281 282 ret = vfio_pci_igd_copy(vdev, host_bridge, info, igd_host_bridge_infos, 283 ARRAY_SIZE(igd_host_bridge_infos)); 284 if (!ret) { 285 trace_vfio_pci_igd_host_bridge_enabled(vdev->vbasedev.name); 286 } 287 288 return ret; 289 } 290 291 /* 292 * IGD LPC/ISA bridge support code. The vBIOS needs this, but we can't write 293 * arbitrary values into just any bridge, so we must create our own. We try 294 * to handle if the user has created it for us, which they might want to do 295 * to enable multifunction so we don't occupy the whole PCI slot. 296 */ 297 static void vfio_pci_igd_lpc_bridge_realize(PCIDevice *pdev, Error **errp) 298 { 299 if (pdev->devfn != PCI_DEVFN(0x1f, 0)) { 300 error_setg(errp, "VFIO dummy ISA/LPC bridge must have address 1f.0"); 301 } 302 } 303 304 static void vfio_pci_igd_lpc_bridge_class_init(ObjectClass *klass, void *data) 305 { 306 DeviceClass *dc = DEVICE_CLASS(klass); 307 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 308 309 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 310 dc->desc = "VFIO dummy ISA/LPC bridge for IGD assignment"; 311 dc->hotpluggable = false; 312 k->realize = vfio_pci_igd_lpc_bridge_realize; 313 k->class_id = PCI_CLASS_BRIDGE_ISA; 314 } 315 316 static const TypeInfo vfio_pci_igd_lpc_bridge_info = { 317 .name = "vfio-pci-igd-lpc-bridge", 318 .parent = TYPE_PCI_DEVICE, 319 .class_init = vfio_pci_igd_lpc_bridge_class_init, 320 .interfaces = (InterfaceInfo[]) { 321 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 322 { }, 323 }, 324 }; 325 326 static void vfio_pci_igd_register_types(void) 327 { 328 type_register_static(&vfio_pci_igd_lpc_bridge_info); 329 } 330 331 type_init(vfio_pci_igd_register_types) 332 333 static int vfio_pci_igd_lpc_init(VFIOPCIDevice *vdev, 334 struct vfio_region_info *info) 335 { 336 PCIDevice *lpc_bridge; 337 int ret; 338 339 lpc_bridge = pci_find_device(pci_device_root_bus(&vdev->pdev), 340 0, PCI_DEVFN(0x1f, 0)); 341 if (!lpc_bridge) { 342 lpc_bridge = pci_create_simple(pci_device_root_bus(&vdev->pdev), 343 PCI_DEVFN(0x1f, 0), "vfio-pci-igd-lpc-bridge"); 344 } 345 346 ret = vfio_pci_igd_copy(vdev, lpc_bridge, info, igd_lpc_bridge_infos, 347 ARRAY_SIZE(igd_lpc_bridge_infos)); 348 if (!ret) { 349 trace_vfio_pci_igd_lpc_bridge_enabled(vdev->vbasedev.name); 350 } 351 352 return ret; 353 } 354 355 static bool vfio_pci_igd_setup_lpc_bridge(VFIOPCIDevice *vdev, Error **errp) 356 { 357 g_autofree struct vfio_region_info *host = NULL; 358 g_autofree struct vfio_region_info *lpc = NULL; 359 PCIDevice *lpc_bridge; 360 int ret; 361 362 /* 363 * Copying IDs or creating new devices are not supported on hotplug 364 */ 365 if (vdev->pdev.qdev.hotplugged) { 366 error_setg(errp, "IGD LPC is not supported on hotplugged device"); 367 return false; 368 } 369 370 /* 371 * We need to create an LPC/ISA bridge at PCI bus address 00:1f.0 that we 372 * can stuff host values into, so if there's already one there and it's not 373 * one we can hack on, this quirk is no-go. Sorry Q35. 374 */ 375 lpc_bridge = pci_find_device(pci_device_root_bus(&vdev->pdev), 376 0, PCI_DEVFN(0x1f, 0)); 377 if (lpc_bridge && !object_dynamic_cast(OBJECT(lpc_bridge), 378 "vfio-pci-igd-lpc-bridge")) { 379 error_setg(errp, 380 "Cannot create LPC bridge due to existing device at 1f.0"); 381 return false; 382 } 383 384 /* 385 * Check whether we have all the vfio device specific regions to 386 * support LPC quirk (added in Linux v4.6). 387 */ 388 ret = vfio_get_dev_region_info(&vdev->vbasedev, 389 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL, 390 VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG, &lpc); 391 if (ret) { 392 error_setg(errp, "IGD LPC bridge access is not supported by kernel"); 393 return false; 394 } 395 396 ret = vfio_get_dev_region_info(&vdev->vbasedev, 397 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL, 398 VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG, &host); 399 if (ret) { 400 error_setg(errp, "IGD host bridge access is not supported by kernel"); 401 return false; 402 } 403 404 /* Create/modify LPC bridge */ 405 ret = vfio_pci_igd_lpc_init(vdev, lpc); 406 if (ret) { 407 error_setg(errp, "Failed to create/modify LPC bridge for IGD"); 408 return false; 409 } 410 411 /* Stuff some host values into the VM PCI host bridge */ 412 ret = vfio_pci_igd_host_init(vdev, host); 413 if (ret) { 414 error_setg(errp, "Failed to modify host bridge for IGD"); 415 return false; 416 } 417 418 return true; 419 } 420 421 #define IGD_GGC_MMIO_OFFSET 0x108040 422 #define IGD_BDSM_MMIO_OFFSET 0x1080C0 423 424 void vfio_probe_igd_bar0_quirk(VFIOPCIDevice *vdev, int nr) 425 { 426 VFIOQuirk *ggc_quirk, *bdsm_quirk; 427 VFIOConfigMirrorQuirk *ggc_mirror, *bdsm_mirror; 428 int gen; 429 430 /* 431 * This must be an Intel VGA device at address 00:02.0 for us to even 432 * consider enabling legacy mode. Some driver have dependencies on the PCI 433 * bus address. 434 */ 435 if (!vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, PCI_ANY_ID) || 436 !vfio_is_vga(vdev) || nr != 0) { 437 return; 438 } 439 440 /* 441 * Only on IGD devices of gen 11 and above, the BDSM register is mirrored 442 * into MMIO space and read from MMIO space by the Windows driver. 443 */ 444 gen = igd_gen(vdev); 445 if (gen < 6) { 446 return; 447 } 448 449 ggc_quirk = vfio_quirk_alloc(1); 450 ggc_mirror = ggc_quirk->data = g_malloc0(sizeof(*ggc_mirror)); 451 ggc_mirror->mem = ggc_quirk->mem; 452 ggc_mirror->vdev = vdev; 453 ggc_mirror->bar = nr; 454 ggc_mirror->offset = IGD_GGC_MMIO_OFFSET; 455 ggc_mirror->config_offset = IGD_GMCH; 456 457 memory_region_init_io(ggc_mirror->mem, OBJECT(vdev), 458 &vfio_generic_mirror_quirk, ggc_mirror, 459 "vfio-igd-ggc-quirk", 2); 460 memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, 461 ggc_mirror->offset, ggc_mirror->mem, 462 1); 463 464 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, ggc_quirk, next); 465 466 bdsm_quirk = vfio_quirk_alloc(1); 467 bdsm_mirror = bdsm_quirk->data = g_malloc0(sizeof(*bdsm_mirror)); 468 bdsm_mirror->mem = bdsm_quirk->mem; 469 bdsm_mirror->vdev = vdev; 470 bdsm_mirror->bar = nr; 471 bdsm_mirror->offset = IGD_BDSM_MMIO_OFFSET; 472 bdsm_mirror->config_offset = (gen < 11) ? IGD_BDSM : IGD_BDSM_GEN11; 473 474 memory_region_init_io(bdsm_mirror->mem, OBJECT(vdev), 475 &vfio_generic_mirror_quirk, bdsm_mirror, 476 "vfio-igd-bdsm-quirk", (gen < 11) ? 4 : 8); 477 memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, 478 bdsm_mirror->offset, bdsm_mirror->mem, 479 1); 480 481 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, bdsm_quirk, next); 482 } 483 484 static bool vfio_pci_igd_config_quirk(VFIOPCIDevice *vdev, Error **errp) 485 { 486 int ret, gen; 487 uint64_t gms_size; 488 uint64_t *bdsm_size; 489 uint32_t gmch; 490 bool legacy_mode_enabled = false; 491 Error *err = NULL; 492 493 /* 494 * This must be an Intel VGA device at address 00:02.0 for us to even 495 * consider enabling legacy mode. The vBIOS has dependencies on the 496 * PCI bus address. 497 */ 498 if (!vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, PCI_ANY_ID) || 499 !vfio_is_vga(vdev)) { 500 return true; 501 } 502 503 /* 504 * IGD is not a standard, they like to change their specs often. We 505 * only attempt to support back to SandBridge and we hope that newer 506 * devices maintain compatibility with generation 8. 507 */ 508 gen = igd_gen(vdev); 509 if (gen == -1) { 510 error_report("IGD device %s is unsupported in legacy mode, " 511 "try SandyBridge or newer", vdev->vbasedev.name); 512 return true; 513 } 514 515 gmch = vfio_pci_read_config(&vdev->pdev, IGD_GMCH, 4); 516 517 /* 518 * For backward compatibility, enable legacy mode when 519 * - Machine type is i440fx (pc_piix) 520 * - IGD device is at guest BDF 00:02.0 521 * - Not manually disabled by x-igd-legacy-mode=off 522 */ 523 if ((vdev->igd_legacy_mode != ON_OFF_AUTO_OFF) && 524 !strcmp(MACHINE_GET_CLASS(qdev_get_machine())->family, "pc_piix") && 525 (&vdev->pdev == pci_find_device(pci_device_root_bus(&vdev->pdev), 526 0, PCI_DEVFN(0x2, 0)))) { 527 /* 528 * IGD legacy mode requires: 529 * - VBIOS in ROM BAR or file 530 * - VGA IO/MMIO ranges are claimed by IGD 531 * - OpRegion 532 * - Same LPC bridge and Host bridge VID/DID/SVID/SSID as host 533 */ 534 g_autofree struct vfio_region_info *rom = NULL; 535 536 legacy_mode_enabled = true; 537 info_report("IGD legacy mode enabled, " 538 "use x-igd-legacy-mode=off to disable it if unwanted."); 539 540 /* 541 * Most of what we're doing here is to enable the ROM to run, so if 542 * there's no ROM, there's no point in setting up this quirk. 543 * NB. We only seem to get BIOS ROMs, so UEFI VM would need CSM support. 544 */ 545 ret = vfio_get_region_info(&vdev->vbasedev, 546 VFIO_PCI_ROM_REGION_INDEX, &rom); 547 if ((ret || !rom->size) && !vdev->pdev.romfile) { 548 error_setg(&err, "Device has no ROM"); 549 goto error; 550 } 551 552 /* 553 * If IGD VGA Disable is clear (expected) and VGA is not already 554 * enabled, try to enable it. Probably shouldn't be using legacy mode 555 * without VGA, but also no point in us enabling VGA if disabled in 556 * hardware. 557 */ 558 if (!(gmch & 0x2) && !vdev->vga && !vfio_populate_vga(vdev, &err)) { 559 error_setg(&err, "Unable to enable VGA access"); 560 goto error; 561 } 562 563 /* Enable OpRegion and LPC bridge quirk */ 564 vdev->features |= VFIO_FEATURE_ENABLE_IGD_OPREGION; 565 vdev->features |= VFIO_FEATURE_ENABLE_IGD_LPC; 566 } else if (vdev->igd_legacy_mode == ON_OFF_AUTO_ON) { 567 error_setg(&err, 568 "Machine is not i440fx or assigned BDF is not 00:02.0"); 569 goto error; 570 } 571 572 /* Setup OpRegion access */ 573 if ((vdev->features & VFIO_FEATURE_ENABLE_IGD_OPREGION) && 574 !vfio_pci_igd_setup_opregion(vdev, errp)) { 575 goto error; 576 } 577 578 /* Setup LPC bridge / Host bridge PCI IDs */ 579 if ((vdev->features & VFIO_FEATURE_ENABLE_IGD_LPC) && 580 !vfio_pci_igd_setup_lpc_bridge(vdev, errp)) { 581 goto error; 582 } 583 584 /* 585 * Allow user to override dsm size using x-igd-gms option, in multiples of 586 * 32MiB. This option should only be used when the desired size cannot be 587 * set from DVMT Pre-Allocated option in host BIOS. 588 */ 589 if (vdev->igd_gms) { 590 if (gen < 8) { 591 if (vdev->igd_gms <= 0x10) { 592 gmch &= ~(IGD_GMCH_GEN6_GMS_MASK << IGD_GMCH_GEN6_GMS_SHIFT); 593 gmch |= vdev->igd_gms << IGD_GMCH_GEN6_GMS_SHIFT; 594 } else { 595 error_report(QERR_INVALID_PARAMETER_VALUE, 596 "x-igd-gms", "0~0x10"); 597 } 598 } else { 599 if (vdev->igd_gms <= 0x40) { 600 gmch &= ~(IGD_GMCH_GEN8_GMS_MASK << IGD_GMCH_GEN8_GMS_SHIFT); 601 gmch |= vdev->igd_gms << IGD_GMCH_GEN8_GMS_SHIFT; 602 } else { 603 error_report(QERR_INVALID_PARAMETER_VALUE, 604 "x-igd-gms", "0~0x40"); 605 } 606 } 607 } 608 609 gms_size = igd_stolen_memory_size(gen, gmch); 610 611 /* 612 * Request reserved memory for stolen memory via fw_cfg. VM firmware 613 * must allocate a 1MB aligned reserved memory region below 4GB with 614 * the requested size (in bytes) for use by the Intel PCI class VGA 615 * device at VM address 00:02.0. The base address of this reserved 616 * memory region must be written to the device BDSM register at PCI 617 * config offset 0x5C. 618 */ 619 bdsm_size = g_malloc(sizeof(*bdsm_size)); 620 *bdsm_size = cpu_to_le64(gms_size); 621 fw_cfg_add_file(fw_cfg_find(), "etc/igd-bdsm-size", 622 bdsm_size, sizeof(*bdsm_size)); 623 624 /* GMCH is read-only, emulated */ 625 pci_set_long(vdev->pdev.config + IGD_GMCH, gmch); 626 pci_set_long(vdev->pdev.wmask + IGD_GMCH, 0); 627 pci_set_long(vdev->emulated_config_bits + IGD_GMCH, ~0); 628 629 /* BDSM is read-write, emulated. The BIOS needs to be able to write it */ 630 if (gen < 11) { 631 pci_set_long(vdev->pdev.config + IGD_BDSM, 0); 632 pci_set_long(vdev->pdev.wmask + IGD_BDSM, ~0); 633 pci_set_long(vdev->emulated_config_bits + IGD_BDSM, ~0); 634 } else { 635 pci_set_quad(vdev->pdev.config + IGD_BDSM_GEN11, 0); 636 pci_set_quad(vdev->pdev.wmask + IGD_BDSM_GEN11, ~0); 637 pci_set_quad(vdev->emulated_config_bits + IGD_BDSM_GEN11, ~0); 638 } 639 640 trace_vfio_pci_igd_bdsm_enabled(vdev->vbasedev.name, (gms_size / MiB)); 641 642 return true; 643 644 error: 645 /* 646 * When legacy mode is implicity enabled, continue on error, 647 * to keep compatibility 648 */ 649 if (legacy_mode_enabled && (vdev->igd_legacy_mode == ON_OFF_AUTO_AUTO)) { 650 error_report_err(err); 651 error_report("IGD legacy mode disabled"); 652 return true; 653 } 654 655 error_propagate(errp, err); 656 return false; 657 } 658 659 /* 660 * KVMGT/GVT-g vGPU exposes an emulated OpRegion. So far, users have to specify 661 * x-igd-opregion=on to enable the access. 662 * TODO: Check VID/DID and enable opregion access automatically 663 */ 664 static bool vfio_pci_kvmgt_config_quirk(VFIOPCIDevice *vdev, Error **errp) 665 { 666 if ((vdev->features & VFIO_FEATURE_ENABLE_IGD_OPREGION) && 667 !vfio_pci_igd_setup_opregion(vdev, errp)) { 668 return false; 669 } 670 671 return true; 672 } 673 674 bool vfio_probe_igd_config_quirk(VFIOPCIDevice *vdev, Error **errp) 675 { 676 /* KVMGT/GVT-g vGPU is exposed as mdev */ 677 if (vdev->vbasedev.mdev) { 678 return vfio_pci_kvmgt_config_quirk(vdev, errp); 679 } 680 681 return vfio_pci_igd_config_quirk(vdev, errp); 682 } 683