1 /* 2 * IGD device quirks 3 * 4 * Copyright Red Hat, Inc. 2016 5 * 6 * Authors: 7 * Alex Williamson <alex.williamson@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2. See 10 * the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qemu/units.h" 15 #include "qemu/error-report.h" 16 #include "qapi/error.h" 17 #include "qapi/qmp/qerror.h" 18 #include "hw/boards.h" 19 #include "hw/hw.h" 20 #include "hw/nvram/fw_cfg.h" 21 #include "pci.h" 22 #include "pci-quirks.h" 23 #include "trace.h" 24 25 /* 26 * Intel IGD support 27 * 28 * Obviously IGD is not a discrete device, this is evidenced not only by it 29 * being integrated into the CPU, but by the various chipset and BIOS 30 * dependencies that it brings along with it. Intel is trying to move away 31 * from this and Broadwell and newer devices can run in what Intel calls 32 * "Universal Pass-Through" mode, or UPT. Theoretically in UPT mode, nothing 33 * more is required beyond assigning the IGD device to a VM. There are 34 * however support limitations to this mode. It only supports IGD as a 35 * secondary graphics device in the VM and it doesn't officially support any 36 * physical outputs. 37 * 38 * The code here attempts to enable what we'll call legacy mode assignment, 39 * IGD retains most of the capabilities we expect for it to have on bare 40 * metal. To enable this mode, the IGD device must be assigned to the VM 41 * at PCI address 00:02.0, it must have a ROM, it very likely needs VGA 42 * support, we must have VM BIOS support for reserving and populating some 43 * of the required tables, and we need to tweak the chipset with revisions 44 * and IDs and an LPC/ISA bridge device. The intention is to make all of 45 * this happen automatically by installing the device at the correct VM PCI 46 * bus address. If any of the conditions are not met, we cross our fingers 47 * and hope the user knows better. 48 * 49 * NB - It is possible to enable physical outputs in UPT mode by supplying 50 * an OpRegion table. We don't do this by default because the guest driver 51 * behaves differently if an OpRegion is provided and no monitor is attached 52 * vs no OpRegion and a monitor being attached or not. Effectively, if a 53 * headless setup is desired, the OpRegion gets in the way of that. 54 */ 55 56 /* 57 * This presumes the device is already known to be an Intel VGA device, so we 58 * take liberties in which device ID bits match which generation. This should 59 * not be taken as an indication that all the devices are supported, or even 60 * supportable, some of them don't even support VT-d. 61 * See linux:include/drm/i915_pciids.h for IDs. 62 */ 63 static int igd_gen(VFIOPCIDevice *vdev) 64 { 65 /* 66 * Device IDs for Broxton/Apollo Lake are 0x0a84, 0x1a84, 0x1a85, 0x5a84 67 * and 0x5a85, match bit 11:1 here 68 * Prefix 0x0a is taken by Haswell, this rule should be matched first. 69 */ 70 if ((vdev->device_id & 0xffe) == 0xa84) { 71 return 9; 72 } 73 74 switch (vdev->device_id & 0xff00) { 75 case 0x0100: /* SandyBridge, IvyBridge */ 76 return 6; 77 case 0x0400: /* Haswell */ 78 case 0x0a00: /* Haswell */ 79 case 0x0c00: /* Haswell */ 80 case 0x0d00: /* Haswell */ 81 case 0x0f00: /* Valleyview/Bay Trail */ 82 return 7; 83 case 0x1600: /* Broadwell */ 84 case 0x2200: /* Cherryview */ 85 return 8; 86 case 0x1900: /* Skylake */ 87 case 0x3100: /* Gemini Lake */ 88 case 0x5900: /* Kaby Lake */ 89 case 0x3e00: /* Coffee Lake */ 90 case 0x9B00: /* Comet Lake */ 91 return 9; 92 case 0x8A00: /* Ice Lake */ 93 case 0x4500: /* Elkhart Lake */ 94 case 0x4E00: /* Jasper Lake */ 95 return 11; 96 case 0x9A00: /* Tiger Lake */ 97 case 0x4C00: /* Rocket Lake */ 98 case 0x4600: /* Alder Lake */ 99 case 0xA700: /* Raptor Lake */ 100 return 12; 101 } 102 103 /* 104 * Unfortunately, Intel changes it's specification quite often. This makes 105 * it impossible to use a suitable default value for unknown devices. 106 * Return -1 for not applying any generation-specific quirks. 107 */ 108 return -1; 109 } 110 111 #define IGD_ASLS 0xfc /* ASL Storage Register */ 112 #define IGD_GMCH 0x50 /* Graphics Control Register */ 113 #define IGD_BDSM 0x5c /* Base Data of Stolen Memory */ 114 #define IGD_BDSM_GEN11 0xc0 /* Base Data of Stolen Memory of gen 11 and later */ 115 116 #define IGD_GMCH_GEN6_GMS_SHIFT 3 /* SNB_GMCH in i915 */ 117 #define IGD_GMCH_GEN6_GMS_MASK 0x1f 118 #define IGD_GMCH_GEN8_GMS_SHIFT 8 /* BDW_GMCH in i915 */ 119 #define IGD_GMCH_GEN8_GMS_MASK 0xff 120 121 static uint64_t igd_stolen_memory_size(int gen, uint32_t gmch) 122 { 123 uint64_t gms; 124 125 if (gen < 8) { 126 gms = (gmch >> IGD_GMCH_GEN6_GMS_SHIFT) & IGD_GMCH_GEN6_GMS_MASK; 127 } else { 128 gms = (gmch >> IGD_GMCH_GEN8_GMS_SHIFT) & IGD_GMCH_GEN8_GMS_MASK; 129 } 130 131 if (gen < 9) { 132 return gms * 32 * MiB; 133 } else { 134 if (gms < 0xf0) { 135 return gms * 32 * MiB; 136 } else { 137 return (gms - 0xf0 + 1) * 4 * MiB; 138 } 139 } 140 141 return 0; 142 } 143 144 /* 145 * The OpRegion includes the Video BIOS Table, which seems important for 146 * telling the driver what sort of outputs it has. Without this, the device 147 * may work in the guest, but we may not get output. This also requires BIOS 148 * support to reserve and populate a section of guest memory sufficient for 149 * the table and to write the base address of that memory to the ASLS register 150 * of the IGD device. 151 */ 152 static bool vfio_pci_igd_opregion_init(VFIOPCIDevice *vdev, 153 struct vfio_region_info *info, 154 Error **errp) 155 { 156 int ret; 157 158 vdev->igd_opregion = g_malloc0(info->size); 159 ret = pread(vdev->vbasedev.fd, vdev->igd_opregion, 160 info->size, info->offset); 161 if (ret != info->size) { 162 error_setg(errp, "failed to read IGD OpRegion"); 163 g_free(vdev->igd_opregion); 164 vdev->igd_opregion = NULL; 165 return false; 166 } 167 168 /* 169 * Provide fw_cfg with a copy of the OpRegion which the VM firmware is to 170 * allocate 32bit reserved memory for, copy these contents into, and write 171 * the reserved memory base address to the device ASLS register at 0xFC. 172 * Alignment of this reserved region seems flexible, but using a 4k page 173 * alignment seems to work well. This interface assumes a single IGD 174 * device, which may be at VM address 00:02.0 in legacy mode or another 175 * address in UPT mode. 176 * 177 * NB, there may be future use cases discovered where the VM should have 178 * direct interaction with the host OpRegion, in which case the write to 179 * the ASLS register would trigger MemoryRegion setup to enable that. 180 */ 181 fw_cfg_add_file(fw_cfg_find(), "etc/igd-opregion", 182 vdev->igd_opregion, info->size); 183 184 trace_vfio_pci_igd_opregion_enabled(vdev->vbasedev.name); 185 186 return true; 187 } 188 189 static bool vfio_pci_igd_opregion_detect(VFIOPCIDevice *vdev, 190 struct vfio_region_info **opregion, 191 Error **errp) 192 { 193 int ret; 194 195 /* Hotplugging is not supported for opregion access */ 196 if (vdev->pdev.qdev.hotplugged) { 197 error_setg(errp, "IGD OpRegion is not supported on hotplugged device"); 198 return false; 199 } 200 201 ret = vfio_device_get_region_info_type(&vdev->vbasedev, 202 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL, 203 VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION, opregion); 204 if (ret) { 205 error_setg_errno(errp, -ret, 206 "Device does not supports IGD OpRegion feature"); 207 return false; 208 } 209 210 return true; 211 } 212 213 /* 214 * The rather short list of registers that we copy from the host devices. 215 * The LPC/ISA bridge values are definitely needed to support the vBIOS, the 216 * host bridge values may or may not be needed depending on the guest OS. 217 * Since we're only munging revision and subsystem values on the host bridge, 218 * we don't require our own device. The LPC/ISA bridge needs to be our very 219 * own though. 220 */ 221 typedef struct { 222 uint8_t offset; 223 uint8_t len; 224 } IGDHostInfo; 225 226 static const IGDHostInfo igd_host_bridge_infos[] = { 227 {PCI_REVISION_ID, 2}, 228 {PCI_SUBSYSTEM_VENDOR_ID, 2}, 229 {PCI_SUBSYSTEM_ID, 2}, 230 }; 231 232 static const IGDHostInfo igd_lpc_bridge_infos[] = { 233 {PCI_VENDOR_ID, 2}, 234 {PCI_DEVICE_ID, 2}, 235 {PCI_REVISION_ID, 2}, 236 {PCI_SUBSYSTEM_VENDOR_ID, 2}, 237 {PCI_SUBSYSTEM_ID, 2}, 238 }; 239 240 static int vfio_pci_igd_copy(VFIOPCIDevice *vdev, PCIDevice *pdev, 241 struct vfio_region_info *info, 242 const IGDHostInfo *list, int len) 243 { 244 int i, ret; 245 246 for (i = 0; i < len; i++) { 247 ret = pread(vdev->vbasedev.fd, pdev->config + list[i].offset, 248 list[i].len, info->offset + list[i].offset); 249 if (ret != list[i].len) { 250 error_report("IGD copy failed: %m"); 251 return -errno; 252 } 253 } 254 255 return 0; 256 } 257 258 /* 259 * Stuff a few values into the host bridge. 260 */ 261 static int vfio_pci_igd_host_init(VFIOPCIDevice *vdev, 262 struct vfio_region_info *info) 263 { 264 PCIBus *bus; 265 PCIDevice *host_bridge; 266 int ret; 267 268 bus = pci_device_root_bus(&vdev->pdev); 269 host_bridge = pci_find_device(bus, 0, PCI_DEVFN(0, 0)); 270 271 if (!host_bridge) { 272 error_report("Can't find host bridge"); 273 return -ENODEV; 274 } 275 276 ret = vfio_pci_igd_copy(vdev, host_bridge, info, igd_host_bridge_infos, 277 ARRAY_SIZE(igd_host_bridge_infos)); 278 if (!ret) { 279 trace_vfio_pci_igd_host_bridge_enabled(vdev->vbasedev.name); 280 } 281 282 return ret; 283 } 284 285 /* 286 * IGD LPC/ISA bridge support code. The vBIOS needs this, but we can't write 287 * arbitrary values into just any bridge, so we must create our own. We try 288 * to handle if the user has created it for us, which they might want to do 289 * to enable multifunction so we don't occupy the whole PCI slot. 290 */ 291 static void vfio_pci_igd_lpc_bridge_realize(PCIDevice *pdev, Error **errp) 292 { 293 if (pdev->devfn != PCI_DEVFN(0x1f, 0)) { 294 error_setg(errp, "VFIO dummy ISA/LPC bridge must have address 1f.0"); 295 } 296 } 297 298 static void vfio_pci_igd_lpc_bridge_class_init(ObjectClass *klass, 299 const void *data) 300 { 301 DeviceClass *dc = DEVICE_CLASS(klass); 302 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 303 304 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 305 dc->desc = "VFIO dummy ISA/LPC bridge for IGD assignment"; 306 dc->hotpluggable = false; 307 k->realize = vfio_pci_igd_lpc_bridge_realize; 308 k->class_id = PCI_CLASS_BRIDGE_ISA; 309 } 310 311 static const TypeInfo vfio_pci_igd_lpc_bridge_info = { 312 .name = "vfio-pci-igd-lpc-bridge", 313 .parent = TYPE_PCI_DEVICE, 314 .class_init = vfio_pci_igd_lpc_bridge_class_init, 315 .interfaces = (const InterfaceInfo[]) { 316 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 317 { }, 318 }, 319 }; 320 321 static void vfio_pci_igd_register_types(void) 322 { 323 type_register_static(&vfio_pci_igd_lpc_bridge_info); 324 } 325 326 type_init(vfio_pci_igd_register_types) 327 328 static int vfio_pci_igd_lpc_init(VFIOPCIDevice *vdev, 329 struct vfio_region_info *info) 330 { 331 PCIDevice *lpc_bridge; 332 int ret; 333 334 lpc_bridge = pci_find_device(pci_device_root_bus(&vdev->pdev), 335 0, PCI_DEVFN(0x1f, 0)); 336 if (!lpc_bridge) { 337 lpc_bridge = pci_create_simple(pci_device_root_bus(&vdev->pdev), 338 PCI_DEVFN(0x1f, 0), "vfio-pci-igd-lpc-bridge"); 339 } 340 341 ret = vfio_pci_igd_copy(vdev, lpc_bridge, info, igd_lpc_bridge_infos, 342 ARRAY_SIZE(igd_lpc_bridge_infos)); 343 if (!ret) { 344 trace_vfio_pci_igd_lpc_bridge_enabled(vdev->vbasedev.name); 345 } 346 347 return ret; 348 } 349 350 static bool vfio_pci_igd_setup_lpc_bridge(VFIOPCIDevice *vdev, Error **errp) 351 { 352 struct vfio_region_info *host = NULL; 353 struct vfio_region_info *lpc = NULL; 354 PCIDevice *lpc_bridge; 355 int ret; 356 357 /* 358 * Copying IDs or creating new devices are not supported on hotplug 359 */ 360 if (vdev->pdev.qdev.hotplugged) { 361 error_setg(errp, "IGD LPC is not supported on hotplugged device"); 362 return false; 363 } 364 365 /* 366 * We need to create an LPC/ISA bridge at PCI bus address 00:1f.0 that we 367 * can stuff host values into, so if there's already one there and it's not 368 * one we can hack on, this quirk is no-go. Sorry Q35. 369 */ 370 lpc_bridge = pci_find_device(pci_device_root_bus(&vdev->pdev), 371 0, PCI_DEVFN(0x1f, 0)); 372 if (lpc_bridge && !object_dynamic_cast(OBJECT(lpc_bridge), 373 "vfio-pci-igd-lpc-bridge")) { 374 error_setg(errp, 375 "Cannot create LPC bridge due to existing device at 1f.0"); 376 return false; 377 } 378 379 /* 380 * Check whether we have all the vfio device specific regions to 381 * support LPC quirk (added in Linux v4.6). 382 */ 383 ret = vfio_device_get_region_info_type(&vdev->vbasedev, 384 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL, 385 VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG, &lpc); 386 if (ret) { 387 error_setg(errp, "IGD LPC bridge access is not supported by kernel"); 388 return false; 389 } 390 391 ret = vfio_device_get_region_info_type(&vdev->vbasedev, 392 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL, 393 VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG, &host); 394 if (ret) { 395 error_setg(errp, "IGD host bridge access is not supported by kernel"); 396 return false; 397 } 398 399 /* Create/modify LPC bridge */ 400 ret = vfio_pci_igd_lpc_init(vdev, lpc); 401 if (ret) { 402 error_setg(errp, "Failed to create/modify LPC bridge for IGD"); 403 return false; 404 } 405 406 /* Stuff some host values into the VM PCI host bridge */ 407 ret = vfio_pci_igd_host_init(vdev, host); 408 if (ret) { 409 error_setg(errp, "Failed to modify host bridge for IGD"); 410 return false; 411 } 412 413 return true; 414 } 415 416 static bool vfio_pci_igd_override_gms(int gen, uint32_t gms, uint32_t *gmch) 417 { 418 bool ret = false; 419 420 if (gen == -1) { 421 error_report("x-igd-gms is not supported on this device"); 422 } else if (gen < 8) { 423 if (gms <= 0x10) { 424 *gmch &= ~(IGD_GMCH_GEN6_GMS_MASK << IGD_GMCH_GEN6_GMS_SHIFT); 425 *gmch |= gms << IGD_GMCH_GEN6_GMS_SHIFT; 426 ret = true; 427 } else { 428 error_report(QERR_INVALID_PARAMETER_VALUE, "x-igd-gms", "0~0x10"); 429 } 430 } else if (gen == 8) { 431 if (gms <= 0x40) { 432 *gmch &= ~(IGD_GMCH_GEN8_GMS_MASK << IGD_GMCH_GEN8_GMS_SHIFT); 433 *gmch |= gms << IGD_GMCH_GEN8_GMS_SHIFT; 434 ret = true; 435 } else { 436 error_report(QERR_INVALID_PARAMETER_VALUE, "x-igd-gms", "0~0x40"); 437 } 438 } else { 439 /* 0x0 to 0x40: 32MB increments starting at 0MB */ 440 /* 0xf0 to 0xfe: 4MB increments starting at 4MB */ 441 if ((gms <= 0x40) || (gms >= 0xf0 && gms <= 0xfe)) { 442 *gmch &= ~(IGD_GMCH_GEN8_GMS_MASK << IGD_GMCH_GEN8_GMS_SHIFT); 443 *gmch |= gms << IGD_GMCH_GEN8_GMS_SHIFT; 444 ret = true; 445 } else { 446 error_report(QERR_INVALID_PARAMETER_VALUE, 447 "x-igd-gms", "0~0x40 or 0xf0~0xfe"); 448 } 449 } 450 451 return ret; 452 } 453 454 #define IGD_GGC_MMIO_OFFSET 0x108040 455 #define IGD_BDSM_MMIO_OFFSET 0x1080C0 456 457 void vfio_probe_igd_bar0_quirk(VFIOPCIDevice *vdev, int nr) 458 { 459 VFIOQuirk *ggc_quirk, *bdsm_quirk; 460 VFIOConfigMirrorQuirk *ggc_mirror, *bdsm_mirror; 461 int gen; 462 463 if (!vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, PCI_ANY_ID) || 464 !vfio_is_vga(vdev) || nr != 0) { 465 return; 466 } 467 468 /* Only on IGD Gen6-12 device needs quirks in BAR 0 */ 469 gen = igd_gen(vdev); 470 if (gen < 6) { 471 return; 472 } 473 474 if (vdev->igd_gms) { 475 ggc_quirk = vfio_quirk_alloc(1); 476 ggc_mirror = ggc_quirk->data = g_malloc0(sizeof(*ggc_mirror)); 477 ggc_mirror->mem = ggc_quirk->mem; 478 ggc_mirror->vdev = vdev; 479 ggc_mirror->bar = nr; 480 ggc_mirror->offset = IGD_GGC_MMIO_OFFSET; 481 ggc_mirror->config_offset = IGD_GMCH; 482 483 memory_region_init_io(ggc_mirror->mem, OBJECT(vdev), 484 &vfio_generic_mirror_quirk, ggc_mirror, 485 "vfio-igd-ggc-quirk", 2); 486 memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, 487 ggc_mirror->offset, ggc_mirror->mem, 488 1); 489 490 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, ggc_quirk, next); 491 } 492 493 bdsm_quirk = vfio_quirk_alloc(1); 494 bdsm_mirror = bdsm_quirk->data = g_malloc0(sizeof(*bdsm_mirror)); 495 bdsm_mirror->mem = bdsm_quirk->mem; 496 bdsm_mirror->vdev = vdev; 497 bdsm_mirror->bar = nr; 498 bdsm_mirror->offset = IGD_BDSM_MMIO_OFFSET; 499 bdsm_mirror->config_offset = (gen < 11) ? IGD_BDSM : IGD_BDSM_GEN11; 500 501 memory_region_init_io(bdsm_mirror->mem, OBJECT(vdev), 502 &vfio_generic_mirror_quirk, bdsm_mirror, 503 "vfio-igd-bdsm-quirk", (gen < 11) ? 4 : 8); 504 memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, 505 bdsm_mirror->offset, bdsm_mirror->mem, 506 1); 507 508 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, bdsm_quirk, next); 509 } 510 511 static bool vfio_pci_igd_config_quirk(VFIOPCIDevice *vdev, Error **errp) 512 { 513 struct vfio_region_info *opregion = NULL; 514 int ret, gen; 515 uint64_t gms_size = 0; 516 uint64_t *bdsm_size; 517 uint32_t gmch; 518 bool legacy_mode_enabled = false; 519 Error *err = NULL; 520 521 if (!vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, PCI_ANY_ID) || 522 !vfio_is_vga(vdev)) { 523 return true; 524 } 525 526 /* IGD device always comes with OpRegion */ 527 if (!vfio_pci_igd_opregion_detect(vdev, &opregion, errp)) { 528 return true; 529 } 530 info_report("OpRegion detected on Intel display %x.", vdev->device_id); 531 532 gen = igd_gen(vdev); 533 gmch = vfio_pci_read_config(&vdev->pdev, IGD_GMCH, 4); 534 535 /* 536 * For backward compatibility, enable legacy mode when 537 * - Device geneation is 6 to 9 (including both) 538 * - Machine type is i440fx (pc_piix) 539 * - IGD device is at guest BDF 00:02.0 540 * - Not manually disabled by x-igd-legacy-mode=off 541 */ 542 if ((vdev->igd_legacy_mode != ON_OFF_AUTO_OFF) && 543 (gen >= 6 && gen <= 9) && 544 !strcmp(MACHINE_GET_CLASS(qdev_get_machine())->family, "pc_piix") && 545 (&vdev->pdev == pci_find_device(pci_device_root_bus(&vdev->pdev), 546 0, PCI_DEVFN(0x2, 0)))) { 547 /* 548 * IGD legacy mode requires: 549 * - VBIOS in ROM BAR or file 550 * - VGA IO/MMIO ranges are claimed by IGD 551 * - OpRegion 552 * - Same LPC bridge and Host bridge VID/DID/SVID/SSID as host 553 */ 554 struct vfio_region_info *rom = NULL; 555 556 legacy_mode_enabled = true; 557 info_report("IGD legacy mode enabled, " 558 "use x-igd-legacy-mode=off to disable it if unwanted."); 559 560 /* 561 * Most of what we're doing here is to enable the ROM to run, so if 562 * there's no ROM, there's no point in setting up this quirk. 563 * NB. We only seem to get BIOS ROMs, so UEFI VM would need CSM support. 564 */ 565 ret = vfio_device_get_region_info(&vdev->vbasedev, 566 VFIO_PCI_ROM_REGION_INDEX, &rom); 567 if ((ret || !rom->size) && !vdev->pdev.romfile) { 568 error_setg(&err, "Device has no ROM"); 569 goto error; 570 } 571 572 /* 573 * If IGD VGA Disable is clear (expected) and VGA is not already 574 * enabled, try to enable it. Probably shouldn't be using legacy mode 575 * without VGA, but also no point in us enabling VGA if disabled in 576 * hardware. 577 */ 578 if (!(gmch & 0x2) && !vdev->vga && !vfio_populate_vga(vdev, &err)) { 579 error_setg(&err, "Unable to enable VGA access"); 580 goto error; 581 } 582 583 /* Enable OpRegion and LPC bridge quirk */ 584 vdev->features |= VFIO_FEATURE_ENABLE_IGD_OPREGION; 585 vdev->features |= VFIO_FEATURE_ENABLE_IGD_LPC; 586 } else if (vdev->igd_legacy_mode == ON_OFF_AUTO_ON) { 587 error_setg(&err, 588 "Machine is not i440fx, assigned BDF is not 00:02.0, " 589 "or device %04x (gen %d) doesn't support legacy mode", 590 vdev->device_id, gen); 591 goto error; 592 } 593 594 /* Setup OpRegion access */ 595 if ((vdev->features & VFIO_FEATURE_ENABLE_IGD_OPREGION) && 596 !vfio_pci_igd_opregion_init(vdev, opregion, errp)) { 597 goto error; 598 } 599 600 /* Setup LPC bridge / Host bridge PCI IDs */ 601 if ((vdev->features & VFIO_FEATURE_ENABLE_IGD_LPC) && 602 !vfio_pci_igd_setup_lpc_bridge(vdev, errp)) { 603 goto error; 604 } 605 606 /* 607 * ASLS (OpRegion address) is read-only, emulated 608 * It contains HPA, guest firmware need to reprogram it with GPA. 609 */ 610 pci_set_long(vdev->pdev.config + IGD_ASLS, 0); 611 pci_set_long(vdev->pdev.wmask + IGD_ASLS, ~0); 612 pci_set_long(vdev->emulated_config_bits + IGD_ASLS, ~0); 613 614 /* 615 * Allow user to override dsm size using x-igd-gms option, in multiples of 616 * 32MiB. This option should only be used when the desired size cannot be 617 * set from DVMT Pre-Allocated option in host BIOS. 618 */ 619 if (vdev->igd_gms) { 620 if (!vfio_pci_igd_override_gms(gen, vdev->igd_gms, &gmch)) { 621 return false; 622 } 623 624 /* GMCH is read-only, emulated */ 625 pci_set_long(vdev->pdev.config + IGD_GMCH, gmch); 626 pci_set_long(vdev->pdev.wmask + IGD_GMCH, 0); 627 pci_set_long(vdev->emulated_config_bits + IGD_GMCH, ~0); 628 } 629 630 if (gen > 0) { 631 gms_size = igd_stolen_memory_size(gen, gmch); 632 633 /* BDSM is read-write, emulated. BIOS needs to be able to write it */ 634 if (gen < 11) { 635 pci_set_long(vdev->pdev.config + IGD_BDSM, 0); 636 pci_set_long(vdev->pdev.wmask + IGD_BDSM, ~0); 637 pci_set_long(vdev->emulated_config_bits + IGD_BDSM, ~0); 638 } else { 639 pci_set_quad(vdev->pdev.config + IGD_BDSM_GEN11, 0); 640 pci_set_quad(vdev->pdev.wmask + IGD_BDSM_GEN11, ~0); 641 pci_set_quad(vdev->emulated_config_bits + IGD_BDSM_GEN11, ~0); 642 } 643 } 644 645 /* 646 * Request reserved memory for stolen memory via fw_cfg. VM firmware 647 * must allocate a 1MB aligned reserved memory region below 4GB with 648 * the requested size (in bytes) for use by the IGD device. The base 649 * address of this reserved memory region must be written to the 650 * device BDSM register. 651 * For newer device without BDSM register, this fw_cfg item is 0. 652 */ 653 bdsm_size = g_malloc(sizeof(*bdsm_size)); 654 *bdsm_size = cpu_to_le64(gms_size); 655 fw_cfg_add_file(fw_cfg_find(), "etc/igd-bdsm-size", 656 bdsm_size, sizeof(*bdsm_size)); 657 658 trace_vfio_pci_igd_bdsm_enabled(vdev->vbasedev.name, (gms_size / MiB)); 659 660 return true; 661 662 error: 663 /* 664 * When legacy mode is implicity enabled, continue on error, 665 * to keep compatibility 666 */ 667 if (legacy_mode_enabled && (vdev->igd_legacy_mode == ON_OFF_AUTO_AUTO)) { 668 error_report_err(err); 669 error_report("IGD legacy mode disabled"); 670 return true; 671 } 672 673 error_propagate(errp, err); 674 return false; 675 } 676 677 /* 678 * KVMGT/GVT-g vGPU exposes an emulated OpRegion. So far, users have to specify 679 * x-igd-opregion=on to enable the access. 680 * TODO: Check VID/DID and enable opregion access automatically 681 */ 682 static bool vfio_pci_kvmgt_config_quirk(VFIOPCIDevice *vdev, Error **errp) 683 { 684 struct vfio_region_info *opregion = NULL; 685 int gen; 686 687 if (!vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, PCI_ANY_ID) || 688 !vfio_is_vga(vdev)) { 689 return true; 690 } 691 692 /* FIXME: Cherryview is Gen8, but don't support GVT-g */ 693 gen = igd_gen(vdev); 694 if (gen != 8 && gen != 9) { 695 return true; 696 } 697 698 if (!vfio_pci_igd_opregion_detect(vdev, &opregion, errp)) { 699 /* Should never reach here, KVMGT always emulates OpRegion */ 700 return false; 701 } 702 703 if ((vdev->features & VFIO_FEATURE_ENABLE_IGD_OPREGION) && 704 !vfio_pci_igd_opregion_init(vdev, opregion, errp)) { 705 return false; 706 } 707 708 return true; 709 } 710 711 bool vfio_probe_igd_config_quirk(VFIOPCIDevice *vdev, Error **errp) 712 { 713 /* KVMGT/GVT-g vGPU is exposed as mdev */ 714 if (vdev->vbasedev.mdev) { 715 return vfio_pci_kvmgt_config_quirk(vdev, errp); 716 } 717 718 return vfio_pci_igd_config_quirk(vdev, errp); 719 } 720