1 /* 2 * IGD device quirks 3 * 4 * Copyright Red Hat, Inc. 2016 5 * 6 * Authors: 7 * Alex Williamson <alex.williamson@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2. See 10 * the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qemu/units.h" 15 #include "qemu/error-report.h" 16 #include "qapi/error.h" 17 #include "qapi/qmp/qerror.h" 18 #include "hw/boards.h" 19 #include "hw/hw.h" 20 #include "hw/nvram/fw_cfg.h" 21 #include "pci.h" 22 #include "pci-quirks.h" 23 #include "trace.h" 24 25 /* 26 * Intel IGD support 27 * 28 * Obviously IGD is not a discrete device, this is evidenced not only by it 29 * being integrated into the CPU, but by the various chipset and BIOS 30 * dependencies that it brings along with it. Intel is trying to move away 31 * from this and Broadwell and newer devices can run in what Intel calls 32 * "Universal Pass-Through" mode, or UPT. Theoretically in UPT mode, nothing 33 * more is required beyond assigning the IGD device to a VM. There are 34 * however support limitations to this mode. It only supports IGD as a 35 * secondary graphics device in the VM and it doesn't officially support any 36 * physical outputs. 37 * 38 * The code here attempts to enable what we'll call legacy mode assignment, 39 * IGD retains most of the capabilities we expect for it to have on bare 40 * metal. To enable this mode, the IGD device must be assigned to the VM 41 * at PCI address 00:02.0, it must have a ROM, it very likely needs VGA 42 * support, we must have VM BIOS support for reserving and populating some 43 * of the required tables, and we need to tweak the chipset with revisions 44 * and IDs and an LPC/ISA bridge device. The intention is to make all of 45 * this happen automatically by installing the device at the correct VM PCI 46 * bus address. If any of the conditions are not met, we cross our fingers 47 * and hope the user knows better. 48 * 49 * NB - It is possible to enable physical outputs in UPT mode by supplying 50 * an OpRegion table. We don't do this by default because the guest driver 51 * behaves differently if an OpRegion is provided and no monitor is attached 52 * vs no OpRegion and a monitor being attached or not. Effectively, if a 53 * headless setup is desired, the OpRegion gets in the way of that. 54 */ 55 56 /* 57 * This presumes the device is already known to be an Intel VGA device, so we 58 * take liberties in which device ID bits match which generation. This should 59 * not be taken as an indication that all the devices are supported, or even 60 * supportable, some of them don't even support VT-d. 61 * See linux:include/drm/i915_pciids.h for IDs. 62 */ 63 static int igd_gen(VFIOPCIDevice *vdev) 64 { 65 /* 66 * Device IDs for Broxton/Apollo Lake are 0x0a84, 0x1a84, 0x1a85, 0x5a84 67 * and 0x5a85, match bit 11:1 here 68 * Prefix 0x0a is taken by Haswell, this rule should be matched first. 69 */ 70 if ((vdev->device_id & 0xffe) == 0xa84) { 71 return 9; 72 } 73 74 switch (vdev->device_id & 0xff00) { 75 case 0x0100: /* SandyBridge, IvyBridge */ 76 return 6; 77 case 0x0400: /* Haswell */ 78 case 0x0a00: /* Haswell */ 79 case 0x0c00: /* Haswell */ 80 case 0x0d00: /* Haswell */ 81 case 0x0f00: /* Valleyview/Bay Trail */ 82 return 7; 83 case 0x1600: /* Broadwell */ 84 case 0x2200: /* Cherryview */ 85 return 8; 86 case 0x1900: /* Skylake */ 87 case 0x3100: /* Gemini Lake */ 88 case 0x5900: /* Kaby Lake */ 89 case 0x3e00: /* Coffee Lake */ 90 case 0x9B00: /* Comet Lake */ 91 return 9; 92 case 0x8A00: /* Ice Lake */ 93 case 0x4500: /* Elkhart Lake */ 94 case 0x4E00: /* Jasper Lake */ 95 return 11; 96 case 0x9A00: /* Tiger Lake */ 97 case 0x4C00: /* Rocket Lake */ 98 case 0x4600: /* Alder Lake */ 99 case 0xA700: /* Raptor Lake */ 100 return 12; 101 } 102 103 /* 104 * Unfortunately, Intel changes it's specification quite often. This makes 105 * it impossible to use a suitable default value for unknown devices. 106 */ 107 return -1; 108 } 109 110 #define IGD_ASLS 0xfc /* ASL Storage Register */ 111 #define IGD_GMCH 0x50 /* Graphics Control Register */ 112 #define IGD_BDSM 0x5c /* Base Data of Stolen Memory */ 113 #define IGD_BDSM_GEN11 0xc0 /* Base Data of Stolen Memory of gen 11 and later */ 114 115 #define IGD_GMCH_GEN6_GMS_SHIFT 3 /* SNB_GMCH in i915 */ 116 #define IGD_GMCH_GEN6_GMS_MASK 0x1f 117 #define IGD_GMCH_GEN8_GMS_SHIFT 8 /* BDW_GMCH in i915 */ 118 #define IGD_GMCH_GEN8_GMS_MASK 0xff 119 120 static uint64_t igd_stolen_memory_size(int gen, uint32_t gmch) 121 { 122 uint64_t gms; 123 124 if (gen < 8) { 125 gms = (gmch >> IGD_GMCH_GEN6_GMS_SHIFT) & IGD_GMCH_GEN6_GMS_MASK; 126 } else { 127 gms = (gmch >> IGD_GMCH_GEN8_GMS_SHIFT) & IGD_GMCH_GEN8_GMS_MASK; 128 } 129 130 if (gen < 9) { 131 return gms * 32 * MiB; 132 } else { 133 if (gms < 0xf0) { 134 return gms * 32 * MiB; 135 } else { 136 return (gms - 0xf0 + 1) * 4 * MiB; 137 } 138 } 139 140 return 0; 141 } 142 143 /* 144 * The OpRegion includes the Video BIOS Table, which seems important for 145 * telling the driver what sort of outputs it has. Without this, the device 146 * may work in the guest, but we may not get output. This also requires BIOS 147 * support to reserve and populate a section of guest memory sufficient for 148 * the table and to write the base address of that memory to the ASLS register 149 * of the IGD device. 150 */ 151 static bool vfio_pci_igd_opregion_init(VFIOPCIDevice *vdev, 152 struct vfio_region_info *info, 153 Error **errp) 154 { 155 int ret; 156 157 vdev->igd_opregion = g_malloc0(info->size); 158 ret = pread(vdev->vbasedev.fd, vdev->igd_opregion, 159 info->size, info->offset); 160 if (ret != info->size) { 161 error_setg(errp, "failed to read IGD OpRegion"); 162 g_free(vdev->igd_opregion); 163 vdev->igd_opregion = NULL; 164 return false; 165 } 166 167 /* 168 * Provide fw_cfg with a copy of the OpRegion which the VM firmware is to 169 * allocate 32bit reserved memory for, copy these contents into, and write 170 * the reserved memory base address to the device ASLS register at 0xFC. 171 * Alignment of this reserved region seems flexible, but using a 4k page 172 * alignment seems to work well. This interface assumes a single IGD 173 * device, which may be at VM address 00:02.0 in legacy mode or another 174 * address in UPT mode. 175 * 176 * NB, there may be future use cases discovered where the VM should have 177 * direct interaction with the host OpRegion, in which case the write to 178 * the ASLS register would trigger MemoryRegion setup to enable that. 179 */ 180 fw_cfg_add_file(fw_cfg_find(), "etc/igd-opregion", 181 vdev->igd_opregion, info->size); 182 183 trace_vfio_pci_igd_opregion_enabled(vdev->vbasedev.name); 184 185 return true; 186 } 187 188 static bool vfio_pci_igd_opregion_detect(VFIOPCIDevice *vdev, 189 struct vfio_region_info **opregion, 190 Error **errp) 191 { 192 int ret; 193 194 /* Hotplugging is not supported for opregion access */ 195 if (vdev->pdev.qdev.hotplugged) { 196 error_setg(errp, "IGD OpRegion is not supported on hotplugged device"); 197 return false; 198 } 199 200 ret = vfio_device_get_region_info_type(&vdev->vbasedev, 201 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL, 202 VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION, opregion); 203 if (ret) { 204 error_setg_errno(errp, -ret, 205 "Device does not supports IGD OpRegion feature"); 206 return false; 207 } 208 209 return true; 210 } 211 212 /* 213 * The rather short list of registers that we copy from the host devices. 214 * The LPC/ISA bridge values are definitely needed to support the vBIOS, the 215 * host bridge values may or may not be needed depending on the guest OS. 216 * Since we're only munging revision and subsystem values on the host bridge, 217 * we don't require our own device. The LPC/ISA bridge needs to be our very 218 * own though. 219 */ 220 typedef struct { 221 uint8_t offset; 222 uint8_t len; 223 } IGDHostInfo; 224 225 static const IGDHostInfo igd_host_bridge_infos[] = { 226 {PCI_REVISION_ID, 2}, 227 {PCI_SUBSYSTEM_VENDOR_ID, 2}, 228 {PCI_SUBSYSTEM_ID, 2}, 229 }; 230 231 static const IGDHostInfo igd_lpc_bridge_infos[] = { 232 {PCI_VENDOR_ID, 2}, 233 {PCI_DEVICE_ID, 2}, 234 {PCI_REVISION_ID, 2}, 235 {PCI_SUBSYSTEM_VENDOR_ID, 2}, 236 {PCI_SUBSYSTEM_ID, 2}, 237 }; 238 239 static int vfio_pci_igd_copy(VFIOPCIDevice *vdev, PCIDevice *pdev, 240 struct vfio_region_info *info, 241 const IGDHostInfo *list, int len) 242 { 243 int i, ret; 244 245 for (i = 0; i < len; i++) { 246 ret = pread(vdev->vbasedev.fd, pdev->config + list[i].offset, 247 list[i].len, info->offset + list[i].offset); 248 if (ret != list[i].len) { 249 error_report("IGD copy failed: %m"); 250 return -errno; 251 } 252 } 253 254 return 0; 255 } 256 257 /* 258 * Stuff a few values into the host bridge. 259 */ 260 static int vfio_pci_igd_host_init(VFIOPCIDevice *vdev, 261 struct vfio_region_info *info) 262 { 263 PCIBus *bus; 264 PCIDevice *host_bridge; 265 int ret; 266 267 bus = pci_device_root_bus(&vdev->pdev); 268 host_bridge = pci_find_device(bus, 0, PCI_DEVFN(0, 0)); 269 270 if (!host_bridge) { 271 error_report("Can't find host bridge"); 272 return -ENODEV; 273 } 274 275 ret = vfio_pci_igd_copy(vdev, host_bridge, info, igd_host_bridge_infos, 276 ARRAY_SIZE(igd_host_bridge_infos)); 277 if (!ret) { 278 trace_vfio_pci_igd_host_bridge_enabled(vdev->vbasedev.name); 279 } 280 281 return ret; 282 } 283 284 /* 285 * IGD LPC/ISA bridge support code. The vBIOS needs this, but we can't write 286 * arbitrary values into just any bridge, so we must create our own. We try 287 * to handle if the user has created it for us, which they might want to do 288 * to enable multifunction so we don't occupy the whole PCI slot. 289 */ 290 static void vfio_pci_igd_lpc_bridge_realize(PCIDevice *pdev, Error **errp) 291 { 292 if (pdev->devfn != PCI_DEVFN(0x1f, 0)) { 293 error_setg(errp, "VFIO dummy ISA/LPC bridge must have address 1f.0"); 294 } 295 } 296 297 static void vfio_pci_igd_lpc_bridge_class_init(ObjectClass *klass, 298 const void *data) 299 { 300 DeviceClass *dc = DEVICE_CLASS(klass); 301 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 302 303 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 304 dc->desc = "VFIO dummy ISA/LPC bridge for IGD assignment"; 305 dc->hotpluggable = false; 306 k->realize = vfio_pci_igd_lpc_bridge_realize; 307 k->class_id = PCI_CLASS_BRIDGE_ISA; 308 } 309 310 static const TypeInfo vfio_pci_igd_lpc_bridge_info = { 311 .name = "vfio-pci-igd-lpc-bridge", 312 .parent = TYPE_PCI_DEVICE, 313 .class_init = vfio_pci_igd_lpc_bridge_class_init, 314 .interfaces = (const InterfaceInfo[]) { 315 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 316 { }, 317 }, 318 }; 319 320 static void vfio_pci_igd_register_types(void) 321 { 322 type_register_static(&vfio_pci_igd_lpc_bridge_info); 323 } 324 325 type_init(vfio_pci_igd_register_types) 326 327 static int vfio_pci_igd_lpc_init(VFIOPCIDevice *vdev, 328 struct vfio_region_info *info) 329 { 330 PCIDevice *lpc_bridge; 331 int ret; 332 333 lpc_bridge = pci_find_device(pci_device_root_bus(&vdev->pdev), 334 0, PCI_DEVFN(0x1f, 0)); 335 if (!lpc_bridge) { 336 lpc_bridge = pci_create_simple(pci_device_root_bus(&vdev->pdev), 337 PCI_DEVFN(0x1f, 0), "vfio-pci-igd-lpc-bridge"); 338 } 339 340 ret = vfio_pci_igd_copy(vdev, lpc_bridge, info, igd_lpc_bridge_infos, 341 ARRAY_SIZE(igd_lpc_bridge_infos)); 342 if (!ret) { 343 trace_vfio_pci_igd_lpc_bridge_enabled(vdev->vbasedev.name); 344 } 345 346 return ret; 347 } 348 349 static bool vfio_pci_igd_setup_lpc_bridge(VFIOPCIDevice *vdev, Error **errp) 350 { 351 g_autofree struct vfio_region_info *host = NULL; 352 g_autofree struct vfio_region_info *lpc = NULL; 353 PCIDevice *lpc_bridge; 354 int ret; 355 356 /* 357 * Copying IDs or creating new devices are not supported on hotplug 358 */ 359 if (vdev->pdev.qdev.hotplugged) { 360 error_setg(errp, "IGD LPC is not supported on hotplugged device"); 361 return false; 362 } 363 364 /* 365 * We need to create an LPC/ISA bridge at PCI bus address 00:1f.0 that we 366 * can stuff host values into, so if there's already one there and it's not 367 * one we can hack on, this quirk is no-go. Sorry Q35. 368 */ 369 lpc_bridge = pci_find_device(pci_device_root_bus(&vdev->pdev), 370 0, PCI_DEVFN(0x1f, 0)); 371 if (lpc_bridge && !object_dynamic_cast(OBJECT(lpc_bridge), 372 "vfio-pci-igd-lpc-bridge")) { 373 error_setg(errp, 374 "Cannot create LPC bridge due to existing device at 1f.0"); 375 return false; 376 } 377 378 /* 379 * Check whether we have all the vfio device specific regions to 380 * support LPC quirk (added in Linux v4.6). 381 */ 382 ret = vfio_device_get_region_info_type(&vdev->vbasedev, 383 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL, 384 VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG, &lpc); 385 if (ret) { 386 error_setg(errp, "IGD LPC bridge access is not supported by kernel"); 387 return false; 388 } 389 390 ret = vfio_device_get_region_info_type(&vdev->vbasedev, 391 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL, 392 VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG, &host); 393 if (ret) { 394 error_setg(errp, "IGD host bridge access is not supported by kernel"); 395 return false; 396 } 397 398 /* Create/modify LPC bridge */ 399 ret = vfio_pci_igd_lpc_init(vdev, lpc); 400 if (ret) { 401 error_setg(errp, "Failed to create/modify LPC bridge for IGD"); 402 return false; 403 } 404 405 /* Stuff some host values into the VM PCI host bridge */ 406 ret = vfio_pci_igd_host_init(vdev, host); 407 if (ret) { 408 error_setg(errp, "Failed to modify host bridge for IGD"); 409 return false; 410 } 411 412 return true; 413 } 414 415 static bool vfio_pci_igd_override_gms(int gen, uint32_t gms, uint32_t *gmch) 416 { 417 bool ret = false; 418 419 if (gen == -1) { 420 error_report("x-igd-gms is not supported on this device"); 421 } else if (gen < 8) { 422 if (gms <= 0x10) { 423 *gmch &= ~(IGD_GMCH_GEN6_GMS_MASK << IGD_GMCH_GEN6_GMS_SHIFT); 424 *gmch |= gms << IGD_GMCH_GEN6_GMS_SHIFT; 425 ret = true; 426 } else { 427 error_report(QERR_INVALID_PARAMETER_VALUE, "x-igd-gms", "0~0x10"); 428 } 429 } else if (gen == 8) { 430 if (gms <= 0x40) { 431 *gmch &= ~(IGD_GMCH_GEN8_GMS_MASK << IGD_GMCH_GEN8_GMS_SHIFT); 432 *gmch |= gms << IGD_GMCH_GEN8_GMS_SHIFT; 433 ret = true; 434 } else { 435 error_report(QERR_INVALID_PARAMETER_VALUE, "x-igd-gms", "0~0x40"); 436 } 437 } else { 438 /* 0x0 to 0x40: 32MB increments starting at 0MB */ 439 /* 0xf0 to 0xfe: 4MB increments starting at 4MB */ 440 if ((gms <= 0x40) || (gms >= 0xf0 && gms <= 0xfe)) { 441 *gmch &= ~(IGD_GMCH_GEN8_GMS_MASK << IGD_GMCH_GEN8_GMS_SHIFT); 442 *gmch |= gms << IGD_GMCH_GEN8_GMS_SHIFT; 443 ret = true; 444 } else { 445 error_report(QERR_INVALID_PARAMETER_VALUE, 446 "x-igd-gms", "0~0x40 or 0xf0~0xfe"); 447 } 448 } 449 450 return ret; 451 } 452 453 #define IGD_GGC_MMIO_OFFSET 0x108040 454 #define IGD_BDSM_MMIO_OFFSET 0x1080C0 455 456 void vfio_probe_igd_bar0_quirk(VFIOPCIDevice *vdev, int nr) 457 { 458 VFIOQuirk *ggc_quirk, *bdsm_quirk; 459 VFIOConfigMirrorQuirk *ggc_mirror, *bdsm_mirror; 460 int gen; 461 462 /* 463 * This must be an Intel VGA device at address 00:02.0 for us to even 464 * consider enabling legacy mode. Some driver have dependencies on the PCI 465 * bus address. 466 */ 467 if (!vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, PCI_ANY_ID) || 468 !vfio_is_vga(vdev) || nr != 0) { 469 return; 470 } 471 472 /* 473 * Only on IGD devices of gen 11 and above, the BDSM register is mirrored 474 * into MMIO space and read from MMIO space by the Windows driver. 475 */ 476 gen = igd_gen(vdev); 477 if (gen < 6) { 478 return; 479 } 480 481 ggc_quirk = vfio_quirk_alloc(1); 482 ggc_mirror = ggc_quirk->data = g_malloc0(sizeof(*ggc_mirror)); 483 ggc_mirror->mem = ggc_quirk->mem; 484 ggc_mirror->vdev = vdev; 485 ggc_mirror->bar = nr; 486 ggc_mirror->offset = IGD_GGC_MMIO_OFFSET; 487 ggc_mirror->config_offset = IGD_GMCH; 488 489 memory_region_init_io(ggc_mirror->mem, OBJECT(vdev), 490 &vfio_generic_mirror_quirk, ggc_mirror, 491 "vfio-igd-ggc-quirk", 2); 492 memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, 493 ggc_mirror->offset, ggc_mirror->mem, 494 1); 495 496 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, ggc_quirk, next); 497 498 bdsm_quirk = vfio_quirk_alloc(1); 499 bdsm_mirror = bdsm_quirk->data = g_malloc0(sizeof(*bdsm_mirror)); 500 bdsm_mirror->mem = bdsm_quirk->mem; 501 bdsm_mirror->vdev = vdev; 502 bdsm_mirror->bar = nr; 503 bdsm_mirror->offset = IGD_BDSM_MMIO_OFFSET; 504 bdsm_mirror->config_offset = (gen < 11) ? IGD_BDSM : IGD_BDSM_GEN11; 505 506 memory_region_init_io(bdsm_mirror->mem, OBJECT(vdev), 507 &vfio_generic_mirror_quirk, bdsm_mirror, 508 "vfio-igd-bdsm-quirk", (gen < 11) ? 4 : 8); 509 memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, 510 bdsm_mirror->offset, bdsm_mirror->mem, 511 1); 512 513 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, bdsm_quirk, next); 514 } 515 516 static bool vfio_pci_igd_config_quirk(VFIOPCIDevice *vdev, Error **errp) 517 { 518 g_autofree struct vfio_region_info *opregion = NULL; 519 int ret, gen; 520 uint64_t gms_size; 521 uint64_t *bdsm_size; 522 uint32_t gmch; 523 bool legacy_mode_enabled = false; 524 Error *err = NULL; 525 526 if (!vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, PCI_ANY_ID) || 527 !vfio_is_vga(vdev)) { 528 return true; 529 } 530 531 /* IGD device always comes with OpRegion */ 532 if (!vfio_pci_igd_opregion_detect(vdev, &opregion, errp)) { 533 return true; 534 } 535 info_report("OpRegion detected on Intel display %x.", vdev->device_id); 536 537 /* 538 * IGD is not a standard, they like to change their specs often. We 539 * only attempt to support back to SandBridge and we hope that newer 540 * devices maintain compatibility with generation 8. 541 */ 542 gen = igd_gen(vdev); 543 if (gen == -1) { 544 error_report("IGD device %s is unsupported in legacy mode, " 545 "try SandyBridge or newer", vdev->vbasedev.name); 546 return true; 547 } 548 549 gmch = vfio_pci_read_config(&vdev->pdev, IGD_GMCH, 4); 550 551 /* 552 * For backward compatibility, enable legacy mode when 553 * - Device geneation is 6 to 9 (including both) 554 * - Machine type is i440fx (pc_piix) 555 * - IGD device is at guest BDF 00:02.0 556 * - Not manually disabled by x-igd-legacy-mode=off 557 */ 558 if ((vdev->igd_legacy_mode != ON_OFF_AUTO_OFF) && 559 (gen >= 6 && gen <= 9) && 560 !strcmp(MACHINE_GET_CLASS(qdev_get_machine())->family, "pc_piix") && 561 (&vdev->pdev == pci_find_device(pci_device_root_bus(&vdev->pdev), 562 0, PCI_DEVFN(0x2, 0)))) { 563 /* 564 * IGD legacy mode requires: 565 * - VBIOS in ROM BAR or file 566 * - VGA IO/MMIO ranges are claimed by IGD 567 * - OpRegion 568 * - Same LPC bridge and Host bridge VID/DID/SVID/SSID as host 569 */ 570 g_autofree struct vfio_region_info *rom = NULL; 571 572 legacy_mode_enabled = true; 573 info_report("IGD legacy mode enabled, " 574 "use x-igd-legacy-mode=off to disable it if unwanted."); 575 576 /* 577 * Most of what we're doing here is to enable the ROM to run, so if 578 * there's no ROM, there's no point in setting up this quirk. 579 * NB. We only seem to get BIOS ROMs, so UEFI VM would need CSM support. 580 */ 581 ret = vfio_device_get_region_info(&vdev->vbasedev, 582 VFIO_PCI_ROM_REGION_INDEX, &rom); 583 if ((ret || !rom->size) && !vdev->pdev.romfile) { 584 error_setg(&err, "Device has no ROM"); 585 goto error; 586 } 587 588 /* 589 * If IGD VGA Disable is clear (expected) and VGA is not already 590 * enabled, try to enable it. Probably shouldn't be using legacy mode 591 * without VGA, but also no point in us enabling VGA if disabled in 592 * hardware. 593 */ 594 if (!(gmch & 0x2) && !vdev->vga && !vfio_populate_vga(vdev, &err)) { 595 error_setg(&err, "Unable to enable VGA access"); 596 goto error; 597 } 598 599 /* Enable OpRegion and LPC bridge quirk */ 600 vdev->features |= VFIO_FEATURE_ENABLE_IGD_OPREGION; 601 vdev->features |= VFIO_FEATURE_ENABLE_IGD_LPC; 602 } else if (vdev->igd_legacy_mode == ON_OFF_AUTO_ON) { 603 error_setg(&err, 604 "Machine is not i440fx, assigned BDF is not 00:02.0, " 605 "or device %04x (gen %d) doesn't support legacy mode", 606 vdev->device_id, gen); 607 goto error; 608 } 609 610 /* Setup OpRegion access */ 611 if ((vdev->features & VFIO_FEATURE_ENABLE_IGD_OPREGION) && 612 !vfio_pci_igd_opregion_init(vdev, opregion, errp)) { 613 goto error; 614 } 615 616 /* Setup LPC bridge / Host bridge PCI IDs */ 617 if ((vdev->features & VFIO_FEATURE_ENABLE_IGD_LPC) && 618 !vfio_pci_igd_setup_lpc_bridge(vdev, errp)) { 619 goto error; 620 } 621 622 /* 623 * ASLS (OpRegion address) is read-only, emulated 624 * It contains HPA, guest firmware need to reprogram it with GPA. 625 */ 626 pci_set_long(vdev->pdev.config + IGD_ASLS, 0); 627 pci_set_long(vdev->pdev.wmask + IGD_ASLS, ~0); 628 pci_set_long(vdev->emulated_config_bits + IGD_ASLS, ~0); 629 630 /* 631 * Allow user to override dsm size using x-igd-gms option, in multiples of 632 * 32MiB. This option should only be used when the desired size cannot be 633 * set from DVMT Pre-Allocated option in host BIOS. 634 */ 635 if (vdev->igd_gms && 636 !vfio_pci_igd_override_gms(gen, vdev->igd_gms, &gmch)) { 637 return false; 638 } 639 640 gms_size = igd_stolen_memory_size(gen, gmch); 641 642 /* 643 * Request reserved memory for stolen memory via fw_cfg. VM firmware 644 * must allocate a 1MB aligned reserved memory region below 4GB with 645 * the requested size (in bytes) for use by the Intel PCI class VGA 646 * device at VM address 00:02.0. The base address of this reserved 647 * memory region must be written to the device BDSM register at PCI 648 * config offset 0x5C. 649 */ 650 bdsm_size = g_malloc(sizeof(*bdsm_size)); 651 *bdsm_size = cpu_to_le64(gms_size); 652 fw_cfg_add_file(fw_cfg_find(), "etc/igd-bdsm-size", 653 bdsm_size, sizeof(*bdsm_size)); 654 655 /* GMCH is read-only, emulated */ 656 pci_set_long(vdev->pdev.config + IGD_GMCH, gmch); 657 pci_set_long(vdev->pdev.wmask + IGD_GMCH, 0); 658 pci_set_long(vdev->emulated_config_bits + IGD_GMCH, ~0); 659 660 /* BDSM is read-write, emulated. The BIOS needs to be able to write it */ 661 if (gen < 11) { 662 pci_set_long(vdev->pdev.config + IGD_BDSM, 0); 663 pci_set_long(vdev->pdev.wmask + IGD_BDSM, ~0); 664 pci_set_long(vdev->emulated_config_bits + IGD_BDSM, ~0); 665 } else { 666 pci_set_quad(vdev->pdev.config + IGD_BDSM_GEN11, 0); 667 pci_set_quad(vdev->pdev.wmask + IGD_BDSM_GEN11, ~0); 668 pci_set_quad(vdev->emulated_config_bits + IGD_BDSM_GEN11, ~0); 669 } 670 671 trace_vfio_pci_igd_bdsm_enabled(vdev->vbasedev.name, (gms_size / MiB)); 672 673 return true; 674 675 error: 676 /* 677 * When legacy mode is implicity enabled, continue on error, 678 * to keep compatibility 679 */ 680 if (legacy_mode_enabled && (vdev->igd_legacy_mode == ON_OFF_AUTO_AUTO)) { 681 error_report_err(err); 682 error_report("IGD legacy mode disabled"); 683 return true; 684 } 685 686 error_propagate(errp, err); 687 return false; 688 } 689 690 /* 691 * KVMGT/GVT-g vGPU exposes an emulated OpRegion. So far, users have to specify 692 * x-igd-opregion=on to enable the access. 693 * TODO: Check VID/DID and enable opregion access automatically 694 */ 695 static bool vfio_pci_kvmgt_config_quirk(VFIOPCIDevice *vdev, Error **errp) 696 { 697 g_autofree struct vfio_region_info *opregion = NULL; 698 int gen; 699 700 if (!vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, PCI_ANY_ID) || 701 !vfio_is_vga(vdev)) { 702 return true; 703 } 704 705 /* FIXME: Cherryview is Gen8, but don't support GVT-g */ 706 gen = igd_gen(vdev); 707 if (gen != 8 && gen != 9) { 708 return true; 709 } 710 711 if (!vfio_pci_igd_opregion_detect(vdev, &opregion, errp)) { 712 /* Should never reach here, KVMGT always emulates OpRegion */ 713 return false; 714 } 715 716 if ((vdev->features & VFIO_FEATURE_ENABLE_IGD_OPREGION) && 717 !vfio_pci_igd_opregion_init(vdev, opregion, errp)) { 718 return false; 719 } 720 721 return true; 722 } 723 724 bool vfio_probe_igd_config_quirk(VFIOPCIDevice *vdev, Error **errp) 725 { 726 /* KVMGT/GVT-g vGPU is exposed as mdev */ 727 if (vdev->vbasedev.mdev) { 728 return vfio_pci_kvmgt_config_quirk(vdev, errp); 729 } 730 731 return vfio_pci_igd_config_quirk(vdev, errp); 732 } 733