1 /* 2 * IGD device quirks 3 * 4 * Copyright Red Hat, Inc. 2016 5 * 6 * Authors: 7 * Alex Williamson <alex.williamson@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2. See 10 * the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qemu/units.h" 15 #include "qemu/error-report.h" 16 #include "qapi/error.h" 17 #include "qapi/qmp/qerror.h" 18 #include "hw/boards.h" 19 #include "hw/hw.h" 20 #include "hw/nvram/fw_cfg.h" 21 #include "pci.h" 22 #include "pci-quirks.h" 23 #include "trace.h" 24 25 /* 26 * Intel IGD support 27 * 28 * Obviously IGD is not a discrete device, this is evidenced not only by it 29 * being integrated into the CPU, but by the various chipset and BIOS 30 * dependencies that it brings along with it. Intel is trying to move away 31 * from this and Broadwell and newer devices can run in what Intel calls 32 * "Universal Pass-Through" mode, or UPT. Theoretically in UPT mode, nothing 33 * more is required beyond assigning the IGD device to a VM. There are 34 * however support limitations to this mode. It only supports IGD as a 35 * secondary graphics device in the VM and it doesn't officially support any 36 * physical outputs. 37 * 38 * The code here attempts to enable what we'll call legacy mode assignment, 39 * IGD retains most of the capabilities we expect for it to have on bare 40 * metal. To enable this mode, the IGD device must be assigned to the VM 41 * at PCI address 00:02.0, it must have a ROM, it very likely needs VGA 42 * support, we must have VM BIOS support for reserving and populating some 43 * of the required tables, and we need to tweak the chipset with revisions 44 * and IDs and an LPC/ISA bridge device. The intention is to make all of 45 * this happen automatically by installing the device at the correct VM PCI 46 * bus address. If any of the conditions are not met, we cross our fingers 47 * and hope the user knows better. 48 * 49 * NB - It is possible to enable physical outputs in UPT mode by supplying 50 * an OpRegion table. We don't do this by default because the guest driver 51 * behaves differently if an OpRegion is provided and no monitor is attached 52 * vs no OpRegion and a monitor being attached or not. Effectively, if a 53 * headless setup is desired, the OpRegion gets in the way of that. 54 */ 55 56 /* 57 * This presumes the device is already known to be an Intel VGA device, so we 58 * take liberties in which device ID bits match which generation. This should 59 * not be taken as an indication that all the devices are supported, or even 60 * supportable, some of them don't even support VT-d. 61 * See linux:include/drm/i915_pciids.h for IDs. 62 */ 63 static int igd_gen(VFIOPCIDevice *vdev) 64 { 65 /* 66 * Device IDs for Broxton/Apollo Lake are 0x0a84, 0x1a84, 0x1a85, 0x5a84 67 * and 0x5a85, match bit 11:1 here 68 * Prefix 0x0a is taken by Haswell, this rule should be matched first. 69 */ 70 if ((vdev->device_id & 0xffe) == 0xa84) { 71 return 9; 72 } 73 74 switch (vdev->device_id & 0xff00) { 75 case 0x0100: /* SandyBridge, IvyBridge */ 76 return 6; 77 case 0x0400: /* Haswell */ 78 case 0x0a00: /* Haswell */ 79 case 0x0c00: /* Haswell */ 80 case 0x0d00: /* Haswell */ 81 case 0x0f00: /* Valleyview/Bay Trail */ 82 return 7; 83 case 0x1600: /* Broadwell */ 84 case 0x2200: /* Cherryview */ 85 return 8; 86 case 0x1900: /* Skylake */ 87 case 0x3100: /* Gemini Lake */ 88 case 0x5900: /* Kaby Lake */ 89 case 0x3e00: /* Coffee Lake */ 90 case 0x9B00: /* Comet Lake */ 91 return 9; 92 case 0x8A00: /* Ice Lake */ 93 case 0x4500: /* Elkhart Lake */ 94 case 0x4E00: /* Jasper Lake */ 95 return 11; 96 case 0x9A00: /* Tiger Lake */ 97 case 0x4C00: /* Rocket Lake */ 98 case 0x4600: /* Alder Lake */ 99 case 0xA700: /* Raptor Lake */ 100 return 12; 101 } 102 103 /* 104 * Unfortunately, Intel changes it's specification quite often. This makes 105 * it impossible to use a suitable default value for unknown devices. 106 */ 107 return -1; 108 } 109 110 #define IGD_ASLS 0xfc /* ASL Storage Register */ 111 #define IGD_GMCH 0x50 /* Graphics Control Register */ 112 #define IGD_BDSM 0x5c /* Base Data of Stolen Memory */ 113 #define IGD_BDSM_GEN11 0xc0 /* Base Data of Stolen Memory of gen 11 and later */ 114 115 #define IGD_GMCH_GEN6_GMS_SHIFT 3 /* SNB_GMCH in i915 */ 116 #define IGD_GMCH_GEN6_GMS_MASK 0x1f 117 #define IGD_GMCH_GEN8_GMS_SHIFT 8 /* BDW_GMCH in i915 */ 118 #define IGD_GMCH_GEN8_GMS_MASK 0xff 119 120 static uint64_t igd_stolen_memory_size(int gen, uint32_t gmch) 121 { 122 uint64_t gms; 123 124 if (gen < 8) { 125 gms = (gmch >> IGD_GMCH_GEN6_GMS_SHIFT) & IGD_GMCH_GEN6_GMS_MASK; 126 } else { 127 gms = (gmch >> IGD_GMCH_GEN8_GMS_SHIFT) & IGD_GMCH_GEN8_GMS_MASK; 128 } 129 130 if (gen < 9) { 131 return gms * 32 * MiB; 132 } else { 133 if (gms < 0xf0) { 134 return gms * 32 * MiB; 135 } else { 136 return (gms - 0xf0 + 1) * 4 * MiB; 137 } 138 } 139 140 return 0; 141 } 142 143 /* 144 * The OpRegion includes the Video BIOS Table, which seems important for 145 * telling the driver what sort of outputs it has. Without this, the device 146 * may work in the guest, but we may not get output. This also requires BIOS 147 * support to reserve and populate a section of guest memory sufficient for 148 * the table and to write the base address of that memory to the ASLS register 149 * of the IGD device. 150 */ 151 static bool vfio_pci_igd_opregion_init(VFIOPCIDevice *vdev, 152 struct vfio_region_info *info, 153 Error **errp) 154 { 155 int ret; 156 157 vdev->igd_opregion = g_malloc0(info->size); 158 ret = pread(vdev->vbasedev.fd, vdev->igd_opregion, 159 info->size, info->offset); 160 if (ret != info->size) { 161 error_setg(errp, "failed to read IGD OpRegion"); 162 g_free(vdev->igd_opregion); 163 vdev->igd_opregion = NULL; 164 return false; 165 } 166 167 /* 168 * Provide fw_cfg with a copy of the OpRegion which the VM firmware is to 169 * allocate 32bit reserved memory for, copy these contents into, and write 170 * the reserved memory base address to the device ASLS register at 0xFC. 171 * Alignment of this reserved region seems flexible, but using a 4k page 172 * alignment seems to work well. This interface assumes a single IGD 173 * device, which may be at VM address 00:02.0 in legacy mode or another 174 * address in UPT mode. 175 * 176 * NB, there may be future use cases discovered where the VM should have 177 * direct interaction with the host OpRegion, in which case the write to 178 * the ASLS register would trigger MemoryRegion setup to enable that. 179 */ 180 fw_cfg_add_file(fw_cfg_find(), "etc/igd-opregion", 181 vdev->igd_opregion, info->size); 182 183 trace_vfio_pci_igd_opregion_enabled(vdev->vbasedev.name); 184 185 return true; 186 } 187 188 static bool vfio_pci_igd_setup_opregion(VFIOPCIDevice *vdev, Error **errp) 189 { 190 g_autofree struct vfio_region_info *opregion = NULL; 191 int ret; 192 193 /* Hotplugging is not supported for opregion access */ 194 if (vdev->pdev.qdev.hotplugged) { 195 error_setg(errp, "IGD OpRegion is not supported on hotplugged device"); 196 return false; 197 } 198 199 ret = vfio_device_get_region_info_type(&vdev->vbasedev, 200 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL, 201 VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION, &opregion); 202 if (ret) { 203 error_setg_errno(errp, -ret, 204 "Device does not supports IGD OpRegion feature"); 205 return false; 206 } 207 208 if (!vfio_pci_igd_opregion_init(vdev, opregion, errp)) { 209 return false; 210 } 211 212 return true; 213 } 214 215 /* 216 * The rather short list of registers that we copy from the host devices. 217 * The LPC/ISA bridge values are definitely needed to support the vBIOS, the 218 * host bridge values may or may not be needed depending on the guest OS. 219 * Since we're only munging revision and subsystem values on the host bridge, 220 * we don't require our own device. The LPC/ISA bridge needs to be our very 221 * own though. 222 */ 223 typedef struct { 224 uint8_t offset; 225 uint8_t len; 226 } IGDHostInfo; 227 228 static const IGDHostInfo igd_host_bridge_infos[] = { 229 {PCI_REVISION_ID, 2}, 230 {PCI_SUBSYSTEM_VENDOR_ID, 2}, 231 {PCI_SUBSYSTEM_ID, 2}, 232 }; 233 234 static const IGDHostInfo igd_lpc_bridge_infos[] = { 235 {PCI_VENDOR_ID, 2}, 236 {PCI_DEVICE_ID, 2}, 237 {PCI_REVISION_ID, 2}, 238 {PCI_SUBSYSTEM_VENDOR_ID, 2}, 239 {PCI_SUBSYSTEM_ID, 2}, 240 }; 241 242 static int vfio_pci_igd_copy(VFIOPCIDevice *vdev, PCIDevice *pdev, 243 struct vfio_region_info *info, 244 const IGDHostInfo *list, int len) 245 { 246 int i, ret; 247 248 for (i = 0; i < len; i++) { 249 ret = pread(vdev->vbasedev.fd, pdev->config + list[i].offset, 250 list[i].len, info->offset + list[i].offset); 251 if (ret != list[i].len) { 252 error_report("IGD copy failed: %m"); 253 return -errno; 254 } 255 } 256 257 return 0; 258 } 259 260 /* 261 * Stuff a few values into the host bridge. 262 */ 263 static int vfio_pci_igd_host_init(VFIOPCIDevice *vdev, 264 struct vfio_region_info *info) 265 { 266 PCIBus *bus; 267 PCIDevice *host_bridge; 268 int ret; 269 270 bus = pci_device_root_bus(&vdev->pdev); 271 host_bridge = pci_find_device(bus, 0, PCI_DEVFN(0, 0)); 272 273 if (!host_bridge) { 274 error_report("Can't find host bridge"); 275 return -ENODEV; 276 } 277 278 ret = vfio_pci_igd_copy(vdev, host_bridge, info, igd_host_bridge_infos, 279 ARRAY_SIZE(igd_host_bridge_infos)); 280 if (!ret) { 281 trace_vfio_pci_igd_host_bridge_enabled(vdev->vbasedev.name); 282 } 283 284 return ret; 285 } 286 287 /* 288 * IGD LPC/ISA bridge support code. The vBIOS needs this, but we can't write 289 * arbitrary values into just any bridge, so we must create our own. We try 290 * to handle if the user has created it for us, which they might want to do 291 * to enable multifunction so we don't occupy the whole PCI slot. 292 */ 293 static void vfio_pci_igd_lpc_bridge_realize(PCIDevice *pdev, Error **errp) 294 { 295 if (pdev->devfn != PCI_DEVFN(0x1f, 0)) { 296 error_setg(errp, "VFIO dummy ISA/LPC bridge must have address 1f.0"); 297 } 298 } 299 300 static void vfio_pci_igd_lpc_bridge_class_init(ObjectClass *klass, 301 const void *data) 302 { 303 DeviceClass *dc = DEVICE_CLASS(klass); 304 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 305 306 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 307 dc->desc = "VFIO dummy ISA/LPC bridge for IGD assignment"; 308 dc->hotpluggable = false; 309 k->realize = vfio_pci_igd_lpc_bridge_realize; 310 k->class_id = PCI_CLASS_BRIDGE_ISA; 311 } 312 313 static const TypeInfo vfio_pci_igd_lpc_bridge_info = { 314 .name = "vfio-pci-igd-lpc-bridge", 315 .parent = TYPE_PCI_DEVICE, 316 .class_init = vfio_pci_igd_lpc_bridge_class_init, 317 .interfaces = (const InterfaceInfo[]) { 318 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 319 { }, 320 }, 321 }; 322 323 static void vfio_pci_igd_register_types(void) 324 { 325 type_register_static(&vfio_pci_igd_lpc_bridge_info); 326 } 327 328 type_init(vfio_pci_igd_register_types) 329 330 static int vfio_pci_igd_lpc_init(VFIOPCIDevice *vdev, 331 struct vfio_region_info *info) 332 { 333 PCIDevice *lpc_bridge; 334 int ret; 335 336 lpc_bridge = pci_find_device(pci_device_root_bus(&vdev->pdev), 337 0, PCI_DEVFN(0x1f, 0)); 338 if (!lpc_bridge) { 339 lpc_bridge = pci_create_simple(pci_device_root_bus(&vdev->pdev), 340 PCI_DEVFN(0x1f, 0), "vfio-pci-igd-lpc-bridge"); 341 } 342 343 ret = vfio_pci_igd_copy(vdev, lpc_bridge, info, igd_lpc_bridge_infos, 344 ARRAY_SIZE(igd_lpc_bridge_infos)); 345 if (!ret) { 346 trace_vfio_pci_igd_lpc_bridge_enabled(vdev->vbasedev.name); 347 } 348 349 return ret; 350 } 351 352 static bool vfio_pci_igd_setup_lpc_bridge(VFIOPCIDevice *vdev, Error **errp) 353 { 354 g_autofree struct vfio_region_info *host = NULL; 355 g_autofree struct vfio_region_info *lpc = NULL; 356 PCIDevice *lpc_bridge; 357 int ret; 358 359 /* 360 * Copying IDs or creating new devices are not supported on hotplug 361 */ 362 if (vdev->pdev.qdev.hotplugged) { 363 error_setg(errp, "IGD LPC is not supported on hotplugged device"); 364 return false; 365 } 366 367 /* 368 * We need to create an LPC/ISA bridge at PCI bus address 00:1f.0 that we 369 * can stuff host values into, so if there's already one there and it's not 370 * one we can hack on, this quirk is no-go. Sorry Q35. 371 */ 372 lpc_bridge = pci_find_device(pci_device_root_bus(&vdev->pdev), 373 0, PCI_DEVFN(0x1f, 0)); 374 if (lpc_bridge && !object_dynamic_cast(OBJECT(lpc_bridge), 375 "vfio-pci-igd-lpc-bridge")) { 376 error_setg(errp, 377 "Cannot create LPC bridge due to existing device at 1f.0"); 378 return false; 379 } 380 381 /* 382 * Check whether we have all the vfio device specific regions to 383 * support LPC quirk (added in Linux v4.6). 384 */ 385 ret = vfio_device_get_region_info_type(&vdev->vbasedev, 386 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL, 387 VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG, &lpc); 388 if (ret) { 389 error_setg(errp, "IGD LPC bridge access is not supported by kernel"); 390 return false; 391 } 392 393 ret = vfio_device_get_region_info_type(&vdev->vbasedev, 394 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL, 395 VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG, &host); 396 if (ret) { 397 error_setg(errp, "IGD host bridge access is not supported by kernel"); 398 return false; 399 } 400 401 /* Create/modify LPC bridge */ 402 ret = vfio_pci_igd_lpc_init(vdev, lpc); 403 if (ret) { 404 error_setg(errp, "Failed to create/modify LPC bridge for IGD"); 405 return false; 406 } 407 408 /* Stuff some host values into the VM PCI host bridge */ 409 ret = vfio_pci_igd_host_init(vdev, host); 410 if (ret) { 411 error_setg(errp, "Failed to modify host bridge for IGD"); 412 return false; 413 } 414 415 return true; 416 } 417 418 #define IGD_GGC_MMIO_OFFSET 0x108040 419 #define IGD_BDSM_MMIO_OFFSET 0x1080C0 420 421 void vfio_probe_igd_bar0_quirk(VFIOPCIDevice *vdev, int nr) 422 { 423 VFIOQuirk *ggc_quirk, *bdsm_quirk; 424 VFIOConfigMirrorQuirk *ggc_mirror, *bdsm_mirror; 425 int gen; 426 427 /* 428 * This must be an Intel VGA device at address 00:02.0 for us to even 429 * consider enabling legacy mode. Some driver have dependencies on the PCI 430 * bus address. 431 */ 432 if (!vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, PCI_ANY_ID) || 433 !vfio_is_vga(vdev) || nr != 0) { 434 return; 435 } 436 437 /* 438 * Only on IGD devices of gen 11 and above, the BDSM register is mirrored 439 * into MMIO space and read from MMIO space by the Windows driver. 440 */ 441 gen = igd_gen(vdev); 442 if (gen < 6) { 443 return; 444 } 445 446 ggc_quirk = vfio_quirk_alloc(1); 447 ggc_mirror = ggc_quirk->data = g_malloc0(sizeof(*ggc_mirror)); 448 ggc_mirror->mem = ggc_quirk->mem; 449 ggc_mirror->vdev = vdev; 450 ggc_mirror->bar = nr; 451 ggc_mirror->offset = IGD_GGC_MMIO_OFFSET; 452 ggc_mirror->config_offset = IGD_GMCH; 453 454 memory_region_init_io(ggc_mirror->mem, OBJECT(vdev), 455 &vfio_generic_mirror_quirk, ggc_mirror, 456 "vfio-igd-ggc-quirk", 2); 457 memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, 458 ggc_mirror->offset, ggc_mirror->mem, 459 1); 460 461 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, ggc_quirk, next); 462 463 bdsm_quirk = vfio_quirk_alloc(1); 464 bdsm_mirror = bdsm_quirk->data = g_malloc0(sizeof(*bdsm_mirror)); 465 bdsm_mirror->mem = bdsm_quirk->mem; 466 bdsm_mirror->vdev = vdev; 467 bdsm_mirror->bar = nr; 468 bdsm_mirror->offset = IGD_BDSM_MMIO_OFFSET; 469 bdsm_mirror->config_offset = (gen < 11) ? IGD_BDSM : IGD_BDSM_GEN11; 470 471 memory_region_init_io(bdsm_mirror->mem, OBJECT(vdev), 472 &vfio_generic_mirror_quirk, bdsm_mirror, 473 "vfio-igd-bdsm-quirk", (gen < 11) ? 4 : 8); 474 memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, 475 bdsm_mirror->offset, bdsm_mirror->mem, 476 1); 477 478 QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, bdsm_quirk, next); 479 } 480 481 static bool vfio_pci_igd_config_quirk(VFIOPCIDevice *vdev, Error **errp) 482 { 483 int ret, gen; 484 uint64_t gms_size; 485 uint64_t *bdsm_size; 486 uint32_t gmch; 487 bool legacy_mode_enabled = false; 488 Error *err = NULL; 489 490 /* 491 * This must be an Intel VGA device at address 00:02.0 for us to even 492 * consider enabling legacy mode. The vBIOS has dependencies on the 493 * PCI bus address. 494 */ 495 if (!vfio_pci_is(vdev, PCI_VENDOR_ID_INTEL, PCI_ANY_ID) || 496 !vfio_is_vga(vdev)) { 497 return true; 498 } 499 500 /* 501 * IGD is not a standard, they like to change their specs often. We 502 * only attempt to support back to SandBridge and we hope that newer 503 * devices maintain compatibility with generation 8. 504 */ 505 gen = igd_gen(vdev); 506 if (gen == -1) { 507 error_report("IGD device %s is unsupported in legacy mode, " 508 "try SandyBridge or newer", vdev->vbasedev.name); 509 return true; 510 } 511 512 gmch = vfio_pci_read_config(&vdev->pdev, IGD_GMCH, 4); 513 514 /* 515 * For backward compatibility, enable legacy mode when 516 * - Device geneation is 6 to 9 (including both) 517 * - Machine type is i440fx (pc_piix) 518 * - IGD device is at guest BDF 00:02.0 519 * - Not manually disabled by x-igd-legacy-mode=off 520 */ 521 if ((vdev->igd_legacy_mode != ON_OFF_AUTO_OFF) && 522 (gen >= 6 && gen <= 9) && 523 !strcmp(MACHINE_GET_CLASS(qdev_get_machine())->family, "pc_piix") && 524 (&vdev->pdev == pci_find_device(pci_device_root_bus(&vdev->pdev), 525 0, PCI_DEVFN(0x2, 0)))) { 526 /* 527 * IGD legacy mode requires: 528 * - VBIOS in ROM BAR or file 529 * - VGA IO/MMIO ranges are claimed by IGD 530 * - OpRegion 531 * - Same LPC bridge and Host bridge VID/DID/SVID/SSID as host 532 */ 533 g_autofree struct vfio_region_info *rom = NULL; 534 535 legacy_mode_enabled = true; 536 info_report("IGD legacy mode enabled, " 537 "use x-igd-legacy-mode=off to disable it if unwanted."); 538 539 /* 540 * Most of what we're doing here is to enable the ROM to run, so if 541 * there's no ROM, there's no point in setting up this quirk. 542 * NB. We only seem to get BIOS ROMs, so UEFI VM would need CSM support. 543 */ 544 ret = vfio_device_get_region_info(&vdev->vbasedev, 545 VFIO_PCI_ROM_REGION_INDEX, &rom); 546 if ((ret || !rom->size) && !vdev->pdev.romfile) { 547 error_setg(&err, "Device has no ROM"); 548 goto error; 549 } 550 551 /* 552 * If IGD VGA Disable is clear (expected) and VGA is not already 553 * enabled, try to enable it. Probably shouldn't be using legacy mode 554 * without VGA, but also no point in us enabling VGA if disabled in 555 * hardware. 556 */ 557 if (!(gmch & 0x2) && !vdev->vga && !vfio_populate_vga(vdev, &err)) { 558 error_setg(&err, "Unable to enable VGA access"); 559 goto error; 560 } 561 562 /* Enable OpRegion and LPC bridge quirk */ 563 vdev->features |= VFIO_FEATURE_ENABLE_IGD_OPREGION; 564 vdev->features |= VFIO_FEATURE_ENABLE_IGD_LPC; 565 } else if (vdev->igd_legacy_mode == ON_OFF_AUTO_ON) { 566 error_setg(&err, 567 "Machine is not i440fx, assigned BDF is not 00:02.0, " 568 "or device %04x (gen %d) doesn't support legacy mode", 569 vdev->device_id, gen); 570 goto error; 571 } 572 573 /* Setup OpRegion access */ 574 if ((vdev->features & VFIO_FEATURE_ENABLE_IGD_OPREGION) && 575 !vfio_pci_igd_setup_opregion(vdev, errp)) { 576 goto error; 577 } 578 579 /* Setup LPC bridge / Host bridge PCI IDs */ 580 if ((vdev->features & VFIO_FEATURE_ENABLE_IGD_LPC) && 581 !vfio_pci_igd_setup_lpc_bridge(vdev, errp)) { 582 goto error; 583 } 584 585 /* 586 * ASLS (OpRegion address) is read-only, emulated 587 * It contains HPA, guest firmware need to reprogram it with GPA. 588 */ 589 pci_set_long(vdev->pdev.config + IGD_ASLS, 0); 590 pci_set_long(vdev->pdev.wmask + IGD_ASLS, ~0); 591 pci_set_long(vdev->emulated_config_bits + IGD_ASLS, ~0); 592 593 /* 594 * Allow user to override dsm size using x-igd-gms option, in multiples of 595 * 32MiB. This option should only be used when the desired size cannot be 596 * set from DVMT Pre-Allocated option in host BIOS. 597 */ 598 if (vdev->igd_gms) { 599 if (gen < 8) { 600 if (vdev->igd_gms <= 0x10) { 601 gmch &= ~(IGD_GMCH_GEN6_GMS_MASK << IGD_GMCH_GEN6_GMS_SHIFT); 602 gmch |= vdev->igd_gms << IGD_GMCH_GEN6_GMS_SHIFT; 603 } else { 604 error_report(QERR_INVALID_PARAMETER_VALUE, 605 "x-igd-gms", "0~0x10"); 606 } 607 } else { 608 if (vdev->igd_gms <= 0x40) { 609 gmch &= ~(IGD_GMCH_GEN8_GMS_MASK << IGD_GMCH_GEN8_GMS_SHIFT); 610 gmch |= vdev->igd_gms << IGD_GMCH_GEN8_GMS_SHIFT; 611 } else { 612 error_report(QERR_INVALID_PARAMETER_VALUE, 613 "x-igd-gms", "0~0x40"); 614 } 615 } 616 } 617 618 gms_size = igd_stolen_memory_size(gen, gmch); 619 620 /* 621 * Request reserved memory for stolen memory via fw_cfg. VM firmware 622 * must allocate a 1MB aligned reserved memory region below 4GB with 623 * the requested size (in bytes) for use by the Intel PCI class VGA 624 * device at VM address 00:02.0. The base address of this reserved 625 * memory region must be written to the device BDSM register at PCI 626 * config offset 0x5C. 627 */ 628 bdsm_size = g_malloc(sizeof(*bdsm_size)); 629 *bdsm_size = cpu_to_le64(gms_size); 630 fw_cfg_add_file(fw_cfg_find(), "etc/igd-bdsm-size", 631 bdsm_size, sizeof(*bdsm_size)); 632 633 /* GMCH is read-only, emulated */ 634 pci_set_long(vdev->pdev.config + IGD_GMCH, gmch); 635 pci_set_long(vdev->pdev.wmask + IGD_GMCH, 0); 636 pci_set_long(vdev->emulated_config_bits + IGD_GMCH, ~0); 637 638 /* BDSM is read-write, emulated. The BIOS needs to be able to write it */ 639 if (gen < 11) { 640 pci_set_long(vdev->pdev.config + IGD_BDSM, 0); 641 pci_set_long(vdev->pdev.wmask + IGD_BDSM, ~0); 642 pci_set_long(vdev->emulated_config_bits + IGD_BDSM, ~0); 643 } else { 644 pci_set_quad(vdev->pdev.config + IGD_BDSM_GEN11, 0); 645 pci_set_quad(vdev->pdev.wmask + IGD_BDSM_GEN11, ~0); 646 pci_set_quad(vdev->emulated_config_bits + IGD_BDSM_GEN11, ~0); 647 } 648 649 trace_vfio_pci_igd_bdsm_enabled(vdev->vbasedev.name, (gms_size / MiB)); 650 651 return true; 652 653 error: 654 /* 655 * When legacy mode is implicity enabled, continue on error, 656 * to keep compatibility 657 */ 658 if (legacy_mode_enabled && (vdev->igd_legacy_mode == ON_OFF_AUTO_AUTO)) { 659 error_report_err(err); 660 error_report("IGD legacy mode disabled"); 661 return true; 662 } 663 664 error_propagate(errp, err); 665 return false; 666 } 667 668 /* 669 * KVMGT/GVT-g vGPU exposes an emulated OpRegion. So far, users have to specify 670 * x-igd-opregion=on to enable the access. 671 * TODO: Check VID/DID and enable opregion access automatically 672 */ 673 static bool vfio_pci_kvmgt_config_quirk(VFIOPCIDevice *vdev, Error **errp) 674 { 675 if ((vdev->features & VFIO_FEATURE_ENABLE_IGD_OPREGION) && 676 !vfio_pci_igd_setup_opregion(vdev, errp)) { 677 return false; 678 } 679 680 return true; 681 } 682 683 bool vfio_probe_igd_config_quirk(VFIOPCIDevice *vdev, Error **errp) 684 { 685 /* KVMGT/GVT-g vGPU is exposed as mdev */ 686 if (vdev->vbasedev.mdev) { 687 return vfio_pci_kvmgt_config_quirk(vdev, errp); 688 } 689 690 return vfio_pci_igd_config_quirk(vdev, errp); 691 } 692