1 /* 2 * USB xHCI controller emulation 3 * 4 * Copyright (c) 2011 Securiforest 5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com> 6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2.1 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qemu/timer.h" 24 #include "qemu/log.h" 25 #include "qemu/module.h" 26 #include "qemu/queue.h" 27 #include "migration/vmstate.h" 28 #include "hw/qdev-properties.h" 29 #include "trace.h" 30 #include "qapi/error.h" 31 32 #include "hcd-xhci.h" 33 34 //#define DEBUG_XHCI 35 //#define DEBUG_DATA 36 37 #ifdef DEBUG_XHCI 38 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__) 39 #else 40 #define DPRINTF(...) do {} while (0) 41 #endif 42 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \ 43 __func__, __LINE__, _msg); abort(); } while (0) 44 45 #define TRB_LINK_LIMIT 32 46 #define COMMAND_LIMIT 256 47 #define TRANSFER_LIMIT 256 48 49 #define LEN_CAP 0x40 50 #define LEN_OPER (0x400 + 0x10 * XHCI_MAXPORTS) 51 #define LEN_RUNTIME ((XHCI_MAXINTRS + 1) * 0x20) 52 #define LEN_DOORBELL ((XHCI_MAXSLOTS + 1) * 0x20) 53 54 #define OFF_OPER LEN_CAP 55 #define OFF_RUNTIME 0x1000 56 #define OFF_DOORBELL 0x2000 57 58 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME 59 #error Increase OFF_RUNTIME 60 #endif 61 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL 62 #error Increase OFF_DOORBELL 63 #endif 64 #if (OFF_DOORBELL + LEN_DOORBELL) > XHCI_LEN_REGS 65 # error Increase XHCI_LEN_REGS 66 #endif 67 68 /* bit definitions */ 69 #define USBCMD_RS (1<<0) 70 #define USBCMD_HCRST (1<<1) 71 #define USBCMD_INTE (1<<2) 72 #define USBCMD_HSEE (1<<3) 73 #define USBCMD_LHCRST (1<<7) 74 #define USBCMD_CSS (1<<8) 75 #define USBCMD_CRS (1<<9) 76 #define USBCMD_EWE (1<<10) 77 #define USBCMD_EU3S (1<<11) 78 79 #define USBSTS_HCH (1<<0) 80 #define USBSTS_HSE (1<<2) 81 #define USBSTS_EINT (1<<3) 82 #define USBSTS_PCD (1<<4) 83 #define USBSTS_SSS (1<<8) 84 #define USBSTS_RSS (1<<9) 85 #define USBSTS_SRE (1<<10) 86 #define USBSTS_CNR (1<<11) 87 #define USBSTS_HCE (1<<12) 88 89 90 #define PORTSC_CCS (1<<0) 91 #define PORTSC_PED (1<<1) 92 #define PORTSC_OCA (1<<3) 93 #define PORTSC_PR (1<<4) 94 #define PORTSC_PLS_SHIFT 5 95 #define PORTSC_PLS_MASK 0xf 96 #define PORTSC_PP (1<<9) 97 #define PORTSC_SPEED_SHIFT 10 98 #define PORTSC_SPEED_MASK 0xf 99 #define PORTSC_SPEED_FULL (1<<10) 100 #define PORTSC_SPEED_LOW (2<<10) 101 #define PORTSC_SPEED_HIGH (3<<10) 102 #define PORTSC_SPEED_SUPER (4<<10) 103 #define PORTSC_PIC_SHIFT 14 104 #define PORTSC_PIC_MASK 0x3 105 #define PORTSC_LWS (1<<16) 106 #define PORTSC_CSC (1<<17) 107 #define PORTSC_PEC (1<<18) 108 #define PORTSC_WRC (1<<19) 109 #define PORTSC_OCC (1<<20) 110 #define PORTSC_PRC (1<<21) 111 #define PORTSC_PLC (1<<22) 112 #define PORTSC_CEC (1<<23) 113 #define PORTSC_CAS (1<<24) 114 #define PORTSC_WCE (1<<25) 115 #define PORTSC_WDE (1<<26) 116 #define PORTSC_WOE (1<<27) 117 #define PORTSC_DR (1<<30) 118 #define PORTSC_WPR (1<<31) 119 120 #define CRCR_RCS (1<<0) 121 #define CRCR_CS (1<<1) 122 #define CRCR_CA (1<<2) 123 #define CRCR_CRR (1<<3) 124 125 #define IMAN_IP (1<<0) 126 #define IMAN_IE (1<<1) 127 128 #define ERDP_EHB (1<<3) 129 130 #define TRB_SIZE 16 131 typedef struct XHCITRB { 132 uint64_t parameter; 133 uint32_t status; 134 uint32_t control; 135 dma_addr_t addr; 136 bool ccs; 137 } XHCITRB; 138 139 enum { 140 PLS_U0 = 0, 141 PLS_U1 = 1, 142 PLS_U2 = 2, 143 PLS_U3 = 3, 144 PLS_DISABLED = 4, 145 PLS_RX_DETECT = 5, 146 PLS_INACTIVE = 6, 147 PLS_POLLING = 7, 148 PLS_RECOVERY = 8, 149 PLS_HOT_RESET = 9, 150 PLS_COMPILANCE_MODE = 10, 151 PLS_TEST_MODE = 11, 152 PLS_RESUME = 15, 153 }; 154 155 #define CR_LINK TR_LINK 156 157 #define TRB_C (1<<0) 158 #define TRB_TYPE_SHIFT 10 159 #define TRB_TYPE_MASK 0x3f 160 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK) 161 162 #define TRB_EV_ED (1<<2) 163 164 #define TRB_TR_ENT (1<<1) 165 #define TRB_TR_ISP (1<<2) 166 #define TRB_TR_NS (1<<3) 167 #define TRB_TR_CH (1<<4) 168 #define TRB_TR_IOC (1<<5) 169 #define TRB_TR_IDT (1<<6) 170 #define TRB_TR_TBC_SHIFT 7 171 #define TRB_TR_TBC_MASK 0x3 172 #define TRB_TR_BEI (1<<9) 173 #define TRB_TR_TLBPC_SHIFT 16 174 #define TRB_TR_TLBPC_MASK 0xf 175 #define TRB_TR_FRAMEID_SHIFT 20 176 #define TRB_TR_FRAMEID_MASK 0x7ff 177 #define TRB_TR_SIA (1<<31) 178 179 #define TRB_TR_DIR (1<<16) 180 181 #define TRB_CR_SLOTID_SHIFT 24 182 #define TRB_CR_SLOTID_MASK 0xff 183 #define TRB_CR_EPID_SHIFT 16 184 #define TRB_CR_EPID_MASK 0x1f 185 186 #define TRB_CR_BSR (1<<9) 187 #define TRB_CR_DC (1<<9) 188 189 #define TRB_LK_TC (1<<1) 190 191 #define TRB_INTR_SHIFT 22 192 #define TRB_INTR_MASK 0x3ff 193 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK) 194 195 #define EP_TYPE_MASK 0x7 196 #define EP_TYPE_SHIFT 3 197 198 #define EP_STATE_MASK 0x7 199 #define EP_DISABLED (0<<0) 200 #define EP_RUNNING (1<<0) 201 #define EP_HALTED (2<<0) 202 #define EP_STOPPED (3<<0) 203 #define EP_ERROR (4<<0) 204 205 #define SLOT_STATE_MASK 0x1f 206 #define SLOT_STATE_SHIFT 27 207 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK) 208 #define SLOT_ENABLED 0 209 #define SLOT_DEFAULT 1 210 #define SLOT_ADDRESSED 2 211 #define SLOT_CONFIGURED 3 212 213 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f 214 #define SLOT_CONTEXT_ENTRIES_SHIFT 27 215 216 #define get_field(data, field) \ 217 (((data) >> field##_SHIFT) & field##_MASK) 218 219 #define set_field(data, newval, field) do { \ 220 uint32_t val_ = *data; \ 221 val_ &= ~(field##_MASK << field##_SHIFT); \ 222 val_ |= ((newval) & field##_MASK) << field##_SHIFT; \ 223 *data = val_; \ 224 } while (0) 225 226 typedef enum EPType { 227 ET_INVALID = 0, 228 ET_ISO_OUT, 229 ET_BULK_OUT, 230 ET_INTR_OUT, 231 ET_CONTROL, 232 ET_ISO_IN, 233 ET_BULK_IN, 234 ET_INTR_IN, 235 } EPType; 236 237 typedef struct XHCITransfer { 238 XHCIEPContext *epctx; 239 USBPacket packet; 240 QEMUSGList sgl; 241 bool running_async; 242 bool running_retry; 243 bool complete; 244 bool int_req; 245 unsigned int iso_pkts; 246 unsigned int streamid; 247 bool in_xfer; 248 bool iso_xfer; 249 bool timed_xfer; 250 251 unsigned int trb_count; 252 XHCITRB *trbs; 253 254 TRBCCode status; 255 256 unsigned int pkts; 257 unsigned int pktsize; 258 unsigned int cur_pkt; 259 260 uint64_t mfindex_kick; 261 262 QTAILQ_ENTRY(XHCITransfer) next; 263 } XHCITransfer; 264 265 struct XHCIStreamContext { 266 dma_addr_t pctx; 267 unsigned int sct; 268 XHCIRing ring; 269 }; 270 271 struct XHCIEPContext { 272 XHCIState *xhci; 273 unsigned int slotid; 274 unsigned int epid; 275 276 XHCIRing ring; 277 uint32_t xfer_count; 278 QTAILQ_HEAD(, XHCITransfer) transfers; 279 XHCITransfer *retry; 280 EPType type; 281 dma_addr_t pctx; 282 unsigned int max_psize; 283 uint32_t state; 284 uint32_t kick_active; 285 286 /* streams */ 287 unsigned int max_pstreams; 288 bool lsa; 289 unsigned int nr_pstreams; 290 XHCIStreamContext *pstreams; 291 292 /* iso xfer scheduling */ 293 unsigned int interval; 294 int64_t mfindex_last; 295 QEMUTimer *kick_timer; 296 }; 297 298 typedef struct XHCIEvRingSeg { 299 uint32_t addr_low; 300 uint32_t addr_high; 301 uint32_t size; 302 uint32_t rsvd; 303 } XHCIEvRingSeg; 304 305 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 306 unsigned int epid, unsigned int streamid); 307 static void xhci_kick_epctx(XHCIEPContext *epctx, unsigned int streamid); 308 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 309 unsigned int epid); 310 static void xhci_xfer_report(XHCITransfer *xfer); 311 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v); 312 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v); 313 static USBEndpoint *xhci_epid_to_usbep(XHCIEPContext *epctx); 314 315 static const char *TRBType_names[] = { 316 [TRB_RESERVED] = "TRB_RESERVED", 317 [TR_NORMAL] = "TR_NORMAL", 318 [TR_SETUP] = "TR_SETUP", 319 [TR_DATA] = "TR_DATA", 320 [TR_STATUS] = "TR_STATUS", 321 [TR_ISOCH] = "TR_ISOCH", 322 [TR_LINK] = "TR_LINK", 323 [TR_EVDATA] = "TR_EVDATA", 324 [TR_NOOP] = "TR_NOOP", 325 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT", 326 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT", 327 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE", 328 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT", 329 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT", 330 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT", 331 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT", 332 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE", 333 [CR_RESET_DEVICE] = "CR_RESET_DEVICE", 334 [CR_FORCE_EVENT] = "CR_FORCE_EVENT", 335 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW", 336 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE", 337 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH", 338 [CR_FORCE_HEADER] = "CR_FORCE_HEADER", 339 [CR_NOOP] = "CR_NOOP", 340 [ER_TRANSFER] = "ER_TRANSFER", 341 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE", 342 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE", 343 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST", 344 [ER_DOORBELL] = "ER_DOORBELL", 345 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER", 346 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION", 347 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP", 348 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION", 349 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE", 350 }; 351 352 static const char *TRBCCode_names[] = { 353 [CC_INVALID] = "CC_INVALID", 354 [CC_SUCCESS] = "CC_SUCCESS", 355 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR", 356 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED", 357 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR", 358 [CC_TRB_ERROR] = "CC_TRB_ERROR", 359 [CC_STALL_ERROR] = "CC_STALL_ERROR", 360 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR", 361 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR", 362 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR", 363 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR", 364 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR", 365 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR", 366 [CC_SHORT_PACKET] = "CC_SHORT_PACKET", 367 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN", 368 [CC_RING_OVERRUN] = "CC_RING_OVERRUN", 369 [CC_VF_ER_FULL] = "CC_VF_ER_FULL", 370 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR", 371 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN", 372 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR", 373 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR", 374 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR", 375 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR", 376 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR", 377 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED", 378 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED", 379 [CC_STOPPED] = "CC_STOPPED", 380 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID", 381 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR] 382 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR", 383 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN", 384 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR", 385 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR", 386 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR", 387 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR", 388 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR", 389 }; 390 391 static const char *ep_state_names[] = { 392 [EP_DISABLED] = "disabled", 393 [EP_RUNNING] = "running", 394 [EP_HALTED] = "halted", 395 [EP_STOPPED] = "stopped", 396 [EP_ERROR] = "error", 397 }; 398 399 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen) 400 { 401 if (index >= llen || list[index] == NULL) { 402 return "???"; 403 } 404 return list[index]; 405 } 406 407 static const char *trb_name(XHCITRB *trb) 408 { 409 return lookup_name(TRB_TYPE(*trb), TRBType_names, 410 ARRAY_SIZE(TRBType_names)); 411 } 412 413 static const char *event_name(XHCIEvent *event) 414 { 415 return lookup_name(event->ccode, TRBCCode_names, 416 ARRAY_SIZE(TRBCCode_names)); 417 } 418 419 static const char *ep_state_name(uint32_t state) 420 { 421 return lookup_name(state, ep_state_names, 422 ARRAY_SIZE(ep_state_names)); 423 } 424 425 bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit) 426 { 427 return xhci->flags & (1 << bit); 428 } 429 430 void xhci_set_flag(XHCIState *xhci, enum xhci_flags bit) 431 { 432 xhci->flags |= (1 << bit); 433 } 434 435 static uint64_t xhci_mfindex_get(XHCIState *xhci) 436 { 437 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 438 return (now - xhci->mfindex_start) / 125000; 439 } 440 441 static void xhci_mfwrap_update(XHCIState *xhci) 442 { 443 const uint32_t bits = USBCMD_RS | USBCMD_EWE; 444 uint32_t mfindex, left; 445 int64_t now; 446 447 if ((xhci->usbcmd & bits) == bits) { 448 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 449 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff; 450 left = 0x4000 - mfindex; 451 timer_mod(xhci->mfwrap_timer, now + left * 125000); 452 } else { 453 timer_del(xhci->mfwrap_timer); 454 } 455 } 456 457 static void xhci_mfwrap_timer(void *opaque) 458 { 459 XHCIState *xhci = opaque; 460 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS }; 461 462 xhci_event(xhci, &wrap, 0); 463 xhci_mfwrap_update(xhci); 464 } 465 466 static void xhci_die(XHCIState *xhci) 467 { 468 xhci->usbsts |= USBSTS_HCE; 469 DPRINTF("xhci: asserted controller error\n"); 470 } 471 472 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high) 473 { 474 if (sizeof(dma_addr_t) == 4) { 475 return low; 476 } else { 477 return low | (((dma_addr_t)high << 16) << 16); 478 } 479 } 480 481 static inline dma_addr_t xhci_mask64(uint64_t addr) 482 { 483 if (sizeof(dma_addr_t) == 4) { 484 return addr & 0xffffffff; 485 } else { 486 return addr; 487 } 488 } 489 490 static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr, 491 uint32_t *buf, size_t len) 492 { 493 int i; 494 495 assert((len % sizeof(uint32_t)) == 0); 496 497 if (dma_memory_read(xhci->as, addr, buf, len, 498 MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) { 499 qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory access failed!\n", 500 __func__); 501 memset(buf, 0xff, len); 502 xhci_die(xhci); 503 return; 504 } 505 506 for (i = 0; i < (len / sizeof(uint32_t)); i++) { 507 buf[i] = le32_to_cpu(buf[i]); 508 } 509 } 510 511 static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr, 512 const uint32_t *buf, size_t len) 513 { 514 int i; 515 uint32_t tmp[5]; 516 uint32_t n = len / sizeof(uint32_t); 517 518 assert((len % sizeof(uint32_t)) == 0); 519 assert(n <= ARRAY_SIZE(tmp)); 520 521 for (i = 0; i < n; i++) { 522 tmp[i] = cpu_to_le32(buf[i]); 523 } 524 if (dma_memory_write(xhci->as, addr, tmp, len, 525 MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) { 526 qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory access failed!\n", 527 __func__); 528 xhci_die(xhci); 529 return; 530 } 531 } 532 533 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport) 534 { 535 int index; 536 537 if (!uport->dev) { 538 return NULL; 539 } 540 switch (uport->dev->speed) { 541 case USB_SPEED_LOW: 542 case USB_SPEED_FULL: 543 case USB_SPEED_HIGH: 544 index = uport->index + xhci->numports_3; 545 break; 546 case USB_SPEED_SUPER: 547 index = uport->index; 548 break; 549 default: 550 return NULL; 551 } 552 return &xhci->ports[index]; 553 } 554 555 static void xhci_intr_update(XHCIState *xhci, int v) 556 { 557 int level = 0; 558 559 if (v == 0) { 560 if (xhci->intr[0].iman & IMAN_IP && 561 xhci->intr[0].iman & IMAN_IE && 562 xhci->usbcmd & USBCMD_INTE) { 563 level = 1; 564 } 565 if (xhci->intr_raise) { 566 if (xhci->intr_raise(xhci, 0, level)) { 567 xhci->intr[0].iman &= ~IMAN_IP; 568 } 569 } 570 } 571 if (xhci->intr_update) { 572 xhci->intr_update(xhci, v, 573 xhci->intr[v].iman & IMAN_IE); 574 } 575 } 576 577 static void xhci_intr_raise(XHCIState *xhci, int v) 578 { 579 bool pending = (xhci->intr[v].erdp_low & ERDP_EHB); 580 581 xhci->intr[v].erdp_low |= ERDP_EHB; 582 xhci->intr[v].iman |= IMAN_IP; 583 xhci->usbsts |= USBSTS_EINT; 584 585 if (pending) { 586 return; 587 } 588 if (!(xhci->intr[v].iman & IMAN_IE)) { 589 return; 590 } 591 592 if (!(xhci->usbcmd & USBCMD_INTE)) { 593 return; 594 } 595 if (xhci->intr_raise) { 596 if (xhci->intr_raise(xhci, v, true)) { 597 xhci->intr[v].iman &= ~IMAN_IP; 598 } 599 } 600 } 601 602 static inline int xhci_running(XHCIState *xhci) 603 { 604 return !(xhci->usbsts & USBSTS_HCH); 605 } 606 607 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v) 608 { 609 XHCIInterrupter *intr = &xhci->intr[v]; 610 XHCITRB ev_trb; 611 dma_addr_t addr; 612 613 ev_trb.parameter = cpu_to_le64(event->ptr); 614 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24)); 615 ev_trb.control = (event->slotid << 24) | (event->epid << 16) | 616 event->flags | (event->type << TRB_TYPE_SHIFT); 617 if (intr->er_pcs) { 618 ev_trb.control |= TRB_C; 619 } 620 ev_trb.control = cpu_to_le32(ev_trb.control); 621 622 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb), 623 event_name(event), ev_trb.parameter, 624 ev_trb.status, ev_trb.control); 625 626 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx; 627 if (dma_memory_write(xhci->as, addr, &ev_trb, TRB_SIZE, 628 MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) { 629 qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory access failed!\n", 630 __func__); 631 xhci_die(xhci); 632 } 633 634 intr->er_ep_idx++; 635 if (intr->er_ep_idx >= intr->er_size) { 636 intr->er_ep_idx = 0; 637 intr->er_pcs = !intr->er_pcs; 638 } 639 } 640 641 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v) 642 { 643 XHCIInterrupter *intr; 644 dma_addr_t erdp; 645 unsigned int dp_idx; 646 647 if (xhci->numintrs == 1 || 648 (xhci->intr_mapping_supported && !xhci->intr_mapping_supported(xhci))) { 649 v = 0; 650 } 651 652 if (v >= xhci->numintrs) { 653 DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs); 654 return; 655 } 656 intr = &xhci->intr[v]; 657 658 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 659 if (erdp < intr->er_start || 660 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 661 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 662 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 663 v, intr->er_start, intr->er_size); 664 xhci_die(xhci); 665 return; 666 } 667 668 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 669 assert(dp_idx < intr->er_size); 670 671 if ((intr->er_ep_idx + 2) % intr->er_size == dp_idx) { 672 DPRINTF("xhci: ER %d full, send ring full error\n", v); 673 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 674 xhci_write_event(xhci, &full, v); 675 } else if ((intr->er_ep_idx + 1) % intr->er_size == dp_idx) { 676 DPRINTF("xhci: ER %d full, drop event\n", v); 677 } else { 678 xhci_write_event(xhci, event, v); 679 } 680 681 xhci_intr_raise(xhci, v); 682 } 683 684 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring, 685 dma_addr_t base) 686 { 687 ring->dequeue = base; 688 ring->ccs = 1; 689 } 690 691 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb, 692 dma_addr_t *addr) 693 { 694 uint32_t link_cnt = 0; 695 696 while (1) { 697 TRBType type; 698 if (dma_memory_read(xhci->as, ring->dequeue, trb, TRB_SIZE, 699 MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) { 700 qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory access failed!\n", 701 __func__); 702 return 0; 703 } 704 trb->addr = ring->dequeue; 705 trb->ccs = ring->ccs; 706 le64_to_cpus(&trb->parameter); 707 le32_to_cpus(&trb->status); 708 le32_to_cpus(&trb->control); 709 710 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb), 711 trb->parameter, trb->status, trb->control); 712 713 if ((trb->control & TRB_C) != ring->ccs) { 714 return 0; 715 } 716 717 type = TRB_TYPE(*trb); 718 719 if (type != TR_LINK) { 720 if (addr) { 721 *addr = ring->dequeue; 722 } 723 ring->dequeue += TRB_SIZE; 724 return type; 725 } else { 726 if (++link_cnt > TRB_LINK_LIMIT) { 727 trace_usb_xhci_enforced_limit("trb-link"); 728 return 0; 729 } 730 ring->dequeue = xhci_mask64(trb->parameter); 731 if (trb->control & TRB_LK_TC) { 732 ring->ccs = !ring->ccs; 733 } 734 } 735 } 736 } 737 738 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring) 739 { 740 XHCITRB trb; 741 int length = 0; 742 dma_addr_t dequeue = ring->dequeue; 743 bool ccs = ring->ccs; 744 /* hack to bundle together the two/three TDs that make a setup transfer */ 745 bool control_td_set = 0; 746 uint32_t link_cnt = 0; 747 748 do { 749 TRBType type; 750 if (dma_memory_read(xhci->as, dequeue, &trb, TRB_SIZE, 751 MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) { 752 qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory access failed!\n", 753 __func__); 754 return -1; 755 } 756 le64_to_cpus(&trb.parameter); 757 le32_to_cpus(&trb.status); 758 le32_to_cpus(&trb.control); 759 760 if ((trb.control & TRB_C) != ccs) { 761 return -length; 762 } 763 764 type = TRB_TYPE(trb); 765 766 if (type == TR_LINK) { 767 if (++link_cnt > TRB_LINK_LIMIT) { 768 return -length; 769 } 770 dequeue = xhci_mask64(trb.parameter); 771 if (trb.control & TRB_LK_TC) { 772 ccs = !ccs; 773 } 774 continue; 775 } 776 777 length += 1; 778 dequeue += TRB_SIZE; 779 780 if (type == TR_SETUP) { 781 control_td_set = 1; 782 } else if (type == TR_STATUS) { 783 control_td_set = 0; 784 } 785 786 if (!control_td_set && !(trb.control & TRB_TR_CH)) { 787 return length; 788 } 789 790 /* 791 * According to the xHCI spec, Transfer Ring segments should have 792 * a maximum size of 64 kB (see chapter "6 Data Structures") 793 */ 794 } while (length < TRB_LINK_LIMIT * 65536 / TRB_SIZE); 795 796 qemu_log_mask(LOG_GUEST_ERROR, "%s: exceeded maximum transfer ring size!\n", 797 __func__); 798 799 return -1; 800 } 801 802 static void xhci_er_reset(XHCIState *xhci, int v) 803 { 804 XHCIInterrupter *intr = &xhci->intr[v]; 805 XHCIEvRingSeg seg; 806 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high); 807 808 if (intr->erstsz == 0 || erstba == 0) { 809 /* disabled */ 810 intr->er_start = 0; 811 intr->er_size = 0; 812 return; 813 } 814 /* cache the (sole) event ring segment location */ 815 if (intr->erstsz != 1) { 816 DPRINTF("xhci: invalid value for ERSTSZ: %d\n", intr->erstsz); 817 xhci_die(xhci); 818 return; 819 } 820 if (dma_memory_read(xhci->as, erstba, &seg, sizeof(seg), 821 MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) { 822 qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory access failed!\n", 823 __func__); 824 xhci_die(xhci); 825 return; 826 } 827 828 le32_to_cpus(&seg.addr_low); 829 le32_to_cpus(&seg.addr_high); 830 le32_to_cpus(&seg.size); 831 if (seg.size < 16 || seg.size > 4096) { 832 DPRINTF("xhci: invalid value for segment size: %d\n", seg.size); 833 xhci_die(xhci); 834 return; 835 } 836 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high); 837 intr->er_size = seg.size; 838 839 intr->er_ep_idx = 0; 840 intr->er_pcs = 1; 841 842 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n", 843 v, intr->er_start, intr->er_size); 844 } 845 846 static void xhci_run(XHCIState *xhci) 847 { 848 trace_usb_xhci_run(); 849 xhci->usbsts &= ~USBSTS_HCH; 850 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 851 } 852 853 static void xhci_stop(XHCIState *xhci) 854 { 855 trace_usb_xhci_stop(); 856 xhci->usbsts |= USBSTS_HCH; 857 xhci->crcr_low &= ~CRCR_CRR; 858 } 859 860 static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count, 861 dma_addr_t base) 862 { 863 XHCIStreamContext *stctx; 864 unsigned int i; 865 866 stctx = g_new0(XHCIStreamContext, count); 867 for (i = 0; i < count; i++) { 868 stctx[i].pctx = base + i * 16; 869 stctx[i].sct = -1; 870 } 871 return stctx; 872 } 873 874 static void xhci_reset_streams(XHCIEPContext *epctx) 875 { 876 unsigned int i; 877 878 for (i = 0; i < epctx->nr_pstreams; i++) { 879 epctx->pstreams[i].sct = -1; 880 } 881 } 882 883 static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base) 884 { 885 assert(epctx->pstreams == NULL); 886 epctx->nr_pstreams = 2 << epctx->max_pstreams; 887 epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base); 888 } 889 890 static void xhci_free_streams(XHCIEPContext *epctx) 891 { 892 assert(epctx->pstreams != NULL); 893 894 g_free(epctx->pstreams); 895 epctx->pstreams = NULL; 896 epctx->nr_pstreams = 0; 897 } 898 899 static int xhci_epmask_to_eps_with_streams(XHCIState *xhci, 900 unsigned int slotid, 901 uint32_t epmask, 902 XHCIEPContext **epctxs, 903 USBEndpoint **eps) 904 { 905 XHCISlot *slot; 906 XHCIEPContext *epctx; 907 USBEndpoint *ep; 908 int i, j; 909 910 assert(slotid >= 1 && slotid <= xhci->numslots); 911 912 slot = &xhci->slots[slotid - 1]; 913 914 for (i = 2, j = 0; i <= 31; i++) { 915 if (!(epmask & (1u << i))) { 916 continue; 917 } 918 919 epctx = slot->eps[i - 1]; 920 ep = xhci_epid_to_usbep(epctx); 921 if (!epctx || !epctx->nr_pstreams || !ep) { 922 continue; 923 } 924 925 if (epctxs) { 926 epctxs[j] = epctx; 927 } 928 eps[j++] = ep; 929 } 930 return j; 931 } 932 933 static void xhci_free_device_streams(XHCIState *xhci, unsigned int slotid, 934 uint32_t epmask) 935 { 936 USBEndpoint *eps[30]; 937 int nr_eps; 938 939 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, NULL, eps); 940 if (nr_eps) { 941 usb_device_free_streams(eps[0]->dev, eps, nr_eps); 942 } 943 } 944 945 static TRBCCode xhci_alloc_device_streams(XHCIState *xhci, unsigned int slotid, 946 uint32_t epmask) 947 { 948 XHCIEPContext *epctxs[30]; 949 USBEndpoint *eps[30]; 950 int i, r, nr_eps, req_nr_streams, dev_max_streams; 951 952 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, epctxs, 953 eps); 954 if (nr_eps == 0) { 955 return CC_SUCCESS; 956 } 957 958 req_nr_streams = epctxs[0]->nr_pstreams; 959 dev_max_streams = eps[0]->max_streams; 960 961 for (i = 1; i < nr_eps; i++) { 962 /* 963 * HdG: I don't expect these to ever trigger, but if they do we need 964 * to come up with another solution, ie group identical endpoints 965 * together and make an usb_device_alloc_streams call per group. 966 */ 967 if (epctxs[i]->nr_pstreams != req_nr_streams) { 968 FIXME("guest streams config not identical for all eps"); 969 return CC_RESOURCE_ERROR; 970 } 971 if (eps[i]->max_streams != dev_max_streams) { 972 FIXME("device streams config not identical for all eps"); 973 return CC_RESOURCE_ERROR; 974 } 975 } 976 977 /* 978 * max-streams in both the device descriptor and in the controller is a 979 * power of 2. But stream id 0 is reserved, so if a device can do up to 4 980 * streams the guest will ask for 5 rounded up to the next power of 2 which 981 * becomes 8. For emulated devices usb_device_alloc_streams is a nop. 982 * 983 * For redirected devices however this is an issue, as there we must ask 984 * the real xhci controller to alloc streams, and the host driver for the 985 * real xhci controller will likely disallow allocating more streams then 986 * the device can handle. 987 * 988 * So we limit the requested nr_streams to the maximum number the device 989 * can handle. 990 */ 991 if (req_nr_streams > dev_max_streams) { 992 req_nr_streams = dev_max_streams; 993 } 994 995 r = usb_device_alloc_streams(eps[0]->dev, eps, nr_eps, req_nr_streams); 996 if (r != 0) { 997 DPRINTF("xhci: alloc streams failed\n"); 998 return CC_RESOURCE_ERROR; 999 } 1000 1001 return CC_SUCCESS; 1002 } 1003 1004 static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx, 1005 unsigned int streamid, 1006 uint32_t *cc_error) 1007 { 1008 XHCIStreamContext *sctx; 1009 dma_addr_t base; 1010 uint32_t ctx[2], sct; 1011 1012 assert(streamid != 0); 1013 if (epctx->lsa) { 1014 if (streamid >= epctx->nr_pstreams) { 1015 *cc_error = CC_INVALID_STREAM_ID_ERROR; 1016 return NULL; 1017 } 1018 sctx = epctx->pstreams + streamid; 1019 } else { 1020 fprintf(stderr, "xhci: FIXME: secondary streams not implemented yet"); 1021 *cc_error = CC_INVALID_STREAM_TYPE_ERROR; 1022 return NULL; 1023 } 1024 1025 if (sctx->sct == -1) { 1026 xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx)); 1027 sct = (ctx[0] >> 1) & 0x07; 1028 if (epctx->lsa && sct != 1) { 1029 *cc_error = CC_INVALID_STREAM_TYPE_ERROR; 1030 return NULL; 1031 } 1032 sctx->sct = sct; 1033 base = xhci_addr64(ctx[0] & ~0xf, ctx[1]); 1034 xhci_ring_init(epctx->xhci, &sctx->ring, base); 1035 } 1036 return sctx; 1037 } 1038 1039 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx, 1040 XHCIStreamContext *sctx, uint32_t state) 1041 { 1042 XHCIRing *ring = NULL; 1043 uint32_t ctx[5]; 1044 uint32_t ctx2[2]; 1045 1046 xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); 1047 ctx[0] &= ~EP_STATE_MASK; 1048 ctx[0] |= state; 1049 1050 /* update ring dequeue ptr */ 1051 if (epctx->nr_pstreams) { 1052 if (sctx != NULL) { 1053 ring = &sctx->ring; 1054 xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); 1055 ctx2[0] &= 0xe; 1056 ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs; 1057 ctx2[1] = (sctx->ring.dequeue >> 16) >> 16; 1058 xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); 1059 } 1060 } else { 1061 ring = &epctx->ring; 1062 } 1063 if (ring) { 1064 ctx[2] = ring->dequeue | ring->ccs; 1065 ctx[3] = (ring->dequeue >> 16) >> 16; 1066 1067 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n", 1068 epctx->pctx, state, ctx[3], ctx[2]); 1069 } 1070 1071 xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); 1072 if (epctx->state != state) { 1073 trace_usb_xhci_ep_state(epctx->slotid, epctx->epid, 1074 ep_state_name(epctx->state), 1075 ep_state_name(state)); 1076 } 1077 epctx->state = state; 1078 } 1079 1080 static void xhci_ep_kick_timer(void *opaque) 1081 { 1082 XHCIEPContext *epctx = opaque; 1083 xhci_kick_epctx(epctx, 0); 1084 } 1085 1086 static XHCIEPContext *xhci_alloc_epctx(XHCIState *xhci, 1087 unsigned int slotid, 1088 unsigned int epid) 1089 { 1090 XHCIEPContext *epctx; 1091 1092 epctx = g_new0(XHCIEPContext, 1); 1093 epctx->xhci = xhci; 1094 epctx->slotid = slotid; 1095 epctx->epid = epid; 1096 1097 QTAILQ_INIT(&epctx->transfers); 1098 epctx->kick_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_ep_kick_timer, epctx); 1099 1100 return epctx; 1101 } 1102 1103 static void xhci_init_epctx(XHCIEPContext *epctx, 1104 dma_addr_t pctx, uint32_t *ctx) 1105 { 1106 dma_addr_t dequeue; 1107 1108 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]); 1109 1110 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK; 1111 epctx->pctx = pctx; 1112 epctx->max_psize = ctx[1]>>16; 1113 epctx->max_psize *= 1+((ctx[1]>>8)&0xff); 1114 epctx->max_pstreams = (ctx[0] >> 10) & epctx->xhci->max_pstreams_mask; 1115 epctx->lsa = (ctx[0] >> 15) & 1; 1116 if (epctx->max_pstreams) { 1117 xhci_alloc_streams(epctx, dequeue); 1118 } else { 1119 xhci_ring_init(epctx->xhci, &epctx->ring, dequeue); 1120 epctx->ring.ccs = ctx[2] & 1; 1121 } 1122 1123 epctx->interval = 1 << ((ctx[0] >> 16) & 0xff); 1124 } 1125 1126 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid, 1127 unsigned int epid, dma_addr_t pctx, 1128 uint32_t *ctx) 1129 { 1130 XHCISlot *slot; 1131 XHCIEPContext *epctx; 1132 1133 trace_usb_xhci_ep_enable(slotid, epid); 1134 assert(slotid >= 1 && slotid <= xhci->numslots); 1135 assert(epid >= 1 && epid <= 31); 1136 1137 slot = &xhci->slots[slotid-1]; 1138 if (slot->eps[epid-1]) { 1139 xhci_disable_ep(xhci, slotid, epid); 1140 } 1141 1142 epctx = xhci_alloc_epctx(xhci, slotid, epid); 1143 slot->eps[epid-1] = epctx; 1144 xhci_init_epctx(epctx, pctx, ctx); 1145 1146 DPRINTF("xhci: endpoint %d.%d type is %d, max transaction (burst) " 1147 "size is %d\n", epid/2, epid%2, epctx->type, epctx->max_psize); 1148 1149 epctx->mfindex_last = 0; 1150 1151 epctx->state = EP_RUNNING; 1152 ctx[0] &= ~EP_STATE_MASK; 1153 ctx[0] |= EP_RUNNING; 1154 1155 return CC_SUCCESS; 1156 } 1157 1158 static XHCITransfer *xhci_ep_alloc_xfer(XHCIEPContext *epctx, 1159 uint32_t length) 1160 { 1161 uint32_t limit = epctx->nr_pstreams + 16; 1162 XHCITransfer *xfer; 1163 1164 if (epctx->xfer_count >= limit) { 1165 return NULL; 1166 } 1167 1168 xfer = g_new0(XHCITransfer, 1); 1169 xfer->epctx = epctx; 1170 xfer->trbs = g_new(XHCITRB, length); 1171 xfer->trb_count = length; 1172 usb_packet_init(&xfer->packet); 1173 1174 QTAILQ_INSERT_TAIL(&epctx->transfers, xfer, next); 1175 epctx->xfer_count++; 1176 1177 return xfer; 1178 } 1179 1180 static void xhci_ep_free_xfer(XHCITransfer *xfer) 1181 { 1182 QTAILQ_REMOVE(&xfer->epctx->transfers, xfer, next); 1183 xfer->epctx->xfer_count--; 1184 1185 usb_packet_cleanup(&xfer->packet); 1186 g_free(xfer->trbs); 1187 g_free(xfer); 1188 } 1189 1190 static void xhci_xfer_unmap(XHCITransfer *xfer) 1191 { 1192 usb_packet_unmap(&xfer->packet, &xfer->sgl); 1193 qemu_sglist_destroy(&xfer->sgl); 1194 } 1195 1196 static int xhci_ep_nuke_one_xfer(XHCITransfer *t, TRBCCode report) 1197 { 1198 int killed = 0; 1199 1200 if (report && (t->running_async || t->running_retry)) { 1201 t->status = report; 1202 xhci_xfer_report(t); 1203 } 1204 1205 if (t->running_async) { 1206 usb_cancel_packet(&t->packet); 1207 xhci_xfer_unmap(t); 1208 t->running_async = 0; 1209 killed = 1; 1210 } 1211 if (t->running_retry) { 1212 if (t->epctx) { 1213 t->epctx->retry = NULL; 1214 timer_del(t->epctx->kick_timer); 1215 } 1216 t->running_retry = 0; 1217 killed = 1; 1218 } 1219 g_free(t->trbs); 1220 1221 t->trbs = NULL; 1222 t->trb_count = 0; 1223 1224 return killed; 1225 } 1226 1227 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid, 1228 unsigned int epid, TRBCCode report) 1229 { 1230 XHCISlot *slot; 1231 XHCIEPContext *epctx; 1232 XHCITransfer *xfer; 1233 int killed = 0; 1234 USBEndpoint *ep = NULL; 1235 assert(slotid >= 1 && slotid <= xhci->numslots); 1236 assert(epid >= 1 && epid <= 31); 1237 1238 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid); 1239 1240 slot = &xhci->slots[slotid-1]; 1241 1242 if (!slot->eps[epid-1]) { 1243 return 0; 1244 } 1245 1246 epctx = slot->eps[epid-1]; 1247 1248 for (;;) { 1249 xfer = QTAILQ_FIRST(&epctx->transfers); 1250 if (xfer == NULL) { 1251 break; 1252 } 1253 killed += xhci_ep_nuke_one_xfer(xfer, report); 1254 if (killed) { 1255 report = 0; /* Only report once */ 1256 } 1257 xhci_ep_free_xfer(xfer); 1258 } 1259 1260 ep = xhci_epid_to_usbep(epctx); 1261 if (ep) { 1262 usb_device_ep_stopped(ep->dev, ep); 1263 } 1264 return killed; 1265 } 1266 1267 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 1268 unsigned int epid) 1269 { 1270 XHCISlot *slot; 1271 XHCIEPContext *epctx; 1272 1273 trace_usb_xhci_ep_disable(slotid, epid); 1274 assert(slotid >= 1 && slotid <= xhci->numslots); 1275 assert(epid >= 1 && epid <= 31); 1276 1277 slot = &xhci->slots[slotid-1]; 1278 1279 if (!slot->eps[epid-1]) { 1280 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid); 1281 return CC_SUCCESS; 1282 } 1283 1284 xhci_ep_nuke_xfers(xhci, slotid, epid, 0); 1285 1286 epctx = slot->eps[epid-1]; 1287 1288 if (epctx->nr_pstreams) { 1289 xhci_free_streams(epctx); 1290 } 1291 1292 /* only touch guest RAM if we're not resetting the HC */ 1293 if (xhci->dcbaap_low || xhci->dcbaap_high) { 1294 xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED); 1295 } 1296 1297 timer_free(epctx->kick_timer); 1298 g_free(epctx); 1299 slot->eps[epid-1] = NULL; 1300 1301 return CC_SUCCESS; 1302 } 1303 1304 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid, 1305 unsigned int epid) 1306 { 1307 XHCISlot *slot; 1308 XHCIEPContext *epctx; 1309 1310 trace_usb_xhci_ep_stop(slotid, epid); 1311 assert(slotid >= 1 && slotid <= xhci->numslots); 1312 1313 if (epid < 1 || epid > 31) { 1314 DPRINTF("xhci: bad ep %d\n", epid); 1315 return CC_TRB_ERROR; 1316 } 1317 1318 slot = &xhci->slots[slotid-1]; 1319 1320 if (!slot->eps[epid-1]) { 1321 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1322 return CC_EP_NOT_ENABLED_ERROR; 1323 } 1324 1325 if (xhci_ep_nuke_xfers(xhci, slotid, epid, CC_STOPPED) > 0) { 1326 DPRINTF("xhci: FIXME: endpoint stopped w/ xfers running, " 1327 "data might be lost\n"); 1328 } 1329 1330 epctx = slot->eps[epid-1]; 1331 1332 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); 1333 1334 if (epctx->nr_pstreams) { 1335 xhci_reset_streams(epctx); 1336 } 1337 1338 return CC_SUCCESS; 1339 } 1340 1341 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid, 1342 unsigned int epid) 1343 { 1344 XHCISlot *slot; 1345 XHCIEPContext *epctx; 1346 1347 trace_usb_xhci_ep_reset(slotid, epid); 1348 assert(slotid >= 1 && slotid <= xhci->numslots); 1349 1350 if (epid < 1 || epid > 31) { 1351 DPRINTF("xhci: bad ep %d\n", epid); 1352 return CC_TRB_ERROR; 1353 } 1354 1355 slot = &xhci->slots[slotid-1]; 1356 1357 if (!slot->eps[epid-1]) { 1358 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1359 return CC_EP_NOT_ENABLED_ERROR; 1360 } 1361 1362 epctx = slot->eps[epid-1]; 1363 1364 if (epctx->state != EP_HALTED) { 1365 DPRINTF("xhci: reset EP while EP %d not halted (%d)\n", 1366 epid, epctx->state); 1367 return CC_CONTEXT_STATE_ERROR; 1368 } 1369 1370 if (xhci_ep_nuke_xfers(xhci, slotid, epid, 0) > 0) { 1371 DPRINTF("xhci: FIXME: endpoint reset w/ xfers running, " 1372 "data might be lost\n"); 1373 } 1374 1375 if (!xhci->slots[slotid-1].uport || 1376 !xhci->slots[slotid-1].uport->dev || 1377 !xhci->slots[slotid-1].uport->dev->attached) { 1378 return CC_USB_TRANSACTION_ERROR; 1379 } 1380 1381 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); 1382 1383 if (epctx->nr_pstreams) { 1384 xhci_reset_streams(epctx); 1385 } 1386 1387 return CC_SUCCESS; 1388 } 1389 1390 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid, 1391 unsigned int epid, unsigned int streamid, 1392 uint64_t pdequeue) 1393 { 1394 XHCISlot *slot; 1395 XHCIEPContext *epctx; 1396 XHCIStreamContext *sctx; 1397 dma_addr_t dequeue; 1398 1399 assert(slotid >= 1 && slotid <= xhci->numslots); 1400 1401 if (epid < 1 || epid > 31) { 1402 DPRINTF("xhci: bad ep %d\n", epid); 1403 return CC_TRB_ERROR; 1404 } 1405 1406 trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue); 1407 dequeue = xhci_mask64(pdequeue); 1408 1409 slot = &xhci->slots[slotid-1]; 1410 1411 if (!slot->eps[epid-1]) { 1412 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1413 return CC_EP_NOT_ENABLED_ERROR; 1414 } 1415 1416 epctx = slot->eps[epid-1]; 1417 1418 if (epctx->state != EP_STOPPED) { 1419 DPRINTF("xhci: set EP dequeue pointer while EP %d not stopped\n", epid); 1420 return CC_CONTEXT_STATE_ERROR; 1421 } 1422 1423 if (epctx->nr_pstreams) { 1424 uint32_t err; 1425 sctx = xhci_find_stream(epctx, streamid, &err); 1426 if (sctx == NULL) { 1427 return err; 1428 } 1429 xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf); 1430 sctx->ring.ccs = dequeue & 1; 1431 } else { 1432 sctx = NULL; 1433 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF); 1434 epctx->ring.ccs = dequeue & 1; 1435 } 1436 1437 xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED); 1438 1439 return CC_SUCCESS; 1440 } 1441 1442 static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer) 1443 { 1444 XHCIState *xhci = xfer->epctx->xhci; 1445 int i; 1446 1447 xfer->int_req = false; 1448 qemu_sglist_init(&xfer->sgl, DEVICE(xhci), xfer->trb_count, xhci->as); 1449 for (i = 0; i < xfer->trb_count; i++) { 1450 XHCITRB *trb = &xfer->trbs[i]; 1451 dma_addr_t addr; 1452 unsigned int chunk = 0; 1453 1454 if (trb->control & TRB_TR_IOC) { 1455 xfer->int_req = true; 1456 } 1457 1458 switch (TRB_TYPE(*trb)) { 1459 case TR_DATA: 1460 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) { 1461 DPRINTF("xhci: data direction mismatch for TR_DATA\n"); 1462 goto err; 1463 } 1464 /* fallthrough */ 1465 case TR_NORMAL: 1466 case TR_ISOCH: 1467 addr = xhci_mask64(trb->parameter); 1468 chunk = trb->status & 0x1ffff; 1469 if (trb->control & TRB_TR_IDT) { 1470 if (chunk > 8 || in_xfer) { 1471 DPRINTF("xhci: invalid immediate data TRB\n"); 1472 goto err; 1473 } 1474 qemu_sglist_add(&xfer->sgl, trb->addr, chunk); 1475 } else { 1476 qemu_sglist_add(&xfer->sgl, addr, chunk); 1477 } 1478 break; 1479 } 1480 } 1481 1482 return 0; 1483 1484 err: 1485 qemu_sglist_destroy(&xfer->sgl); 1486 xhci_die(xhci); 1487 return -1; 1488 } 1489 1490 static void xhci_xfer_report(XHCITransfer *xfer) 1491 { 1492 uint32_t edtla = 0; 1493 unsigned int left; 1494 bool reported = 0; 1495 bool shortpkt = 0; 1496 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS}; 1497 XHCIState *xhci = xfer->epctx->xhci; 1498 int i; 1499 1500 left = xfer->packet.actual_length; 1501 1502 for (i = 0; i < xfer->trb_count; i++) { 1503 XHCITRB *trb = &xfer->trbs[i]; 1504 unsigned int chunk = 0; 1505 1506 switch (TRB_TYPE(*trb)) { 1507 case TR_SETUP: 1508 chunk = trb->status & 0x1ffff; 1509 if (chunk > 8) { 1510 chunk = 8; 1511 } 1512 break; 1513 case TR_DATA: 1514 case TR_NORMAL: 1515 case TR_ISOCH: 1516 chunk = trb->status & 0x1ffff; 1517 if (chunk > left) { 1518 chunk = left; 1519 if (xfer->status == CC_SUCCESS) { 1520 shortpkt = 1; 1521 } 1522 } 1523 left -= chunk; 1524 edtla += chunk; 1525 break; 1526 case TR_STATUS: 1527 reported = 0; 1528 shortpkt = 0; 1529 break; 1530 } 1531 1532 if (!reported && ((trb->control & TRB_TR_IOC) || 1533 (shortpkt && (trb->control & TRB_TR_ISP)) || 1534 (xfer->status != CC_SUCCESS && left == 0))) { 1535 event.slotid = xfer->epctx->slotid; 1536 event.epid = xfer->epctx->epid; 1537 event.length = (trb->status & 0x1ffff) - chunk; 1538 event.flags = 0; 1539 event.ptr = trb->addr; 1540 if (xfer->status == CC_SUCCESS) { 1541 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS; 1542 } else { 1543 event.ccode = xfer->status; 1544 } 1545 if (TRB_TYPE(*trb) == TR_EVDATA) { 1546 event.ptr = trb->parameter; 1547 event.flags |= TRB_EV_ED; 1548 event.length = edtla & 0xffffff; 1549 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length); 1550 edtla = 0; 1551 } 1552 xhci_event(xhci, &event, TRB_INTR(*trb)); 1553 reported = 1; 1554 if (xfer->status != CC_SUCCESS) { 1555 return; 1556 } 1557 } 1558 1559 switch (TRB_TYPE(*trb)) { 1560 case TR_SETUP: 1561 reported = 0; 1562 shortpkt = 0; 1563 break; 1564 } 1565 1566 } 1567 } 1568 1569 static void xhci_stall_ep(XHCITransfer *xfer) 1570 { 1571 XHCIEPContext *epctx = xfer->epctx; 1572 XHCIState *xhci = epctx->xhci; 1573 uint32_t err; 1574 XHCIStreamContext *sctx; 1575 1576 if (epctx->type == ET_ISO_IN || epctx->type == ET_ISO_OUT) { 1577 /* never halt isoch endpoints, 4.10.2 */ 1578 return; 1579 } 1580 1581 if (epctx->nr_pstreams) { 1582 sctx = xhci_find_stream(epctx, xfer->streamid, &err); 1583 if (sctx == NULL) { 1584 return; 1585 } 1586 sctx->ring.dequeue = xfer->trbs[0].addr; 1587 sctx->ring.ccs = xfer->trbs[0].ccs; 1588 xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED); 1589 } else { 1590 epctx->ring.dequeue = xfer->trbs[0].addr; 1591 epctx->ring.ccs = xfer->trbs[0].ccs; 1592 xhci_set_ep_state(xhci, epctx, NULL, EP_HALTED); 1593 } 1594 } 1595 1596 static int xhci_setup_packet(XHCITransfer *xfer) 1597 { 1598 USBEndpoint *ep; 1599 int dir; 1600 1601 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT; 1602 1603 if (xfer->packet.ep) { 1604 ep = xfer->packet.ep; 1605 } else { 1606 ep = xhci_epid_to_usbep(xfer->epctx); 1607 if (!ep) { 1608 DPRINTF("xhci: slot %d has no device\n", 1609 xfer->epctx->slotid); 1610 return -1; 1611 } 1612 } 1613 1614 xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */ 1615 usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid, 1616 xfer->trbs[0].addr, false, xfer->int_req); 1617 if (usb_packet_map(&xfer->packet, &xfer->sgl)) { 1618 qemu_sglist_destroy(&xfer->sgl); 1619 return -1; 1620 } 1621 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n", 1622 xfer->packet.pid, ep->dev->addr, ep->nr); 1623 return 0; 1624 } 1625 1626 static int xhci_try_complete_packet(XHCITransfer *xfer) 1627 { 1628 if (xfer->packet.status == USB_RET_ASYNC) { 1629 trace_usb_xhci_xfer_async(xfer); 1630 xfer->running_async = 1; 1631 xfer->running_retry = 0; 1632 xfer->complete = 0; 1633 return 0; 1634 } else if (xfer->packet.status == USB_RET_NAK) { 1635 trace_usb_xhci_xfer_nak(xfer); 1636 xfer->running_async = 0; 1637 xfer->running_retry = 1; 1638 xfer->complete = 0; 1639 return 0; 1640 } else { 1641 xfer->running_async = 0; 1642 xfer->running_retry = 0; 1643 xfer->complete = 1; 1644 xhci_xfer_unmap(xfer); 1645 } 1646 1647 if (xfer->packet.status == USB_RET_SUCCESS) { 1648 trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length); 1649 xfer->status = CC_SUCCESS; 1650 xhci_xfer_report(xfer); 1651 return 0; 1652 } 1653 1654 /* error */ 1655 trace_usb_xhci_xfer_error(xfer, xfer->packet.status); 1656 switch (xfer->packet.status) { 1657 case USB_RET_NODEV: 1658 case USB_RET_IOERROR: 1659 xfer->status = CC_USB_TRANSACTION_ERROR; 1660 xhci_xfer_report(xfer); 1661 xhci_stall_ep(xfer); 1662 break; 1663 case USB_RET_STALL: 1664 xfer->status = CC_STALL_ERROR; 1665 xhci_xfer_report(xfer); 1666 xhci_stall_ep(xfer); 1667 break; 1668 case USB_RET_BABBLE: 1669 xfer->status = CC_BABBLE_DETECTED; 1670 xhci_xfer_report(xfer); 1671 xhci_stall_ep(xfer); 1672 break; 1673 default: 1674 DPRINTF("%s: FIXME: status = %d\n", __func__, 1675 xfer->packet.status); 1676 FIXME("unhandled USB_RET_*"); 1677 } 1678 return 0; 1679 } 1680 1681 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer) 1682 { 1683 XHCITRB *trb_setup, *trb_status; 1684 uint8_t bmRequestType; 1685 1686 trb_setup = &xfer->trbs[0]; 1687 trb_status = &xfer->trbs[xfer->trb_count-1]; 1688 1689 trace_usb_xhci_xfer_start(xfer, xfer->epctx->slotid, 1690 xfer->epctx->epid, xfer->streamid); 1691 1692 /* at most one Event Data TRB allowed after STATUS */ 1693 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) { 1694 trb_status--; 1695 } 1696 1697 /* do some sanity checks */ 1698 if (TRB_TYPE(*trb_setup) != TR_SETUP) { 1699 DPRINTF("xhci: ep0 first TD not SETUP: %d\n", 1700 TRB_TYPE(*trb_setup)); 1701 return -1; 1702 } 1703 if (TRB_TYPE(*trb_status) != TR_STATUS) { 1704 DPRINTF("xhci: ep0 last TD not STATUS: %d\n", 1705 TRB_TYPE(*trb_status)); 1706 return -1; 1707 } 1708 if (!(trb_setup->control & TRB_TR_IDT)) { 1709 DPRINTF("xhci: Setup TRB doesn't have IDT set\n"); 1710 return -1; 1711 } 1712 if ((trb_setup->status & 0x1ffff) != 8) { 1713 DPRINTF("xhci: Setup TRB has bad length (%d)\n", 1714 (trb_setup->status & 0x1ffff)); 1715 return -1; 1716 } 1717 1718 bmRequestType = trb_setup->parameter; 1719 1720 xfer->in_xfer = bmRequestType & USB_DIR_IN; 1721 xfer->iso_xfer = false; 1722 xfer->timed_xfer = false; 1723 1724 if (xhci_setup_packet(xfer) < 0) { 1725 return -1; 1726 } 1727 xfer->packet.parameter = trb_setup->parameter; 1728 1729 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1730 xhci_try_complete_packet(xfer); 1731 return 0; 1732 } 1733 1734 static void xhci_calc_intr_kick(XHCIState *xhci, XHCITransfer *xfer, 1735 XHCIEPContext *epctx, uint64_t mfindex) 1736 { 1737 uint64_t asap = ((mfindex + epctx->interval - 1) & 1738 ~(epctx->interval-1)); 1739 uint64_t kick = epctx->mfindex_last + epctx->interval; 1740 1741 assert(epctx->interval != 0); 1742 xfer->mfindex_kick = MAX(asap, kick); 1743 } 1744 1745 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1746 XHCIEPContext *epctx, uint64_t mfindex) 1747 { 1748 if (xfer->trbs[0].control & TRB_TR_SIA) { 1749 uint64_t asap = ((mfindex + epctx->interval - 1) & 1750 ~(epctx->interval-1)); 1751 if (asap >= epctx->mfindex_last && 1752 asap <= epctx->mfindex_last + epctx->interval * 4) { 1753 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval; 1754 } else { 1755 xfer->mfindex_kick = asap; 1756 } 1757 } else { 1758 xfer->mfindex_kick = ((xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT) 1759 & TRB_TR_FRAMEID_MASK) << 3; 1760 xfer->mfindex_kick |= mfindex & ~0x3fff; 1761 if (xfer->mfindex_kick + 0x100 < mfindex) { 1762 xfer->mfindex_kick += 0x4000; 1763 } 1764 } 1765 } 1766 1767 static void xhci_check_intr_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1768 XHCIEPContext *epctx, uint64_t mfindex) 1769 { 1770 if (xfer->mfindex_kick > mfindex) { 1771 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 1772 (xfer->mfindex_kick - mfindex) * 125000); 1773 xfer->running_retry = 1; 1774 } else { 1775 epctx->mfindex_last = xfer->mfindex_kick; 1776 timer_del(epctx->kick_timer); 1777 xfer->running_retry = 0; 1778 } 1779 } 1780 1781 1782 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1783 { 1784 uint64_t mfindex; 1785 1786 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", epctx->slotid, epctx->epid); 1787 1788 xfer->in_xfer = epctx->type>>2; 1789 1790 switch(epctx->type) { 1791 case ET_INTR_OUT: 1792 case ET_INTR_IN: 1793 xfer->pkts = 0; 1794 xfer->iso_xfer = false; 1795 xfer->timed_xfer = true; 1796 mfindex = xhci_mfindex_get(xhci); 1797 xhci_calc_intr_kick(xhci, xfer, epctx, mfindex); 1798 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); 1799 if (xfer->running_retry) { 1800 return -1; 1801 } 1802 break; 1803 case ET_BULK_OUT: 1804 case ET_BULK_IN: 1805 xfer->pkts = 0; 1806 xfer->iso_xfer = false; 1807 xfer->timed_xfer = false; 1808 break; 1809 case ET_ISO_OUT: 1810 case ET_ISO_IN: 1811 xfer->pkts = 1; 1812 xfer->iso_xfer = true; 1813 xfer->timed_xfer = true; 1814 mfindex = xhci_mfindex_get(xhci); 1815 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex); 1816 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); 1817 if (xfer->running_retry) { 1818 return -1; 1819 } 1820 break; 1821 default: 1822 trace_usb_xhci_unimplemented("endpoint type", epctx->type); 1823 return -1; 1824 } 1825 1826 if (xhci_setup_packet(xfer) < 0) { 1827 return -1; 1828 } 1829 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1830 xhci_try_complete_packet(xfer); 1831 return 0; 1832 } 1833 1834 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1835 { 1836 trace_usb_xhci_xfer_start(xfer, xfer->epctx->slotid, 1837 xfer->epctx->epid, xfer->streamid); 1838 return xhci_submit(xhci, xfer, epctx); 1839 } 1840 1841 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 1842 unsigned int epid, unsigned int streamid) 1843 { 1844 XHCIEPContext *epctx; 1845 1846 assert(slotid >= 1 && slotid <= xhci->numslots); 1847 assert(epid >= 1 && epid <= 31); 1848 1849 if (!xhci->slots[slotid-1].enabled) { 1850 DPRINTF("xhci: xhci_kick_ep for disabled slot %d\n", slotid); 1851 return; 1852 } 1853 epctx = xhci->slots[slotid-1].eps[epid-1]; 1854 if (!epctx) { 1855 DPRINTF("xhci: xhci_kick_ep for disabled endpoint %d,%d\n", 1856 epid, slotid); 1857 return; 1858 } 1859 1860 if (epctx->kick_active) { 1861 return; 1862 } 1863 xhci_kick_epctx(epctx, streamid); 1864 } 1865 1866 static bool xhci_slot_ok(XHCIState *xhci, int slotid) 1867 { 1868 return (xhci->slots[slotid - 1].uport && 1869 xhci->slots[slotid - 1].uport->dev && 1870 xhci->slots[slotid - 1].uport->dev->attached); 1871 } 1872 1873 static void xhci_kick_epctx(XHCIEPContext *epctx, unsigned int streamid) 1874 { 1875 XHCIState *xhci = epctx->xhci; 1876 XHCIStreamContext *stctx = NULL; 1877 XHCITransfer *xfer; 1878 XHCIRing *ring; 1879 USBEndpoint *ep = NULL; 1880 uint64_t mfindex; 1881 unsigned int count = 0; 1882 int length; 1883 int i; 1884 1885 trace_usb_xhci_ep_kick(epctx->slotid, epctx->epid, streamid); 1886 assert(!epctx->kick_active); 1887 1888 /* If the device has been detached, but the guest has not noticed this 1889 yet the 2 above checks will succeed, but we must NOT continue */ 1890 if (!xhci_slot_ok(xhci, epctx->slotid)) { 1891 return; 1892 } 1893 1894 if (epctx->retry) { 1895 xfer = epctx->retry; 1896 1897 trace_usb_xhci_xfer_retry(xfer); 1898 assert(xfer->running_retry); 1899 if (xfer->timed_xfer) { 1900 /* time to kick the transfer? */ 1901 mfindex = xhci_mfindex_get(xhci); 1902 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); 1903 if (xfer->running_retry) { 1904 return; 1905 } 1906 xfer->timed_xfer = 0; 1907 xfer->running_retry = 1; 1908 } 1909 if (xfer->iso_xfer) { 1910 /* retry iso transfer */ 1911 if (xhci_setup_packet(xfer) < 0) { 1912 return; 1913 } 1914 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1915 assert(xfer->packet.status != USB_RET_NAK); 1916 xhci_try_complete_packet(xfer); 1917 } else { 1918 /* retry nak'ed transfer */ 1919 if (xhci_setup_packet(xfer) < 0) { 1920 return; 1921 } 1922 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1923 if (xfer->packet.status == USB_RET_NAK) { 1924 xhci_xfer_unmap(xfer); 1925 return; 1926 } 1927 xhci_try_complete_packet(xfer); 1928 } 1929 assert(!xfer->running_retry); 1930 if (xfer->complete) { 1931 /* update ring dequeue ptr */ 1932 xhci_set_ep_state(xhci, epctx, stctx, epctx->state); 1933 xhci_ep_free_xfer(epctx->retry); 1934 } 1935 epctx->retry = NULL; 1936 } 1937 1938 if (epctx->state == EP_HALTED) { 1939 DPRINTF("xhci: ep halted, not running schedule\n"); 1940 return; 1941 } 1942 1943 1944 if (epctx->nr_pstreams) { 1945 uint32_t err; 1946 stctx = xhci_find_stream(epctx, streamid, &err); 1947 if (stctx == NULL) { 1948 return; 1949 } 1950 ring = &stctx->ring; 1951 xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING); 1952 } else { 1953 ring = &epctx->ring; 1954 streamid = 0; 1955 xhci_set_ep_state(xhci, epctx, NULL, EP_RUNNING); 1956 } 1957 if (!ring->dequeue) { 1958 return; 1959 } 1960 1961 epctx->kick_active++; 1962 while (1) { 1963 length = xhci_ring_chain_length(xhci, ring); 1964 if (length <= 0) { 1965 if (epctx->type == ET_ISO_OUT || epctx->type == ET_ISO_IN) { 1966 /* 4.10.3.1 */ 1967 XHCIEvent ev = { ER_TRANSFER }; 1968 ev.ccode = epctx->type == ET_ISO_IN ? 1969 CC_RING_OVERRUN : CC_RING_UNDERRUN; 1970 ev.slotid = epctx->slotid; 1971 ev.epid = epctx->epid; 1972 ev.ptr = epctx->ring.dequeue; 1973 xhci_event(xhci, &ev, xhci->slots[epctx->slotid-1].intr); 1974 } 1975 break; 1976 } 1977 xfer = xhci_ep_alloc_xfer(epctx, length); 1978 if (xfer == NULL) { 1979 break; 1980 } 1981 1982 for (i = 0; i < length; i++) { 1983 TRBType type; 1984 type = xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL); 1985 if (!type) { 1986 xhci_die(xhci); 1987 xhci_ep_free_xfer(xfer); 1988 epctx->kick_active--; 1989 return; 1990 } 1991 } 1992 xfer->streamid = streamid; 1993 1994 if (epctx->epid == 1) { 1995 xhci_fire_ctl_transfer(xhci, xfer); 1996 } else { 1997 xhci_fire_transfer(xhci, xfer, epctx); 1998 } 1999 if (!xhci_slot_ok(xhci, epctx->slotid)) { 2000 /* surprise removal -> stop processing */ 2001 break; 2002 } 2003 if (xfer->complete) { 2004 /* update ring dequeue ptr */ 2005 xhci_set_ep_state(xhci, epctx, stctx, epctx->state); 2006 xhci_ep_free_xfer(xfer); 2007 xfer = NULL; 2008 } 2009 2010 if (epctx->state == EP_HALTED) { 2011 break; 2012 } 2013 if (xfer != NULL && xfer->running_retry) { 2014 DPRINTF("xhci: xfer nacked, stopping schedule\n"); 2015 epctx->retry = xfer; 2016 xhci_xfer_unmap(xfer); 2017 break; 2018 } 2019 if (count++ > TRANSFER_LIMIT) { 2020 trace_usb_xhci_enforced_limit("transfers"); 2021 break; 2022 } 2023 } 2024 epctx->kick_active--; 2025 2026 ep = xhci_epid_to_usbep(epctx); 2027 if (ep) { 2028 usb_device_flush_ep_queue(ep->dev, ep); 2029 } 2030 } 2031 2032 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid) 2033 { 2034 trace_usb_xhci_slot_enable(slotid); 2035 assert(slotid >= 1 && slotid <= xhci->numslots); 2036 xhci->slots[slotid-1].enabled = 1; 2037 xhci->slots[slotid-1].uport = NULL; 2038 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31); 2039 2040 return CC_SUCCESS; 2041 } 2042 2043 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid) 2044 { 2045 int i; 2046 2047 trace_usb_xhci_slot_disable(slotid); 2048 assert(slotid >= 1 && slotid <= xhci->numslots); 2049 2050 for (i = 1; i <= 31; i++) { 2051 if (xhci->slots[slotid-1].eps[i-1]) { 2052 xhci_disable_ep(xhci, slotid, i); 2053 } 2054 } 2055 2056 xhci->slots[slotid-1].enabled = 0; 2057 xhci->slots[slotid-1].addressed = 0; 2058 xhci->slots[slotid-1].uport = NULL; 2059 xhci->slots[slotid-1].intr = 0; 2060 return CC_SUCCESS; 2061 } 2062 2063 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx) 2064 { 2065 USBPort *uport; 2066 char path[32]; 2067 int i, pos, port; 2068 2069 port = (slot_ctx[1]>>16) & 0xFF; 2070 if (port < 1 || port > xhci->numports) { 2071 return NULL; 2072 } 2073 port = xhci->ports[port-1].uport->index+1; 2074 pos = snprintf(path, sizeof(path), "%d", port); 2075 for (i = 0; i < 5; i++) { 2076 port = (slot_ctx[0] >> 4*i) & 0x0f; 2077 if (!port) { 2078 break; 2079 } 2080 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port); 2081 } 2082 2083 QTAILQ_FOREACH(uport, &xhci->bus.used, next) { 2084 if (strcmp(uport->path, path) == 0) { 2085 return uport; 2086 } 2087 } 2088 return NULL; 2089 } 2090 2091 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, 2092 uint64_t pictx, bool bsr) 2093 { 2094 XHCISlot *slot; 2095 USBPort *uport; 2096 USBDevice *dev; 2097 dma_addr_t ictx, octx, dcbaap; 2098 uint64_t poctx; 2099 uint32_t ictl_ctx[2]; 2100 uint32_t slot_ctx[4]; 2101 uint32_t ep0_ctx[5]; 2102 int i; 2103 TRBCCode res; 2104 2105 assert(slotid >= 1 && slotid <= xhci->numslots); 2106 2107 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 2108 ldq_le_dma(xhci->as, dcbaap + 8 * slotid, &poctx, MEMTXATTRS_UNSPECIFIED); 2109 ictx = xhci_mask64(pictx); 2110 octx = xhci_mask64(poctx); 2111 2112 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2113 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2114 2115 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2116 2117 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) { 2118 DPRINTF("xhci: invalid input context control %08x %08x\n", 2119 ictl_ctx[0], ictl_ctx[1]); 2120 return CC_TRB_ERROR; 2121 } 2122 2123 xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx)); 2124 xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx)); 2125 2126 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2127 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2128 2129 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2130 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2131 2132 uport = xhci_lookup_uport(xhci, slot_ctx); 2133 if (uport == NULL) { 2134 DPRINTF("xhci: port not found\n"); 2135 return CC_TRB_ERROR; 2136 } 2137 trace_usb_xhci_slot_address(slotid, uport->path); 2138 2139 dev = uport->dev; 2140 if (!dev || !dev->attached) { 2141 DPRINTF("xhci: port %s not connected\n", uport->path); 2142 return CC_USB_TRANSACTION_ERROR; 2143 } 2144 2145 for (i = 0; i < xhci->numslots; i++) { 2146 if (i == slotid-1) { 2147 continue; 2148 } 2149 if (xhci->slots[i].uport == uport) { 2150 DPRINTF("xhci: port %s already assigned to slot %d\n", 2151 uport->path, i+1); 2152 return CC_TRB_ERROR; 2153 } 2154 } 2155 2156 slot = &xhci->slots[slotid-1]; 2157 slot->uport = uport; 2158 slot->ctx = octx; 2159 slot->intr = get_field(slot_ctx[2], TRB_INTR); 2160 2161 /* Make sure device is in USB_STATE_DEFAULT state */ 2162 usb_device_reset(dev); 2163 if (bsr) { 2164 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT; 2165 } else { 2166 USBPacket p; 2167 uint8_t buf[1]; 2168 2169 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid; 2170 memset(&p, 0, sizeof(p)); 2171 usb_packet_addbuf(&p, buf, sizeof(buf)); 2172 usb_packet_setup(&p, USB_TOKEN_OUT, 2173 usb_ep_get(dev, USB_TOKEN_OUT, 0), 0, 2174 0, false, false); 2175 usb_device_handle_control(dev, &p, 2176 DeviceOutRequest | USB_REQ_SET_ADDRESS, 2177 slotid, 0, 0, NULL); 2178 assert(p.status != USB_RET_ASYNC); 2179 usb_packet_cleanup(&p); 2180 } 2181 2182 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx); 2183 2184 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2185 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2186 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2187 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2188 2189 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2190 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2191 2192 xhci->slots[slotid-1].addressed = 1; 2193 return res; 2194 } 2195 2196 2197 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid, 2198 uint64_t pictx, bool dc) 2199 { 2200 dma_addr_t ictx, octx; 2201 uint32_t ictl_ctx[2]; 2202 uint32_t slot_ctx[4]; 2203 uint32_t islot_ctx[4]; 2204 uint32_t ep_ctx[5]; 2205 int i; 2206 TRBCCode res; 2207 2208 trace_usb_xhci_slot_configure(slotid); 2209 assert(slotid >= 1 && slotid <= xhci->numslots); 2210 2211 ictx = xhci_mask64(pictx); 2212 octx = xhci->slots[slotid-1].ctx; 2213 2214 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2215 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2216 2217 if (dc) { 2218 for (i = 2; i <= 31; i++) { 2219 if (xhci->slots[slotid-1].eps[i-1]) { 2220 xhci_disable_ep(xhci, slotid, i); 2221 } 2222 } 2223 2224 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2225 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2226 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT; 2227 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2228 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2229 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2230 2231 return CC_SUCCESS; 2232 } 2233 2234 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2235 2236 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) { 2237 DPRINTF("xhci: invalid input context control %08x %08x\n", 2238 ictl_ctx[0], ictl_ctx[1]); 2239 return CC_TRB_ERROR; 2240 } 2241 2242 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); 2243 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2244 2245 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) { 2246 DPRINTF("xhci: invalid slot state %08x\n", slot_ctx[3]); 2247 return CC_CONTEXT_STATE_ERROR; 2248 } 2249 2250 xhci_free_device_streams(xhci, slotid, ictl_ctx[0] | ictl_ctx[1]); 2251 2252 for (i = 2; i <= 31; i++) { 2253 if (ictl_ctx[0] & (1<<i)) { 2254 xhci_disable_ep(xhci, slotid, i); 2255 } 2256 if (ictl_ctx[1] & (1<<i)) { 2257 xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx)); 2258 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n", 2259 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2260 ep_ctx[3], ep_ctx[4]); 2261 xhci_disable_ep(xhci, slotid, i); 2262 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx); 2263 if (res != CC_SUCCESS) { 2264 return res; 2265 } 2266 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n", 2267 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2268 ep_ctx[3], ep_ctx[4]); 2269 xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx)); 2270 } 2271 } 2272 2273 res = xhci_alloc_device_streams(xhci, slotid, ictl_ctx[1]); 2274 if (res != CC_SUCCESS) { 2275 for (i = 2; i <= 31; i++) { 2276 if (ictl_ctx[1] & (1u << i)) { 2277 xhci_disable_ep(xhci, slotid, i); 2278 } 2279 } 2280 return res; 2281 } 2282 2283 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2284 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT; 2285 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT); 2286 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK << 2287 SLOT_CONTEXT_ENTRIES_SHIFT); 2288 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2289 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2290 2291 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2292 2293 return CC_SUCCESS; 2294 } 2295 2296 2297 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid, 2298 uint64_t pictx) 2299 { 2300 dma_addr_t ictx, octx; 2301 uint32_t ictl_ctx[2]; 2302 uint32_t iep0_ctx[5]; 2303 uint32_t ep0_ctx[5]; 2304 uint32_t islot_ctx[4]; 2305 uint32_t slot_ctx[4]; 2306 2307 trace_usb_xhci_slot_evaluate(slotid); 2308 assert(slotid >= 1 && slotid <= xhci->numslots); 2309 2310 ictx = xhci_mask64(pictx); 2311 octx = xhci->slots[slotid-1].ctx; 2312 2313 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2314 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2315 2316 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2317 2318 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) { 2319 DPRINTF("xhci: invalid input context control %08x %08x\n", 2320 ictl_ctx[0], ictl_ctx[1]); 2321 return CC_TRB_ERROR; 2322 } 2323 2324 if (ictl_ctx[1] & 0x1) { 2325 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); 2326 2327 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2328 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]); 2329 2330 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2331 2332 slot_ctx[1] &= ~0xFFFF; /* max exit latency */ 2333 slot_ctx[1] |= islot_ctx[1] & 0xFFFF; 2334 /* update interrupter target field */ 2335 xhci->slots[slotid-1].intr = get_field(islot_ctx[2], TRB_INTR); 2336 set_field(&slot_ctx[2], xhci->slots[slotid-1].intr, TRB_INTR); 2337 2338 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2339 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2340 2341 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2342 } 2343 2344 if (ictl_ctx[1] & 0x2) { 2345 xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx)); 2346 2347 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2348 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2], 2349 iep0_ctx[3], iep0_ctx[4]); 2350 2351 xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2352 2353 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/ 2354 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000; 2355 2356 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2357 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2358 2359 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2360 } 2361 2362 return CC_SUCCESS; 2363 } 2364 2365 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid) 2366 { 2367 uint32_t slot_ctx[4]; 2368 dma_addr_t octx; 2369 int i; 2370 2371 trace_usb_xhci_slot_reset(slotid); 2372 assert(slotid >= 1 && slotid <= xhci->numslots); 2373 2374 octx = xhci->slots[slotid-1].ctx; 2375 2376 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2377 2378 for (i = 2; i <= 31; i++) { 2379 if (xhci->slots[slotid-1].eps[i-1]) { 2380 xhci_disable_ep(xhci, slotid, i); 2381 } 2382 } 2383 2384 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2385 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2386 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT; 2387 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2388 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2389 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2390 2391 return CC_SUCCESS; 2392 } 2393 2394 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb) 2395 { 2396 unsigned int slotid; 2397 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK; 2398 if (slotid < 1 || slotid > xhci->numslots) { 2399 DPRINTF("xhci: bad slot id %d\n", slotid); 2400 event->ccode = CC_TRB_ERROR; 2401 return 0; 2402 } else if (!xhci->slots[slotid-1].enabled) { 2403 DPRINTF("xhci: slot id %d not enabled\n", slotid); 2404 event->ccode = CC_SLOT_NOT_ENABLED_ERROR; 2405 return 0; 2406 } 2407 return slotid; 2408 } 2409 2410 /* cleanup slot state on usb device detach */ 2411 static void xhci_detach_slot(XHCIState *xhci, USBPort *uport) 2412 { 2413 int slot, ep; 2414 2415 for (slot = 0; slot < xhci->numslots; slot++) { 2416 if (xhci->slots[slot].uport == uport) { 2417 break; 2418 } 2419 } 2420 if (slot == xhci->numslots) { 2421 return; 2422 } 2423 2424 for (ep = 0; ep < 31; ep++) { 2425 if (xhci->slots[slot].eps[ep]) { 2426 xhci_ep_nuke_xfers(xhci, slot + 1, ep + 1, 0); 2427 } 2428 } 2429 xhci->slots[slot].uport = NULL; 2430 } 2431 2432 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx) 2433 { 2434 dma_addr_t ctx; 2435 2436 DPRINTF("xhci_get_port_bandwidth()\n"); 2437 2438 ctx = xhci_mask64(pctx); 2439 2440 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx); 2441 2442 /* TODO: actually implement real values here. This is 80% for all ports. */ 2443 if (stb_dma(xhci->as, ctx, 0, MEMTXATTRS_UNSPECIFIED) != MEMTX_OK || 2444 dma_memory_set(xhci->as, ctx + 1, 80, xhci->numports, 2445 MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) { 2446 qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory write failed!\n", 2447 __func__); 2448 return CC_TRB_ERROR; 2449 } 2450 2451 return CC_SUCCESS; 2452 } 2453 2454 static uint32_t rotl(uint32_t v, unsigned count) 2455 { 2456 count &= 31; 2457 return (v << count) | (v >> (32 - count)); 2458 } 2459 2460 2461 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo) 2462 { 2463 uint32_t val; 2464 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F)); 2465 val += rotl(lo + 0x49434878, hi & 0x1F); 2466 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F); 2467 return ~val; 2468 } 2469 2470 static void xhci_process_commands(XHCIState *xhci) 2471 { 2472 XHCITRB trb; 2473 TRBType type; 2474 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS}; 2475 dma_addr_t addr; 2476 unsigned int i, slotid = 0, count = 0; 2477 2478 DPRINTF("xhci_process_commands()\n"); 2479 if (!xhci_running(xhci)) { 2480 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n"); 2481 return; 2482 } 2483 2484 xhci->crcr_low |= CRCR_CRR; 2485 2486 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) { 2487 event.ptr = addr; 2488 switch (type) { 2489 case CR_ENABLE_SLOT: 2490 for (i = 0; i < xhci->numslots; i++) { 2491 if (!xhci->slots[i].enabled) { 2492 break; 2493 } 2494 } 2495 if (i >= xhci->numslots) { 2496 DPRINTF("xhci: no device slots available\n"); 2497 event.ccode = CC_NO_SLOTS_ERROR; 2498 } else { 2499 slotid = i+1; 2500 event.ccode = xhci_enable_slot(xhci, slotid); 2501 } 2502 break; 2503 case CR_DISABLE_SLOT: 2504 slotid = xhci_get_slot(xhci, &event, &trb); 2505 if (slotid) { 2506 event.ccode = xhci_disable_slot(xhci, slotid); 2507 } 2508 break; 2509 case CR_ADDRESS_DEVICE: 2510 slotid = xhci_get_slot(xhci, &event, &trb); 2511 if (slotid) { 2512 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter, 2513 trb.control & TRB_CR_BSR); 2514 } 2515 break; 2516 case CR_CONFIGURE_ENDPOINT: 2517 slotid = xhci_get_slot(xhci, &event, &trb); 2518 if (slotid) { 2519 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter, 2520 trb.control & TRB_CR_DC); 2521 } 2522 break; 2523 case CR_EVALUATE_CONTEXT: 2524 slotid = xhci_get_slot(xhci, &event, &trb); 2525 if (slotid) { 2526 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter); 2527 } 2528 break; 2529 case CR_STOP_ENDPOINT: 2530 slotid = xhci_get_slot(xhci, &event, &trb); 2531 if (slotid) { 2532 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2533 & TRB_CR_EPID_MASK; 2534 event.ccode = xhci_stop_ep(xhci, slotid, epid); 2535 } 2536 break; 2537 case CR_RESET_ENDPOINT: 2538 slotid = xhci_get_slot(xhci, &event, &trb); 2539 if (slotid) { 2540 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2541 & TRB_CR_EPID_MASK; 2542 event.ccode = xhci_reset_ep(xhci, slotid, epid); 2543 } 2544 break; 2545 case CR_SET_TR_DEQUEUE: 2546 slotid = xhci_get_slot(xhci, &event, &trb); 2547 if (slotid) { 2548 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2549 & TRB_CR_EPID_MASK; 2550 unsigned int streamid = (trb.status >> 16) & 0xffff; 2551 event.ccode = xhci_set_ep_dequeue(xhci, slotid, 2552 epid, streamid, 2553 trb.parameter); 2554 } 2555 break; 2556 case CR_RESET_DEVICE: 2557 slotid = xhci_get_slot(xhci, &event, &trb); 2558 if (slotid) { 2559 event.ccode = xhci_reset_slot(xhci, slotid); 2560 } 2561 break; 2562 case CR_GET_PORT_BANDWIDTH: 2563 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter); 2564 break; 2565 case CR_NOOP: 2566 event.ccode = CC_SUCCESS; 2567 break; 2568 case CR_VENDOR_NEC_FIRMWARE_REVISION: 2569 if (xhci->nec_quirks) { 2570 event.type = 48; /* NEC reply */ 2571 event.length = 0x3034; 2572 } else { 2573 event.ccode = CC_TRB_ERROR; 2574 } 2575 break; 2576 case CR_VENDOR_NEC_CHALLENGE_RESPONSE: 2577 if (xhci->nec_quirks) { 2578 uint32_t chi = trb.parameter >> 32; 2579 uint32_t clo = trb.parameter; 2580 uint32_t val = xhci_nec_challenge(chi, clo); 2581 event.length = val & 0xFFFF; 2582 event.epid = val >> 16; 2583 slotid = val >> 24; 2584 event.type = 48; /* NEC reply */ 2585 } else { 2586 event.ccode = CC_TRB_ERROR; 2587 } 2588 break; 2589 default: 2590 trace_usb_xhci_unimplemented("command", type); 2591 event.ccode = CC_TRB_ERROR; 2592 break; 2593 } 2594 event.slotid = slotid; 2595 xhci_event(xhci, &event, 0); 2596 2597 if (count++ > COMMAND_LIMIT) { 2598 trace_usb_xhci_enforced_limit("commands"); 2599 return; 2600 } 2601 } 2602 } 2603 2604 static bool xhci_port_have_device(XHCIPort *port) 2605 { 2606 if (!port->uport->dev || !port->uport->dev->attached) { 2607 return false; /* no device present */ 2608 } 2609 if (!((1 << port->uport->dev->speed) & port->speedmask)) { 2610 return false; /* speed mismatch */ 2611 } 2612 return true; 2613 } 2614 2615 static void xhci_port_notify(XHCIPort *port, uint32_t bits) 2616 { 2617 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, 2618 port->portnr << 24 }; 2619 2620 if ((port->portsc & bits) == bits) { 2621 return; 2622 } 2623 trace_usb_xhci_port_notify(port->portnr, bits); 2624 port->portsc |= bits; 2625 if (!xhci_running(port->xhci)) { 2626 return; 2627 } 2628 xhci_event(port->xhci, &ev, 0); 2629 } 2630 2631 static void xhci_port_update(XHCIPort *port, int is_detach) 2632 { 2633 uint32_t pls = PLS_RX_DETECT; 2634 2635 assert(port); 2636 port->portsc = PORTSC_PP; 2637 if (!is_detach && xhci_port_have_device(port)) { 2638 port->portsc |= PORTSC_CCS; 2639 switch (port->uport->dev->speed) { 2640 case USB_SPEED_LOW: 2641 port->portsc |= PORTSC_SPEED_LOW; 2642 pls = PLS_POLLING; 2643 break; 2644 case USB_SPEED_FULL: 2645 port->portsc |= PORTSC_SPEED_FULL; 2646 pls = PLS_POLLING; 2647 break; 2648 case USB_SPEED_HIGH: 2649 port->portsc |= PORTSC_SPEED_HIGH; 2650 pls = PLS_POLLING; 2651 break; 2652 case USB_SPEED_SUPER: 2653 port->portsc |= PORTSC_SPEED_SUPER; 2654 port->portsc |= PORTSC_PED; 2655 pls = PLS_U0; 2656 break; 2657 } 2658 } 2659 set_field(&port->portsc, pls, PORTSC_PLS); 2660 trace_usb_xhci_port_link(port->portnr, pls); 2661 xhci_port_notify(port, PORTSC_CSC); 2662 } 2663 2664 static void xhci_port_reset(XHCIPort *port, bool warm_reset) 2665 { 2666 trace_usb_xhci_port_reset(port->portnr, warm_reset); 2667 2668 if (!xhci_port_have_device(port)) { 2669 return; 2670 } 2671 2672 usb_device_reset(port->uport->dev); 2673 2674 switch (port->uport->dev->speed) { 2675 case USB_SPEED_SUPER: 2676 if (warm_reset) { 2677 port->portsc |= PORTSC_WRC; 2678 } 2679 /* fall through */ 2680 case USB_SPEED_LOW: 2681 case USB_SPEED_FULL: 2682 case USB_SPEED_HIGH: 2683 set_field(&port->portsc, PLS_U0, PORTSC_PLS); 2684 trace_usb_xhci_port_link(port->portnr, PLS_U0); 2685 port->portsc |= PORTSC_PED; 2686 break; 2687 } 2688 2689 port->portsc &= ~PORTSC_PR; 2690 xhci_port_notify(port, PORTSC_PRC); 2691 } 2692 2693 static void xhci_reset(DeviceState *dev) 2694 { 2695 XHCIState *xhci = XHCI(dev); 2696 int i; 2697 2698 trace_usb_xhci_reset(); 2699 if (!(xhci->usbsts & USBSTS_HCH)) { 2700 DPRINTF("xhci: reset while running!\n"); 2701 } 2702 2703 xhci->usbcmd = 0; 2704 xhci->usbsts = USBSTS_HCH; 2705 xhci->dnctrl = 0; 2706 xhci->crcr_low = 0; 2707 xhci->crcr_high = 0; 2708 xhci->dcbaap_low = 0; 2709 xhci->dcbaap_high = 0; 2710 xhci->config = 0; 2711 2712 for (i = 0; i < xhci->numslots; i++) { 2713 xhci_disable_slot(xhci, i+1); 2714 } 2715 2716 for (i = 0; i < xhci->numports; i++) { 2717 xhci_port_update(xhci->ports + i, 0); 2718 } 2719 2720 for (i = 0; i < xhci->numintrs; i++) { 2721 xhci->intr[i].iman = 0; 2722 xhci->intr[i].imod = 0; 2723 xhci->intr[i].erstsz = 0; 2724 xhci->intr[i].erstba_low = 0; 2725 xhci->intr[i].erstba_high = 0; 2726 xhci->intr[i].erdp_low = 0; 2727 xhci->intr[i].erdp_high = 0; 2728 2729 xhci->intr[i].er_ep_idx = 0; 2730 xhci->intr[i].er_pcs = 1; 2731 xhci->intr[i].ev_buffer_put = 0; 2732 xhci->intr[i].ev_buffer_get = 0; 2733 } 2734 2735 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 2736 xhci_mfwrap_update(xhci); 2737 } 2738 2739 static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size) 2740 { 2741 XHCIState *xhci = ptr; 2742 uint32_t ret; 2743 2744 switch (reg) { 2745 case 0x00: /* HCIVERSION, CAPLENGTH */ 2746 ret = 0x01000000 | LEN_CAP; 2747 break; 2748 case 0x04: /* HCSPARAMS 1 */ 2749 ret = ((xhci->numports_2+xhci->numports_3)<<24) 2750 | (xhci->numintrs<<8) | xhci->numslots; 2751 break; 2752 case 0x08: /* HCSPARAMS 2 */ 2753 ret = 0x0000000f; 2754 break; 2755 case 0x0c: /* HCSPARAMS 3 */ 2756 ret = 0x00000000; 2757 break; 2758 case 0x10: /* HCCPARAMS */ 2759 if (sizeof(dma_addr_t) == 4) { 2760 ret = 0x00080000 | (xhci->max_pstreams_mask << 12); 2761 } else { 2762 ret = 0x00080001 | (xhci->max_pstreams_mask << 12); 2763 } 2764 break; 2765 case 0x14: /* DBOFF */ 2766 ret = OFF_DOORBELL; 2767 break; 2768 case 0x18: /* RTSOFF */ 2769 ret = OFF_RUNTIME; 2770 break; 2771 2772 /* extended capabilities */ 2773 case 0x20: /* Supported Protocol:00 */ 2774 ret = 0x02000402; /* USB 2.0 */ 2775 break; 2776 case 0x24: /* Supported Protocol:04 */ 2777 ret = 0x20425355; /* "USB " */ 2778 break; 2779 case 0x28: /* Supported Protocol:08 */ 2780 ret = (xhci->numports_2 << 8) | (xhci->numports_3 + 1); 2781 break; 2782 case 0x2c: /* Supported Protocol:0c */ 2783 ret = 0x00000000; /* reserved */ 2784 break; 2785 case 0x30: /* Supported Protocol:00 */ 2786 ret = 0x03000002; /* USB 3.0 */ 2787 break; 2788 case 0x34: /* Supported Protocol:04 */ 2789 ret = 0x20425355; /* "USB " */ 2790 break; 2791 case 0x38: /* Supported Protocol:08 */ 2792 ret = (xhci->numports_3 << 8) | 1; 2793 break; 2794 case 0x3c: /* Supported Protocol:0c */ 2795 ret = 0x00000000; /* reserved */ 2796 break; 2797 default: 2798 trace_usb_xhci_unimplemented("cap read", reg); 2799 ret = 0; 2800 } 2801 2802 trace_usb_xhci_cap_read(reg, ret); 2803 return ret; 2804 } 2805 2806 static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size) 2807 { 2808 XHCIPort *port = ptr; 2809 uint32_t ret; 2810 2811 switch (reg) { 2812 case 0x00: /* PORTSC */ 2813 ret = port->portsc; 2814 break; 2815 case 0x04: /* PORTPMSC */ 2816 case 0x08: /* PORTLI */ 2817 ret = 0; 2818 break; 2819 case 0x0c: /* PORTHLPMC */ 2820 ret = 0; 2821 qemu_log_mask(LOG_UNIMP, "%s: read from port register PORTHLPMC", 2822 __func__); 2823 break; 2824 default: 2825 qemu_log_mask(LOG_GUEST_ERROR, 2826 "%s: read from port offset 0x%" HWADDR_PRIx, 2827 __func__, reg); 2828 ret = 0; 2829 } 2830 2831 trace_usb_xhci_port_read(port->portnr, reg, ret); 2832 return ret; 2833 } 2834 2835 static void xhci_port_write(void *ptr, hwaddr reg, 2836 uint64_t val, unsigned size) 2837 { 2838 XHCIPort *port = ptr; 2839 uint32_t portsc, notify; 2840 2841 trace_usb_xhci_port_write(port->portnr, reg, val); 2842 2843 switch (reg) { 2844 case 0x00: /* PORTSC */ 2845 /* write-1-to-start bits */ 2846 if (val & PORTSC_WPR) { 2847 xhci_port_reset(port, true); 2848 break; 2849 } 2850 if (val & PORTSC_PR) { 2851 xhci_port_reset(port, false); 2852 break; 2853 } 2854 2855 portsc = port->portsc; 2856 notify = 0; 2857 /* write-1-to-clear bits*/ 2858 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC| 2859 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC)); 2860 if (val & PORTSC_LWS) { 2861 /* overwrite PLS only when LWS=1 */ 2862 uint32_t old_pls = get_field(port->portsc, PORTSC_PLS); 2863 uint32_t new_pls = get_field(val, PORTSC_PLS); 2864 switch (new_pls) { 2865 case PLS_U0: 2866 if (old_pls != PLS_U0) { 2867 set_field(&portsc, new_pls, PORTSC_PLS); 2868 trace_usb_xhci_port_link(port->portnr, new_pls); 2869 notify = PORTSC_PLC; 2870 } 2871 break; 2872 case PLS_U3: 2873 if (old_pls < PLS_U3) { 2874 set_field(&portsc, new_pls, PORTSC_PLS); 2875 trace_usb_xhci_port_link(port->portnr, new_pls); 2876 } 2877 break; 2878 case PLS_RESUME: 2879 /* windows does this for some reason, don't spam stderr */ 2880 break; 2881 default: 2882 DPRINTF("%s: ignore pls write (old %d, new %d)\n", 2883 __func__, old_pls, new_pls); 2884 break; 2885 } 2886 } 2887 /* read/write bits */ 2888 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE); 2889 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE)); 2890 port->portsc = portsc; 2891 if (notify) { 2892 xhci_port_notify(port, notify); 2893 } 2894 break; 2895 case 0x04: /* PORTPMSC */ 2896 case 0x0c: /* PORTHLPMC */ 2897 qemu_log_mask(LOG_UNIMP, 2898 "%s: write 0x%" PRIx64 2899 " (%u bytes) to port register at offset 0x%" HWADDR_PRIx, 2900 __func__, val, size, reg); 2901 break; 2902 case 0x08: /* PORTLI */ 2903 qemu_log_mask(LOG_GUEST_ERROR, "%s: Write to read-only PORTLI register", 2904 __func__); 2905 break; 2906 default: 2907 qemu_log_mask(LOG_GUEST_ERROR, 2908 "%s: write 0x%" PRIx64 " (%u bytes) to unknown port " 2909 "register at offset 0x%" HWADDR_PRIx, 2910 __func__, val, size, reg); 2911 break; 2912 } 2913 } 2914 2915 static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size) 2916 { 2917 XHCIState *xhci = ptr; 2918 uint32_t ret; 2919 2920 switch (reg) { 2921 case 0x00: /* USBCMD */ 2922 ret = xhci->usbcmd; 2923 break; 2924 case 0x04: /* USBSTS */ 2925 ret = xhci->usbsts; 2926 break; 2927 case 0x08: /* PAGESIZE */ 2928 ret = 1; /* 4KiB */ 2929 break; 2930 case 0x14: /* DNCTRL */ 2931 ret = xhci->dnctrl; 2932 break; 2933 case 0x18: /* CRCR low */ 2934 ret = xhci->crcr_low & ~0xe; 2935 break; 2936 case 0x1c: /* CRCR high */ 2937 ret = xhci->crcr_high; 2938 break; 2939 case 0x30: /* DCBAAP low */ 2940 ret = xhci->dcbaap_low; 2941 break; 2942 case 0x34: /* DCBAAP high */ 2943 ret = xhci->dcbaap_high; 2944 break; 2945 case 0x38: /* CONFIG */ 2946 ret = xhci->config; 2947 break; 2948 default: 2949 trace_usb_xhci_unimplemented("oper read", reg); 2950 ret = 0; 2951 } 2952 2953 trace_usb_xhci_oper_read(reg, ret); 2954 return ret; 2955 } 2956 2957 static void xhci_oper_write(void *ptr, hwaddr reg, 2958 uint64_t val, unsigned size) 2959 { 2960 XHCIState *xhci = XHCI(ptr); 2961 2962 trace_usb_xhci_oper_write(reg, val); 2963 2964 switch (reg) { 2965 case 0x00: /* USBCMD */ 2966 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) { 2967 xhci_run(xhci); 2968 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) { 2969 xhci_stop(xhci); 2970 } 2971 if (val & USBCMD_CSS) { 2972 /* save state */ 2973 xhci->usbsts &= ~USBSTS_SRE; 2974 } 2975 if (val & USBCMD_CRS) { 2976 /* restore state */ 2977 xhci->usbsts |= USBSTS_SRE; 2978 } 2979 xhci->usbcmd = val & 0xc0f; 2980 xhci_mfwrap_update(xhci); 2981 if (val & USBCMD_HCRST) { 2982 xhci_reset(DEVICE(xhci)); 2983 } 2984 xhci_intr_update(xhci, 0); 2985 break; 2986 2987 case 0x04: /* USBSTS */ 2988 /* these bits are write-1-to-clear */ 2989 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE)); 2990 xhci_intr_update(xhci, 0); 2991 break; 2992 2993 case 0x14: /* DNCTRL */ 2994 xhci->dnctrl = val & 0xffff; 2995 break; 2996 case 0x18: /* CRCR low */ 2997 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR); 2998 break; 2999 case 0x1c: /* CRCR high */ 3000 xhci->crcr_high = val; 3001 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) { 3002 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED}; 3003 xhci->crcr_low &= ~CRCR_CRR; 3004 xhci_event(xhci, &event, 0); 3005 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low); 3006 } else { 3007 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val); 3008 xhci_ring_init(xhci, &xhci->cmd_ring, base); 3009 } 3010 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS); 3011 break; 3012 case 0x30: /* DCBAAP low */ 3013 xhci->dcbaap_low = val & 0xffffffc0; 3014 break; 3015 case 0x34: /* DCBAAP high */ 3016 xhci->dcbaap_high = val; 3017 break; 3018 case 0x38: /* CONFIG */ 3019 xhci->config = val & 0xff; 3020 break; 3021 default: 3022 trace_usb_xhci_unimplemented("oper write", reg); 3023 } 3024 } 3025 3026 static uint64_t xhci_runtime_read(void *ptr, hwaddr reg, 3027 unsigned size) 3028 { 3029 XHCIState *xhci = ptr; 3030 uint32_t ret = 0; 3031 3032 if (reg < 0x20) { 3033 switch (reg) { 3034 case 0x00: /* MFINDEX */ 3035 ret = xhci_mfindex_get(xhci) & 0x3fff; 3036 break; 3037 default: 3038 trace_usb_xhci_unimplemented("runtime read", reg); 3039 break; 3040 } 3041 } else { 3042 int v = (reg - 0x20) / 0x20; 3043 XHCIInterrupter *intr = &xhci->intr[v]; 3044 switch (reg & 0x1f) { 3045 case 0x00: /* IMAN */ 3046 ret = intr->iman; 3047 break; 3048 case 0x04: /* IMOD */ 3049 ret = intr->imod; 3050 break; 3051 case 0x08: /* ERSTSZ */ 3052 ret = intr->erstsz; 3053 break; 3054 case 0x10: /* ERSTBA low */ 3055 ret = intr->erstba_low; 3056 break; 3057 case 0x14: /* ERSTBA high */ 3058 ret = intr->erstba_high; 3059 break; 3060 case 0x18: /* ERDP low */ 3061 ret = intr->erdp_low; 3062 break; 3063 case 0x1c: /* ERDP high */ 3064 ret = intr->erdp_high; 3065 break; 3066 } 3067 } 3068 3069 trace_usb_xhci_runtime_read(reg, ret); 3070 return ret; 3071 } 3072 3073 static void xhci_runtime_write(void *ptr, hwaddr reg, 3074 uint64_t val, unsigned size) 3075 { 3076 XHCIState *xhci = ptr; 3077 XHCIInterrupter *intr; 3078 int v; 3079 3080 trace_usb_xhci_runtime_write(reg, val); 3081 3082 if (reg < 0x20) { 3083 trace_usb_xhci_unimplemented("runtime write", reg); 3084 return; 3085 } 3086 v = (reg - 0x20) / 0x20; 3087 intr = &xhci->intr[v]; 3088 3089 switch (reg & 0x1f) { 3090 case 0x00: /* IMAN */ 3091 if (val & IMAN_IP) { 3092 intr->iman &= ~IMAN_IP; 3093 } 3094 intr->iman &= ~IMAN_IE; 3095 intr->iman |= val & IMAN_IE; 3096 xhci_intr_update(xhci, v); 3097 break; 3098 case 0x04: /* IMOD */ 3099 intr->imod = val; 3100 break; 3101 case 0x08: /* ERSTSZ */ 3102 intr->erstsz = val & 0xffff; 3103 break; 3104 case 0x10: /* ERSTBA low */ 3105 if (xhci->nec_quirks) { 3106 /* NEC driver bug: it doesn't align this to 64 bytes */ 3107 intr->erstba_low = val & 0xfffffff0; 3108 } else { 3109 intr->erstba_low = val & 0xffffffc0; 3110 } 3111 break; 3112 case 0x14: /* ERSTBA high */ 3113 intr->erstba_high = val; 3114 xhci_er_reset(xhci, v); 3115 break; 3116 case 0x18: /* ERDP low */ 3117 if (val & ERDP_EHB) { 3118 intr->erdp_low &= ~ERDP_EHB; 3119 } 3120 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB); 3121 if (val & ERDP_EHB) { 3122 dma_addr_t erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 3123 unsigned int dp_idx = (erdp - intr->er_start) / TRB_SIZE; 3124 if (erdp >= intr->er_start && 3125 erdp < (intr->er_start + TRB_SIZE * intr->er_size) && 3126 dp_idx != intr->er_ep_idx) { 3127 xhci_intr_raise(xhci, v); 3128 } 3129 } 3130 break; 3131 case 0x1c: /* ERDP high */ 3132 intr->erdp_high = val; 3133 break; 3134 default: 3135 trace_usb_xhci_unimplemented("oper write", reg); 3136 } 3137 } 3138 3139 static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg, 3140 unsigned size) 3141 { 3142 /* doorbells always read as 0 */ 3143 trace_usb_xhci_doorbell_read(reg, 0); 3144 return 0; 3145 } 3146 3147 static void xhci_doorbell_write(void *ptr, hwaddr reg, 3148 uint64_t val, unsigned size) 3149 { 3150 XHCIState *xhci = ptr; 3151 unsigned int epid, streamid; 3152 3153 trace_usb_xhci_doorbell_write(reg, val); 3154 3155 if (!xhci_running(xhci)) { 3156 DPRINTF("xhci: wrote doorbell while xHC stopped or paused\n"); 3157 return; 3158 } 3159 3160 reg >>= 2; 3161 3162 if (reg == 0) { 3163 if (val == 0) { 3164 xhci_process_commands(xhci); 3165 } else { 3166 DPRINTF("xhci: bad doorbell 0 write: 0x%x\n", 3167 (uint32_t)val); 3168 } 3169 } else { 3170 epid = val & 0xff; 3171 streamid = (val >> 16) & 0xffff; 3172 if (reg > xhci->numslots) { 3173 DPRINTF("xhci: bad doorbell %d\n", (int)reg); 3174 } else if (epid == 0 || epid > 31) { 3175 DPRINTF("xhci: bad doorbell %d write: 0x%x\n", 3176 (int)reg, (uint32_t)val); 3177 } else { 3178 xhci_kick_ep(xhci, reg, epid, streamid); 3179 } 3180 } 3181 } 3182 3183 static void xhci_cap_write(void *opaque, hwaddr addr, uint64_t val, 3184 unsigned width) 3185 { 3186 /* nothing */ 3187 } 3188 3189 static const MemoryRegionOps xhci_cap_ops = { 3190 .read = xhci_cap_read, 3191 .write = xhci_cap_write, 3192 .valid.min_access_size = 1, 3193 .valid.max_access_size = 4, 3194 .impl.min_access_size = 4, 3195 .impl.max_access_size = 4, 3196 .endianness = DEVICE_LITTLE_ENDIAN, 3197 }; 3198 3199 static const MemoryRegionOps xhci_oper_ops = { 3200 .read = xhci_oper_read, 3201 .write = xhci_oper_write, 3202 .valid.min_access_size = 4, 3203 .valid.max_access_size = sizeof(dma_addr_t), 3204 .endianness = DEVICE_LITTLE_ENDIAN, 3205 }; 3206 3207 static const MemoryRegionOps xhci_port_ops = { 3208 .read = xhci_port_read, 3209 .write = xhci_port_write, 3210 .valid.min_access_size = 4, 3211 .valid.max_access_size = 4, 3212 .endianness = DEVICE_LITTLE_ENDIAN, 3213 }; 3214 3215 static const MemoryRegionOps xhci_runtime_ops = { 3216 .read = xhci_runtime_read, 3217 .write = xhci_runtime_write, 3218 .valid.min_access_size = 4, 3219 .valid.max_access_size = sizeof(dma_addr_t), 3220 .endianness = DEVICE_LITTLE_ENDIAN, 3221 }; 3222 3223 static const MemoryRegionOps xhci_doorbell_ops = { 3224 .read = xhci_doorbell_read, 3225 .write = xhci_doorbell_write, 3226 .valid.min_access_size = 4, 3227 .valid.max_access_size = 4, 3228 .endianness = DEVICE_LITTLE_ENDIAN, 3229 }; 3230 3231 static void xhci_attach(USBPort *usbport) 3232 { 3233 XHCIState *xhci = usbport->opaque; 3234 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3235 3236 xhci_port_update(port, 0); 3237 } 3238 3239 static void xhci_detach(USBPort *usbport) 3240 { 3241 XHCIState *xhci = usbport->opaque; 3242 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3243 3244 xhci_detach_slot(xhci, usbport); 3245 xhci_port_update(port, 1); 3246 } 3247 3248 static void xhci_wakeup(USBPort *usbport) 3249 { 3250 XHCIState *xhci = usbport->opaque; 3251 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3252 3253 assert(port); 3254 if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) { 3255 return; 3256 } 3257 set_field(&port->portsc, PLS_RESUME, PORTSC_PLS); 3258 xhci_port_notify(port, PORTSC_PLC); 3259 } 3260 3261 static void xhci_complete(USBPort *port, USBPacket *packet) 3262 { 3263 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet); 3264 3265 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { 3266 xhci_ep_nuke_one_xfer(xfer, 0); 3267 return; 3268 } 3269 xhci_try_complete_packet(xfer); 3270 xhci_kick_epctx(xfer->epctx, xfer->streamid); 3271 if (xfer->complete) { 3272 xhci_ep_free_xfer(xfer); 3273 } 3274 } 3275 3276 static void xhci_child_detach(USBPort *uport, USBDevice *child) 3277 { 3278 USBBus *bus = usb_bus_from_device(child); 3279 XHCIState *xhci = container_of(bus, XHCIState, bus); 3280 3281 xhci_detach_slot(xhci, child->port); 3282 } 3283 3284 static USBPortOps xhci_uport_ops = { 3285 .attach = xhci_attach, 3286 .detach = xhci_detach, 3287 .wakeup = xhci_wakeup, 3288 .complete = xhci_complete, 3289 .child_detach = xhci_child_detach, 3290 }; 3291 3292 static int xhci_find_epid(USBEndpoint *ep) 3293 { 3294 if (ep->nr == 0) { 3295 return 1; 3296 } 3297 if (ep->pid == USB_TOKEN_IN) { 3298 return ep->nr * 2 + 1; 3299 } else { 3300 return ep->nr * 2; 3301 } 3302 } 3303 3304 static USBEndpoint *xhci_epid_to_usbep(XHCIEPContext *epctx) 3305 { 3306 USBPort *uport; 3307 uint32_t token; 3308 3309 if (!epctx) { 3310 return NULL; 3311 } 3312 uport = epctx->xhci->slots[epctx->slotid - 1].uport; 3313 if (!uport || !uport->dev) { 3314 return NULL; 3315 } 3316 token = (epctx->epid & 1) ? USB_TOKEN_IN : USB_TOKEN_OUT; 3317 return usb_ep_get(uport->dev, token, epctx->epid >> 1); 3318 } 3319 3320 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep, 3321 unsigned int stream) 3322 { 3323 XHCIState *xhci = container_of(bus, XHCIState, bus); 3324 int slotid; 3325 3326 DPRINTF("%s\n", __func__); 3327 slotid = ep->dev->addr; 3328 if (slotid == 0 || slotid > xhci->numslots || 3329 !xhci->slots[slotid - 1].enabled) { 3330 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr); 3331 return; 3332 } 3333 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep), stream); 3334 } 3335 3336 static USBBusOps xhci_bus_ops = { 3337 .wakeup_endpoint = xhci_wakeup_endpoint, 3338 }; 3339 3340 static void usb_xhci_init(XHCIState *xhci) 3341 { 3342 XHCIPort *port; 3343 unsigned int i, usbports, speedmask; 3344 3345 xhci->usbsts = USBSTS_HCH; 3346 3347 if (xhci->numports_2 > XHCI_MAXPORTS_2) { 3348 xhci->numports_2 = XHCI_MAXPORTS_2; 3349 } 3350 if (xhci->numports_3 > XHCI_MAXPORTS_3) { 3351 xhci->numports_3 = XHCI_MAXPORTS_3; 3352 } 3353 usbports = MAX(xhci->numports_2, xhci->numports_3); 3354 xhci->numports = xhci->numports_2 + xhci->numports_3; 3355 3356 usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, xhci->hostOpaque); 3357 3358 for (i = 0; i < usbports; i++) { 3359 speedmask = 0; 3360 if (i < xhci->numports_2) { 3361 port = &xhci->ports[i + xhci->numports_3]; 3362 port->portnr = i + 1 + xhci->numports_3; 3363 port->uport = &xhci->uports[i]; 3364 port->speedmask = 3365 USB_SPEED_MASK_LOW | 3366 USB_SPEED_MASK_FULL | 3367 USB_SPEED_MASK_HIGH; 3368 assert(i < XHCI_MAXPORTS); 3369 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1); 3370 speedmask |= port->speedmask; 3371 } 3372 if (i < xhci->numports_3) { 3373 port = &xhci->ports[i]; 3374 port->portnr = i + 1; 3375 port->uport = &xhci->uports[i]; 3376 port->speedmask = USB_SPEED_MASK_SUPER; 3377 assert(i < XHCI_MAXPORTS); 3378 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1); 3379 speedmask |= port->speedmask; 3380 } 3381 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i, 3382 &xhci_uport_ops, speedmask); 3383 } 3384 } 3385 3386 static void usb_xhci_realize(DeviceState *dev, Error **errp) 3387 { 3388 int i; 3389 3390 XHCIState *xhci = XHCI(dev); 3391 3392 if (xhci->numintrs > XHCI_MAXINTRS) { 3393 xhci->numintrs = XHCI_MAXINTRS; 3394 } 3395 while (xhci->numintrs & (xhci->numintrs - 1)) { /* ! power of 2 */ 3396 xhci->numintrs++; 3397 } 3398 if (xhci->numintrs < 1) { 3399 xhci->numintrs = 1; 3400 } 3401 if (xhci->numslots > XHCI_MAXSLOTS) { 3402 xhci->numslots = XHCI_MAXSLOTS; 3403 } 3404 if (xhci->numslots < 1) { 3405 xhci->numslots = 1; 3406 } 3407 if (xhci_get_flag(xhci, XHCI_FLAG_ENABLE_STREAMS)) { 3408 xhci->max_pstreams_mask = 7; /* == 256 primary streams */ 3409 } else { 3410 xhci->max_pstreams_mask = 0; 3411 } 3412 3413 usb_xhci_init(xhci); 3414 xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci); 3415 3416 memory_region_init(&xhci->mem, OBJECT(dev), "xhci", XHCI_LEN_REGS); 3417 memory_region_init_io(&xhci->mem_cap, OBJECT(dev), &xhci_cap_ops, xhci, 3418 "capabilities", LEN_CAP); 3419 memory_region_init_io(&xhci->mem_oper, OBJECT(dev), &xhci_oper_ops, xhci, 3420 "operational", 0x400); 3421 memory_region_init_io(&xhci->mem_runtime, OBJECT(dev), &xhci_runtime_ops, 3422 xhci, "runtime", LEN_RUNTIME); 3423 memory_region_init_io(&xhci->mem_doorbell, OBJECT(dev), &xhci_doorbell_ops, 3424 xhci, "doorbell", LEN_DOORBELL); 3425 3426 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap); 3427 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper); 3428 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime); 3429 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell); 3430 3431 for (i = 0; i < xhci->numports; i++) { 3432 XHCIPort *port = &xhci->ports[i]; 3433 uint32_t offset = OFF_OPER + 0x400 + 0x10 * i; 3434 port->xhci = xhci; 3435 memory_region_init_io(&port->mem, OBJECT(dev), &xhci_port_ops, port, 3436 port->name, 0x10); 3437 memory_region_add_subregion(&xhci->mem, offset, &port->mem); 3438 } 3439 } 3440 3441 static void usb_xhci_unrealize(DeviceState *dev) 3442 { 3443 int i; 3444 XHCIState *xhci = XHCI(dev); 3445 3446 trace_usb_xhci_exit(); 3447 3448 for (i = 0; i < xhci->numslots; i++) { 3449 xhci_disable_slot(xhci, i + 1); 3450 } 3451 3452 if (xhci->mfwrap_timer) { 3453 timer_free(xhci->mfwrap_timer); 3454 xhci->mfwrap_timer = NULL; 3455 } 3456 3457 memory_region_del_subregion(&xhci->mem, &xhci->mem_cap); 3458 memory_region_del_subregion(&xhci->mem, &xhci->mem_oper); 3459 memory_region_del_subregion(&xhci->mem, &xhci->mem_runtime); 3460 memory_region_del_subregion(&xhci->mem, &xhci->mem_doorbell); 3461 3462 for (i = 0; i < xhci->numports; i++) { 3463 XHCIPort *port = &xhci->ports[i]; 3464 memory_region_del_subregion(&xhci->mem, &port->mem); 3465 } 3466 3467 usb_bus_release(&xhci->bus); 3468 } 3469 3470 static int usb_xhci_post_load(void *opaque, int version_id) 3471 { 3472 XHCIState *xhci = opaque; 3473 XHCISlot *slot; 3474 XHCIEPContext *epctx; 3475 dma_addr_t dcbaap, pctx; 3476 uint32_t slot_ctx[4]; 3477 uint32_t ep_ctx[5]; 3478 int slotid, epid, state; 3479 uint64_t addr; 3480 3481 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 3482 3483 for (slotid = 1; slotid <= xhci->numslots; slotid++) { 3484 slot = &xhci->slots[slotid-1]; 3485 if (!slot->addressed) { 3486 continue; 3487 } 3488 ldq_le_dma(xhci->as, dcbaap + 8 * slotid, &addr, MEMTXATTRS_UNSPECIFIED); 3489 slot->ctx = xhci_mask64(addr); 3490 3491 xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx)); 3492 slot->uport = xhci_lookup_uport(xhci, slot_ctx); 3493 if (!slot->uport) { 3494 /* should not happen, but may trigger on guest bugs */ 3495 slot->enabled = 0; 3496 slot->addressed = 0; 3497 continue; 3498 } 3499 assert(slot->uport && slot->uport->dev); 3500 3501 for (epid = 1; epid <= 31; epid++) { 3502 pctx = slot->ctx + 32 * epid; 3503 xhci_dma_read_u32s(xhci, pctx, ep_ctx, sizeof(ep_ctx)); 3504 state = ep_ctx[0] & EP_STATE_MASK; 3505 if (state == EP_DISABLED) { 3506 continue; 3507 } 3508 epctx = xhci_alloc_epctx(xhci, slotid, epid); 3509 slot->eps[epid-1] = epctx; 3510 xhci_init_epctx(epctx, pctx, ep_ctx); 3511 epctx->state = state; 3512 if (state == EP_RUNNING) { 3513 /* kick endpoint after vmload is finished */ 3514 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 3515 } 3516 } 3517 } 3518 return 0; 3519 } 3520 3521 static const VMStateDescription vmstate_xhci_ring = { 3522 .name = "xhci-ring", 3523 .version_id = 1, 3524 .fields = (const VMStateField[]) { 3525 VMSTATE_UINT64(dequeue, XHCIRing), 3526 VMSTATE_BOOL(ccs, XHCIRing), 3527 VMSTATE_END_OF_LIST() 3528 } 3529 }; 3530 3531 static const VMStateDescription vmstate_xhci_port = { 3532 .name = "xhci-port", 3533 .version_id = 1, 3534 .fields = (const VMStateField[]) { 3535 VMSTATE_UINT32(portsc, XHCIPort), 3536 VMSTATE_END_OF_LIST() 3537 } 3538 }; 3539 3540 static const VMStateDescription vmstate_xhci_slot = { 3541 .name = "xhci-slot", 3542 .version_id = 1, 3543 .fields = (const VMStateField[]) { 3544 VMSTATE_BOOL(enabled, XHCISlot), 3545 VMSTATE_BOOL(addressed, XHCISlot), 3546 VMSTATE_END_OF_LIST() 3547 } 3548 }; 3549 3550 static const VMStateDescription vmstate_xhci_event = { 3551 .name = "xhci-event", 3552 .version_id = 1, 3553 .fields = (const VMStateField[]) { 3554 VMSTATE_UINT32(type, XHCIEvent), 3555 VMSTATE_UINT32(ccode, XHCIEvent), 3556 VMSTATE_UINT64(ptr, XHCIEvent), 3557 VMSTATE_UINT32(length, XHCIEvent), 3558 VMSTATE_UINT32(flags, XHCIEvent), 3559 VMSTATE_UINT8(slotid, XHCIEvent), 3560 VMSTATE_UINT8(epid, XHCIEvent), 3561 VMSTATE_END_OF_LIST() 3562 } 3563 }; 3564 3565 static bool xhci_er_full(void *opaque, int version_id) 3566 { 3567 return false; 3568 } 3569 3570 static const VMStateDescription vmstate_xhci_intr = { 3571 .name = "xhci-intr", 3572 .version_id = 1, 3573 .fields = (const VMStateField[]) { 3574 /* registers */ 3575 VMSTATE_UINT32(iman, XHCIInterrupter), 3576 VMSTATE_UINT32(imod, XHCIInterrupter), 3577 VMSTATE_UINT32(erstsz, XHCIInterrupter), 3578 VMSTATE_UINT32(erstba_low, XHCIInterrupter), 3579 VMSTATE_UINT32(erstba_high, XHCIInterrupter), 3580 VMSTATE_UINT32(erdp_low, XHCIInterrupter), 3581 VMSTATE_UINT32(erdp_high, XHCIInterrupter), 3582 3583 /* state */ 3584 VMSTATE_BOOL(msix_used, XHCIInterrupter), 3585 VMSTATE_BOOL(er_pcs, XHCIInterrupter), 3586 VMSTATE_UINT64(er_start, XHCIInterrupter), 3587 VMSTATE_UINT32(er_size, XHCIInterrupter), 3588 VMSTATE_UINT32(er_ep_idx, XHCIInterrupter), 3589 3590 /* event queue (used if ring is full) */ 3591 VMSTATE_BOOL(er_full_unused, XHCIInterrupter), 3592 VMSTATE_UINT32_TEST(ev_buffer_put, XHCIInterrupter, xhci_er_full), 3593 VMSTATE_UINT32_TEST(ev_buffer_get, XHCIInterrupter, xhci_er_full), 3594 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer, XHCIInterrupter, EV_QUEUE, 3595 xhci_er_full, 1, 3596 vmstate_xhci_event, XHCIEvent), 3597 3598 VMSTATE_END_OF_LIST() 3599 } 3600 }; 3601 3602 const VMStateDescription vmstate_xhci = { 3603 .name = "xhci-core", 3604 .version_id = 1, 3605 .post_load = usb_xhci_post_load, 3606 .fields = (const VMStateField[]) { 3607 VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1, 3608 vmstate_xhci_port, XHCIPort), 3609 VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1, 3610 vmstate_xhci_slot, XHCISlot), 3611 VMSTATE_STRUCT_VARRAY_UINT32(intr, XHCIState, numintrs, 1, 3612 vmstate_xhci_intr, XHCIInterrupter), 3613 3614 /* Operational Registers */ 3615 VMSTATE_UINT32(usbcmd, XHCIState), 3616 VMSTATE_UINT32(usbsts, XHCIState), 3617 VMSTATE_UINT32(dnctrl, XHCIState), 3618 VMSTATE_UINT32(crcr_low, XHCIState), 3619 VMSTATE_UINT32(crcr_high, XHCIState), 3620 VMSTATE_UINT32(dcbaap_low, XHCIState), 3621 VMSTATE_UINT32(dcbaap_high, XHCIState), 3622 VMSTATE_UINT32(config, XHCIState), 3623 3624 /* Runtime Registers & state */ 3625 VMSTATE_INT64(mfindex_start, XHCIState), 3626 VMSTATE_TIMER_PTR(mfwrap_timer, XHCIState), 3627 VMSTATE_STRUCT(cmd_ring, XHCIState, 1, vmstate_xhci_ring, XHCIRing), 3628 3629 VMSTATE_END_OF_LIST() 3630 } 3631 }; 3632 3633 static const Property xhci_properties[] = { 3634 DEFINE_PROP_BIT("streams", XHCIState, flags, 3635 XHCI_FLAG_ENABLE_STREAMS, true), 3636 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4), 3637 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4), 3638 DEFINE_PROP_LINK("host", XHCIState, hostOpaque, TYPE_DEVICE, 3639 DeviceState *), 3640 }; 3641 3642 static void xhci_class_init(ObjectClass *klass, const void *data) 3643 { 3644 DeviceClass *dc = DEVICE_CLASS(klass); 3645 3646 dc->realize = usb_xhci_realize; 3647 dc->unrealize = usb_xhci_unrealize; 3648 device_class_set_legacy_reset(dc, xhci_reset); 3649 device_class_set_props(dc, xhci_properties); 3650 dc->user_creatable = false; 3651 } 3652 3653 static const TypeInfo xhci_info = { 3654 .name = TYPE_XHCI, 3655 .parent = TYPE_DEVICE, 3656 .instance_size = sizeof(XHCIState), 3657 .class_init = xhci_class_init, 3658 }; 3659 3660 static void xhci_register_types(void) 3661 { 3662 type_register_static(&xhci_info); 3663 } 3664 3665 type_init(xhci_register_types) 3666