1 /* 2 * USB xHCI controller with PCI bus emulation 3 * 4 * SPDX-FileCopyrightText: 2011 Securiforest 5 * SPDX-FileContributor: Hector Martin <hector@marcansoft.com> 6 * SPDX-sourceInfo: Based on usb-ohci.c, emulates Renesas NEC USB 3.0 7 * SPDX-FileCopyrightText: 2020 Xilinx 8 * SPDX-FileContributor: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> 9 * SPDX-sourceInfo: Moved the pci specific content for hcd-xhci.c to 10 * hcd-xhci-pci.c 11 * 12 * This library is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU Lesser General Public 14 * License as published by the Free Software Foundation; either 15 * version 2.1 of the License, or (at your option) any later version. 16 * 17 * This library is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * Lesser General Public License for more details. 21 * 22 * You should have received a copy of the GNU Lesser General Public 23 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 24 */ 25 #include "qemu/osdep.h" 26 #include "hw/pci/pci.h" 27 #include "hw/qdev-properties.h" 28 #include "migration/vmstate.h" 29 #include "hw/pci/msi.h" 30 #include "hw/pci/msix.h" 31 #include "hcd-xhci-pci.h" 32 #include "trace.h" 33 #include "qapi/error.h" 34 35 #define OFF_MSIX_TABLE 0x3000 36 #define OFF_MSIX_PBA 0x3800 37 38 static void xhci_pci_intr_update(XHCIState *xhci, int n, bool enable) 39 { 40 XHCIPciState *s = container_of(xhci, XHCIPciState, xhci); 41 PCIDevice *pci_dev = PCI_DEVICE(s); 42 43 if (!msix_enabled(pci_dev)) { 44 return; 45 } 46 if (enable == !!xhci->intr[n].msix_used) { 47 return; 48 } 49 if (enable) { 50 trace_usb_xhci_irq_msix_use(n); 51 msix_vector_use(pci_dev, n); 52 xhci->intr[n].msix_used = true; 53 } else { 54 trace_usb_xhci_irq_msix_unuse(n); 55 msix_vector_unuse(pci_dev, n); 56 xhci->intr[n].msix_used = false; 57 } 58 } 59 60 static bool xhci_pci_intr_raise(XHCIState *xhci, int n, bool level) 61 { 62 XHCIPciState *s = container_of(xhci, XHCIPciState, xhci); 63 PCIDevice *pci_dev = PCI_DEVICE(s); 64 65 if (n == 0 && 66 !(msix_enabled(pci_dev) || 67 msi_enabled(pci_dev))) { 68 pci_set_irq(pci_dev, level); 69 } 70 71 if (msix_enabled(pci_dev) && level) { 72 msix_notify(pci_dev, n); 73 return true; 74 } 75 76 if (msi_enabled(pci_dev) && level) { 77 msi_notify(pci_dev, n); 78 return true; 79 } 80 81 return false; 82 } 83 84 static void xhci_pci_reset(DeviceState *dev) 85 { 86 XHCIPciState *s = XHCI_PCI(dev); 87 88 device_cold_reset(DEVICE(&s->xhci)); 89 } 90 91 static int xhci_pci_vmstate_post_load(void *opaque, int version_id) 92 { 93 XHCIPciState *s = XHCI_PCI(opaque); 94 PCIDevice *pci_dev = PCI_DEVICE(s); 95 int intr; 96 97 for (intr = 0; intr < s->xhci.numintrs; intr++) { 98 if (s->xhci.intr[intr].msix_used) { 99 msix_vector_use(pci_dev, intr); 100 } else { 101 msix_vector_unuse(pci_dev, intr); 102 } 103 } 104 return 0; 105 } 106 107 static void usb_xhci_pci_realize(struct PCIDevice *dev, Error **errp) 108 { 109 int ret; 110 Error *err = NULL; 111 XHCIPciState *s = XHCI_PCI(dev); 112 113 dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */ 114 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ 115 dev->config[PCI_CACHE_LINE_SIZE] = 0x10; 116 dev->config[0x60] = 0x30; /* release number */ 117 118 object_property_set_link(OBJECT(&s->xhci), "host", OBJECT(s), NULL); 119 s->xhci.intr_update = xhci_pci_intr_update; 120 s->xhci.intr_raise = xhci_pci_intr_raise; 121 if (!qdev_realize(DEVICE(&s->xhci), NULL, errp)) { 122 return; 123 } 124 if (strcmp(object_get_typename(OBJECT(dev)), TYPE_NEC_XHCI) == 0) { 125 s->xhci.nec_quirks = true; 126 } 127 128 if (s->msi != ON_OFF_AUTO_OFF) { 129 ret = msi_init(dev, 0x70, s->xhci.numintrs, true, false, &err); 130 /* 131 * Any error other than -ENOTSUP(board's MSI support is broken) 132 * is a programming error 133 */ 134 assert(!ret || ret == -ENOTSUP); 135 if (ret && s->msi == ON_OFF_AUTO_ON) { 136 /* Can't satisfy user's explicit msi=on request, fail */ 137 error_append_hint(&err, "You have to use msi=auto (default) or " 138 "msi=off with this machine type.\n"); 139 error_propagate(errp, err); 140 return; 141 } 142 assert(!err || s->msi == ON_OFF_AUTO_AUTO); 143 /* With msi=auto, we fall back to MSI off silently */ 144 error_free(err); 145 } 146 pci_register_bar(dev, 0, 147 PCI_BASE_ADDRESS_SPACE_MEMORY | 148 PCI_BASE_ADDRESS_MEM_TYPE_64, 149 &s->xhci.mem); 150 151 if (pci_bus_is_express(pci_get_bus(dev))) { 152 ret = pcie_endpoint_cap_init(dev, 0xa0); 153 assert(ret > 0); 154 } 155 156 if (s->msix != ON_OFF_AUTO_OFF) { 157 /* TODO check for errors, and should fail when msix=on */ 158 msix_init(dev, s->xhci.numintrs, 159 &s->xhci.mem, 0, OFF_MSIX_TABLE, 160 &s->xhci.mem, 0, OFF_MSIX_PBA, 161 0x90, NULL); 162 } 163 s->xhci.as = pci_get_address_space(dev); 164 } 165 166 static void usb_xhci_pci_exit(PCIDevice *dev) 167 { 168 XHCIPciState *s = XHCI_PCI(dev); 169 /* destroy msix memory region */ 170 if (dev->msix_table && dev->msix_pba 171 && dev->msix_entry_used) { 172 msix_uninit(dev, &s->xhci.mem, &s->xhci.mem); 173 } 174 } 175 176 static const VMStateDescription vmstate_xhci_pci = { 177 .name = "xhci", 178 .version_id = 1, 179 .post_load = xhci_pci_vmstate_post_load, 180 .fields = (const VMStateField[]) { 181 VMSTATE_PCI_DEVICE(parent_obj, XHCIPciState), 182 VMSTATE_MSIX(parent_obj, XHCIPciState), 183 VMSTATE_STRUCT(xhci, XHCIPciState, 1, vmstate_xhci, XHCIState), 184 VMSTATE_END_OF_LIST() 185 } 186 }; 187 188 static void xhci_instance_init(Object *obj) 189 { 190 XHCIPciState *s = XHCI_PCI(obj); 191 /* 192 * QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU command 193 * line, therefore, no need to wait to realize like other devices 194 */ 195 PCI_DEVICE(obj)->cap_present |= QEMU_PCI_CAP_EXPRESS; 196 object_initialize_child(obj, "xhci-core", &s->xhci, TYPE_XHCI); 197 qdev_alias_all_properties(DEVICE(&s->xhci), obj); 198 } 199 200 static const Property xhci_pci_properties[] = { 201 DEFINE_PROP_ON_OFF_AUTO("msi", XHCIPciState, msi, ON_OFF_AUTO_AUTO), 202 DEFINE_PROP_ON_OFF_AUTO("msix", XHCIPciState, msix, ON_OFF_AUTO_AUTO), 203 }; 204 205 static void xhci_class_init(ObjectClass *klass, void *data) 206 { 207 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 208 DeviceClass *dc = DEVICE_CLASS(klass); 209 210 device_class_set_legacy_reset(dc, xhci_pci_reset); 211 dc->vmsd = &vmstate_xhci_pci; 212 set_bit(DEVICE_CATEGORY_USB, dc->categories); 213 k->realize = usb_xhci_pci_realize; 214 k->exit = usb_xhci_pci_exit; 215 k->class_id = PCI_CLASS_SERIAL_USB; 216 device_class_set_props(dc, xhci_pci_properties); 217 } 218 219 static const TypeInfo xhci_pci_info = { 220 .name = TYPE_XHCI_PCI, 221 .parent = TYPE_PCI_DEVICE, 222 .instance_size = sizeof(XHCIPciState), 223 .class_init = xhci_class_init, 224 .instance_init = xhci_instance_init, 225 .abstract = true, 226 .interfaces = (InterfaceInfo[]) { 227 { INTERFACE_PCIE_DEVICE }, 228 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 229 { } 230 }, 231 }; 232 233 static void qemu_xhci_class_init(ObjectClass *klass, void *data) 234 { 235 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 236 237 k->vendor_id = PCI_VENDOR_ID_REDHAT; 238 k->device_id = PCI_DEVICE_ID_REDHAT_XHCI; 239 k->revision = 0x01; 240 } 241 242 static void qemu_xhci_instance_init(Object *obj) 243 { 244 XHCIPciState *s = XHCI_PCI(obj); 245 XHCIState *xhci = &s->xhci; 246 247 s->msi = ON_OFF_AUTO_OFF; 248 s->msix = ON_OFF_AUTO_AUTO; 249 xhci->numintrs = XHCI_MAXINTRS; 250 xhci->numslots = XHCI_MAXSLOTS; 251 } 252 253 static const TypeInfo qemu_xhci_info = { 254 .name = TYPE_QEMU_XHCI, 255 .parent = TYPE_XHCI_PCI, 256 .class_init = qemu_xhci_class_init, 257 .instance_init = qemu_xhci_instance_init, 258 }; 259 260 static void xhci_register_types(void) 261 { 262 type_register_static(&xhci_pci_info); 263 type_register_static(&qemu_xhci_info); 264 } 265 266 type_init(xhci_register_types) 267