1 /* 2 * USB UHCI controller emulation 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Copyright (c) 2008 Max Krasnyansky 7 * Magor rewrite of the UHCI data structures parser and frame processor 8 * Support for fully async operation and multiple outstanding transactions 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy 11 * of this software and associated documentation files (the "Software"), to deal 12 * in the Software without restriction, including without limitation the rights 13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 14 * copies of the Software, and to permit persons to whom the Software is 15 * furnished to do so, subject to the following conditions: 16 * 17 * The above copyright notice and this permission notice shall be included in 18 * all copies or substantial portions of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 26 * THE SOFTWARE. 27 */ 28 #include "hw/hw.h" 29 #include "hw/usb.h" 30 #include "hw/pci.h" 31 #include "qemu-timer.h" 32 #include "iov.h" 33 #include "dma.h" 34 #include "trace.h" 35 36 //#define DEBUG 37 //#define DEBUG_DUMP_DATA 38 39 #define UHCI_CMD_FGR (1 << 4) 40 #define UHCI_CMD_EGSM (1 << 3) 41 #define UHCI_CMD_GRESET (1 << 2) 42 #define UHCI_CMD_HCRESET (1 << 1) 43 #define UHCI_CMD_RS (1 << 0) 44 45 #define UHCI_STS_HCHALTED (1 << 5) 46 #define UHCI_STS_HCPERR (1 << 4) 47 #define UHCI_STS_HSERR (1 << 3) 48 #define UHCI_STS_RD (1 << 2) 49 #define UHCI_STS_USBERR (1 << 1) 50 #define UHCI_STS_USBINT (1 << 0) 51 52 #define TD_CTRL_SPD (1 << 29) 53 #define TD_CTRL_ERROR_SHIFT 27 54 #define TD_CTRL_IOS (1 << 25) 55 #define TD_CTRL_IOC (1 << 24) 56 #define TD_CTRL_ACTIVE (1 << 23) 57 #define TD_CTRL_STALL (1 << 22) 58 #define TD_CTRL_BABBLE (1 << 20) 59 #define TD_CTRL_NAK (1 << 19) 60 #define TD_CTRL_TIMEOUT (1 << 18) 61 62 #define UHCI_PORT_SUSPEND (1 << 12) 63 #define UHCI_PORT_RESET (1 << 9) 64 #define UHCI_PORT_LSDA (1 << 8) 65 #define UHCI_PORT_RD (1 << 6) 66 #define UHCI_PORT_ENC (1 << 3) 67 #define UHCI_PORT_EN (1 << 2) 68 #define UHCI_PORT_CSC (1 << 1) 69 #define UHCI_PORT_CCS (1 << 0) 70 71 #define UHCI_PORT_READ_ONLY (0x1bb) 72 #define UHCI_PORT_WRITE_CLEAR (UHCI_PORT_CSC | UHCI_PORT_ENC) 73 74 #define FRAME_TIMER_FREQ 1000 75 76 #define FRAME_MAX_LOOPS 256 77 78 #define NB_PORTS 2 79 80 enum { 81 TD_RESULT_STOP_FRAME = 10, 82 TD_RESULT_COMPLETE, 83 TD_RESULT_NEXT_QH, 84 TD_RESULT_ASYNC_START, 85 TD_RESULT_ASYNC_CONT, 86 }; 87 88 typedef struct UHCIState UHCIState; 89 typedef struct UHCIAsync UHCIAsync; 90 typedef struct UHCIQueue UHCIQueue; 91 92 /* 93 * Pending async transaction. 94 * 'packet' must be the first field because completion 95 * handler does "(UHCIAsync *) pkt" cast. 96 */ 97 98 struct UHCIAsync { 99 USBPacket packet; 100 QEMUSGList sgl; 101 UHCIQueue *queue; 102 QTAILQ_ENTRY(UHCIAsync) next; 103 uint32_t td; 104 uint8_t isoc; 105 uint8_t done; 106 }; 107 108 struct UHCIQueue { 109 uint32_t token; 110 UHCIState *uhci; 111 QTAILQ_ENTRY(UHCIQueue) next; 112 QTAILQ_HEAD(, UHCIAsync) asyncs; 113 int8_t valid; 114 }; 115 116 typedef struct UHCIPort { 117 USBPort port; 118 uint16_t ctrl; 119 } UHCIPort; 120 121 struct UHCIState { 122 PCIDevice dev; 123 MemoryRegion io_bar; 124 USBBus bus; /* Note unused when we're a companion controller */ 125 uint16_t cmd; /* cmd register */ 126 uint16_t status; 127 uint16_t intr; /* interrupt enable register */ 128 uint16_t frnum; /* frame number */ 129 uint32_t fl_base_addr; /* frame list base address */ 130 uint8_t sof_timing; 131 uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */ 132 int64_t expire_time; 133 QEMUTimer *frame_timer; 134 UHCIPort ports[NB_PORTS]; 135 136 /* Interrupts that should be raised at the end of the current frame. */ 137 uint32_t pending_int_mask; 138 139 /* Active packets */ 140 QTAILQ_HEAD(, UHCIQueue) queues; 141 uint8_t num_ports_vmstate; 142 143 /* Properties */ 144 char *masterbus; 145 uint32_t firstport; 146 }; 147 148 typedef struct UHCI_TD { 149 uint32_t link; 150 uint32_t ctrl; /* see TD_CTRL_xxx */ 151 uint32_t token; 152 uint32_t buffer; 153 } UHCI_TD; 154 155 typedef struct UHCI_QH { 156 uint32_t link; 157 uint32_t el_link; 158 } UHCI_QH; 159 160 static inline int32_t uhci_queue_token(UHCI_TD *td) 161 { 162 /* covers ep, dev, pid -> identifies the endpoint */ 163 return td->token & 0x7ffff; 164 } 165 166 static UHCIQueue *uhci_queue_get(UHCIState *s, UHCI_TD *td) 167 { 168 uint32_t token = uhci_queue_token(td); 169 UHCIQueue *queue; 170 171 QTAILQ_FOREACH(queue, &s->queues, next) { 172 if (queue->token == token) { 173 return queue; 174 } 175 } 176 177 queue = g_new0(UHCIQueue, 1); 178 queue->uhci = s; 179 queue->token = token; 180 QTAILQ_INIT(&queue->asyncs); 181 QTAILQ_INSERT_HEAD(&s->queues, queue, next); 182 trace_usb_uhci_queue_add(queue->token); 183 return queue; 184 } 185 186 static void uhci_queue_free(UHCIQueue *queue) 187 { 188 UHCIState *s = queue->uhci; 189 190 trace_usb_uhci_queue_del(queue->token); 191 QTAILQ_REMOVE(&s->queues, queue, next); 192 g_free(queue); 193 } 194 195 static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t addr) 196 { 197 UHCIAsync *async = g_new0(UHCIAsync, 1); 198 199 async->queue = queue; 200 async->td = addr; 201 usb_packet_init(&async->packet); 202 pci_dma_sglist_init(&async->sgl, &queue->uhci->dev, 1); 203 trace_usb_uhci_packet_add(async->queue->token, async->td); 204 205 return async; 206 } 207 208 static void uhci_async_free(UHCIAsync *async) 209 { 210 trace_usb_uhci_packet_del(async->queue->token, async->td); 211 usb_packet_cleanup(&async->packet); 212 qemu_sglist_destroy(&async->sgl); 213 g_free(async); 214 } 215 216 static void uhci_async_link(UHCIAsync *async) 217 { 218 UHCIQueue *queue = async->queue; 219 QTAILQ_INSERT_TAIL(&queue->asyncs, async, next); 220 trace_usb_uhci_packet_link_async(async->queue->token, async->td); 221 } 222 223 static void uhci_async_unlink(UHCIAsync *async) 224 { 225 UHCIQueue *queue = async->queue; 226 QTAILQ_REMOVE(&queue->asyncs, async, next); 227 trace_usb_uhci_packet_unlink_async(async->queue->token, async->td); 228 } 229 230 static void uhci_async_cancel(UHCIAsync *async) 231 { 232 trace_usb_uhci_packet_cancel(async->queue->token, async->td, async->done); 233 if (!async->done) 234 usb_cancel_packet(&async->packet); 235 uhci_async_free(async); 236 } 237 238 /* 239 * Mark all outstanding async packets as invalid. 240 * This is used for canceling them when TDs are removed by the HCD. 241 */ 242 static void uhci_async_validate_begin(UHCIState *s) 243 { 244 UHCIQueue *queue; 245 246 QTAILQ_FOREACH(queue, &s->queues, next) { 247 queue->valid--; 248 } 249 } 250 251 /* 252 * Cancel async packets that are no longer valid 253 */ 254 static void uhci_async_validate_end(UHCIState *s) 255 { 256 UHCIQueue *queue, *n; 257 UHCIAsync *async; 258 259 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 260 if (queue->valid > 0) { 261 continue; 262 } 263 while (!QTAILQ_EMPTY(&queue->asyncs)) { 264 async = QTAILQ_FIRST(&queue->asyncs); 265 uhci_async_unlink(async); 266 uhci_async_cancel(async); 267 } 268 uhci_queue_free(queue); 269 } 270 } 271 272 static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev) 273 { 274 UHCIQueue *queue; 275 UHCIAsync *curr, *n; 276 277 QTAILQ_FOREACH(queue, &s->queues, next) { 278 QTAILQ_FOREACH_SAFE(curr, &queue->asyncs, next, n) { 279 if (!usb_packet_is_inflight(&curr->packet) || 280 curr->packet.ep->dev != dev) { 281 continue; 282 } 283 uhci_async_unlink(curr); 284 uhci_async_cancel(curr); 285 } 286 } 287 } 288 289 static void uhci_async_cancel_all(UHCIState *s) 290 { 291 UHCIQueue *queue; 292 UHCIAsync *curr, *n; 293 294 QTAILQ_FOREACH(queue, &s->queues, next) { 295 QTAILQ_FOREACH_SAFE(curr, &queue->asyncs, next, n) { 296 uhci_async_unlink(curr); 297 uhci_async_cancel(curr); 298 } 299 uhci_queue_free(queue); 300 } 301 } 302 303 static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t addr, UHCI_TD *td) 304 { 305 uint32_t token = uhci_queue_token(td); 306 UHCIQueue *queue; 307 UHCIAsync *async; 308 309 QTAILQ_FOREACH(queue, &s->queues, next) { 310 if (queue->token == token) { 311 break; 312 } 313 } 314 if (queue == NULL) { 315 return NULL; 316 } 317 318 QTAILQ_FOREACH(async, &queue->asyncs, next) { 319 if (async->td == addr) { 320 return async; 321 } 322 } 323 324 return NULL; 325 } 326 327 static void uhci_update_irq(UHCIState *s) 328 { 329 int level; 330 if (((s->status2 & 1) && (s->intr & (1 << 2))) || 331 ((s->status2 & 2) && (s->intr & (1 << 3))) || 332 ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || 333 ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || 334 (s->status & UHCI_STS_HSERR) || 335 (s->status & UHCI_STS_HCPERR)) { 336 level = 1; 337 } else { 338 level = 0; 339 } 340 qemu_set_irq(s->dev.irq[3], level); 341 } 342 343 static void uhci_reset(void *opaque) 344 { 345 UHCIState *s = opaque; 346 uint8_t *pci_conf; 347 int i; 348 UHCIPort *port; 349 350 trace_usb_uhci_reset(); 351 352 pci_conf = s->dev.config; 353 354 pci_conf[0x6a] = 0x01; /* usb clock */ 355 pci_conf[0x6b] = 0x00; 356 s->cmd = 0; 357 s->status = 0; 358 s->status2 = 0; 359 s->intr = 0; 360 s->fl_base_addr = 0; 361 s->sof_timing = 64; 362 363 for(i = 0; i < NB_PORTS; i++) { 364 port = &s->ports[i]; 365 port->ctrl = 0x0080; 366 if (port->port.dev && port->port.dev->attached) { 367 usb_port_reset(&port->port); 368 } 369 } 370 371 uhci_async_cancel_all(s); 372 } 373 374 static void uhci_pre_save(void *opaque) 375 { 376 UHCIState *s = opaque; 377 378 uhci_async_cancel_all(s); 379 } 380 381 static const VMStateDescription vmstate_uhci_port = { 382 .name = "uhci port", 383 .version_id = 1, 384 .minimum_version_id = 1, 385 .minimum_version_id_old = 1, 386 .fields = (VMStateField []) { 387 VMSTATE_UINT16(ctrl, UHCIPort), 388 VMSTATE_END_OF_LIST() 389 } 390 }; 391 392 static const VMStateDescription vmstate_uhci = { 393 .name = "uhci", 394 .version_id = 2, 395 .minimum_version_id = 1, 396 .minimum_version_id_old = 1, 397 .pre_save = uhci_pre_save, 398 .fields = (VMStateField []) { 399 VMSTATE_PCI_DEVICE(dev, UHCIState), 400 VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState), 401 VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1, 402 vmstate_uhci_port, UHCIPort), 403 VMSTATE_UINT16(cmd, UHCIState), 404 VMSTATE_UINT16(status, UHCIState), 405 VMSTATE_UINT16(intr, UHCIState), 406 VMSTATE_UINT16(frnum, UHCIState), 407 VMSTATE_UINT32(fl_base_addr, UHCIState), 408 VMSTATE_UINT8(sof_timing, UHCIState), 409 VMSTATE_UINT8(status2, UHCIState), 410 VMSTATE_TIMER(frame_timer, UHCIState), 411 VMSTATE_INT64_V(expire_time, UHCIState, 2), 412 VMSTATE_END_OF_LIST() 413 } 414 }; 415 416 static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) 417 { 418 UHCIState *s = opaque; 419 420 addr &= 0x1f; 421 switch(addr) { 422 case 0x0c: 423 s->sof_timing = val; 424 break; 425 } 426 } 427 428 static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr) 429 { 430 UHCIState *s = opaque; 431 uint32_t val; 432 433 addr &= 0x1f; 434 switch(addr) { 435 case 0x0c: 436 val = s->sof_timing; 437 break; 438 default: 439 val = 0xff; 440 break; 441 } 442 return val; 443 } 444 445 static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val) 446 { 447 UHCIState *s = opaque; 448 449 addr &= 0x1f; 450 trace_usb_uhci_mmio_writew(addr, val); 451 452 switch(addr) { 453 case 0x00: 454 if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) { 455 /* start frame processing */ 456 trace_usb_uhci_schedule_start(); 457 s->expire_time = qemu_get_clock_ns(vm_clock) + 458 (get_ticks_per_sec() / FRAME_TIMER_FREQ); 459 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock)); 460 s->status &= ~UHCI_STS_HCHALTED; 461 } else if (!(val & UHCI_CMD_RS)) { 462 s->status |= UHCI_STS_HCHALTED; 463 } 464 if (val & UHCI_CMD_GRESET) { 465 UHCIPort *port; 466 int i; 467 468 /* send reset on the USB bus */ 469 for(i = 0; i < NB_PORTS; i++) { 470 port = &s->ports[i]; 471 usb_device_reset(port->port.dev); 472 } 473 uhci_reset(s); 474 return; 475 } 476 if (val & UHCI_CMD_HCRESET) { 477 uhci_reset(s); 478 return; 479 } 480 s->cmd = val; 481 break; 482 case 0x02: 483 s->status &= ~val; 484 /* XXX: the chip spec is not coherent, so we add a hidden 485 register to distinguish between IOC and SPD */ 486 if (val & UHCI_STS_USBINT) 487 s->status2 = 0; 488 uhci_update_irq(s); 489 break; 490 case 0x04: 491 s->intr = val; 492 uhci_update_irq(s); 493 break; 494 case 0x06: 495 if (s->status & UHCI_STS_HCHALTED) 496 s->frnum = val & 0x7ff; 497 break; 498 case 0x10 ... 0x1f: 499 { 500 UHCIPort *port; 501 USBDevice *dev; 502 int n; 503 504 n = (addr >> 1) & 7; 505 if (n >= NB_PORTS) 506 return; 507 port = &s->ports[n]; 508 dev = port->port.dev; 509 if (dev && dev->attached) { 510 /* port reset */ 511 if ( (val & UHCI_PORT_RESET) && 512 !(port->ctrl & UHCI_PORT_RESET) ) { 513 usb_device_reset(dev); 514 } 515 } 516 port->ctrl &= UHCI_PORT_READ_ONLY; 517 port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); 518 /* some bits are reset when a '1' is written to them */ 519 port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); 520 } 521 break; 522 } 523 } 524 525 static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr) 526 { 527 UHCIState *s = opaque; 528 uint32_t val; 529 530 addr &= 0x1f; 531 switch(addr) { 532 case 0x00: 533 val = s->cmd; 534 break; 535 case 0x02: 536 val = s->status; 537 break; 538 case 0x04: 539 val = s->intr; 540 break; 541 case 0x06: 542 val = s->frnum; 543 break; 544 case 0x10 ... 0x1f: 545 { 546 UHCIPort *port; 547 int n; 548 n = (addr >> 1) & 7; 549 if (n >= NB_PORTS) 550 goto read_default; 551 port = &s->ports[n]; 552 val = port->ctrl; 553 } 554 break; 555 default: 556 read_default: 557 val = 0xff7f; /* disabled port */ 558 break; 559 } 560 561 trace_usb_uhci_mmio_readw(addr, val); 562 563 return val; 564 } 565 566 static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val) 567 { 568 UHCIState *s = opaque; 569 570 addr &= 0x1f; 571 trace_usb_uhci_mmio_writel(addr, val); 572 573 switch(addr) { 574 case 0x08: 575 s->fl_base_addr = val & ~0xfff; 576 break; 577 } 578 } 579 580 static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr) 581 { 582 UHCIState *s = opaque; 583 uint32_t val; 584 585 addr &= 0x1f; 586 switch(addr) { 587 case 0x08: 588 val = s->fl_base_addr; 589 break; 590 default: 591 val = 0xffffffff; 592 break; 593 } 594 trace_usb_uhci_mmio_readl(addr, val); 595 return val; 596 } 597 598 /* signal resume if controller suspended */ 599 static void uhci_resume (void *opaque) 600 { 601 UHCIState *s = (UHCIState *)opaque; 602 603 if (!s) 604 return; 605 606 if (s->cmd & UHCI_CMD_EGSM) { 607 s->cmd |= UHCI_CMD_FGR; 608 s->status |= UHCI_STS_RD; 609 uhci_update_irq(s); 610 } 611 } 612 613 static void uhci_attach(USBPort *port1) 614 { 615 UHCIState *s = port1->opaque; 616 UHCIPort *port = &s->ports[port1->index]; 617 618 /* set connect status */ 619 port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; 620 621 /* update speed */ 622 if (port->port.dev->speed == USB_SPEED_LOW) { 623 port->ctrl |= UHCI_PORT_LSDA; 624 } else { 625 port->ctrl &= ~UHCI_PORT_LSDA; 626 } 627 628 uhci_resume(s); 629 } 630 631 static void uhci_detach(USBPort *port1) 632 { 633 UHCIState *s = port1->opaque; 634 UHCIPort *port = &s->ports[port1->index]; 635 636 uhci_async_cancel_device(s, port1->dev); 637 638 /* set connect status */ 639 if (port->ctrl & UHCI_PORT_CCS) { 640 port->ctrl &= ~UHCI_PORT_CCS; 641 port->ctrl |= UHCI_PORT_CSC; 642 } 643 /* disable port */ 644 if (port->ctrl & UHCI_PORT_EN) { 645 port->ctrl &= ~UHCI_PORT_EN; 646 port->ctrl |= UHCI_PORT_ENC; 647 } 648 649 uhci_resume(s); 650 } 651 652 static void uhci_child_detach(USBPort *port1, USBDevice *child) 653 { 654 UHCIState *s = port1->opaque; 655 656 uhci_async_cancel_device(s, child); 657 } 658 659 static void uhci_wakeup(USBPort *port1) 660 { 661 UHCIState *s = port1->opaque; 662 UHCIPort *port = &s->ports[port1->index]; 663 664 if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) { 665 port->ctrl |= UHCI_PORT_RD; 666 uhci_resume(s); 667 } 668 } 669 670 static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr) 671 { 672 USBDevice *dev; 673 int i; 674 675 for (i = 0; i < NB_PORTS; i++) { 676 UHCIPort *port = &s->ports[i]; 677 if (!(port->ctrl & UHCI_PORT_EN)) { 678 continue; 679 } 680 dev = usb_find_device(&port->port, addr); 681 if (dev != NULL) { 682 return dev; 683 } 684 } 685 return NULL; 686 } 687 688 static void uhci_async_complete(USBPort *port, USBPacket *packet); 689 static void uhci_process_frame(UHCIState *s); 690 691 /* return -1 if fatal error (frame must be stopped) 692 0 if TD successful 693 1 if TD unsuccessful or inactive 694 */ 695 static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) 696 { 697 int len = 0, max_len, err, ret; 698 uint8_t pid; 699 700 max_len = ((td->token >> 21) + 1) & 0x7ff; 701 pid = td->token & 0xff; 702 703 ret = async->packet.result; 704 705 if (td->ctrl & TD_CTRL_IOS) 706 td->ctrl &= ~TD_CTRL_ACTIVE; 707 708 if (ret < 0) 709 goto out; 710 711 len = async->packet.result; 712 td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); 713 714 /* The NAK bit may have been set by a previous frame, so clear it 715 here. The docs are somewhat unclear, but win2k relies on this 716 behavior. */ 717 td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); 718 if (td->ctrl & TD_CTRL_IOC) 719 *int_mask |= 0x01; 720 721 if (pid == USB_TOKEN_IN) { 722 if (len > max_len) { 723 ret = USB_RET_BABBLE; 724 goto out; 725 } 726 727 if ((td->ctrl & TD_CTRL_SPD) && len < max_len) { 728 *int_mask |= 0x02; 729 /* short packet: do not update QH */ 730 trace_usb_uhci_packet_complete_shortxfer(async->queue->token, 731 async->td); 732 return TD_RESULT_NEXT_QH; 733 } 734 } 735 736 /* success */ 737 trace_usb_uhci_packet_complete_success(async->queue->token, async->td); 738 return TD_RESULT_COMPLETE; 739 740 out: 741 switch(ret) { 742 case USB_RET_STALL: 743 td->ctrl |= TD_CTRL_STALL; 744 td->ctrl &= ~TD_CTRL_ACTIVE; 745 s->status |= UHCI_STS_USBERR; 746 if (td->ctrl & TD_CTRL_IOC) { 747 *int_mask |= 0x01; 748 } 749 uhci_update_irq(s); 750 trace_usb_uhci_packet_complete_stall(async->queue->token, async->td); 751 return TD_RESULT_NEXT_QH; 752 753 case USB_RET_BABBLE: 754 td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; 755 td->ctrl &= ~TD_CTRL_ACTIVE; 756 s->status |= UHCI_STS_USBERR; 757 if (td->ctrl & TD_CTRL_IOC) { 758 *int_mask |= 0x01; 759 } 760 uhci_update_irq(s); 761 /* frame interrupted */ 762 trace_usb_uhci_packet_complete_babble(async->queue->token, async->td); 763 return TD_RESULT_STOP_FRAME; 764 765 case USB_RET_NAK: 766 td->ctrl |= TD_CTRL_NAK; 767 if (pid == USB_TOKEN_SETUP) 768 break; 769 return TD_RESULT_NEXT_QH; 770 771 case USB_RET_IOERROR: 772 case USB_RET_NODEV: 773 default: 774 break; 775 } 776 777 /* Retry the TD if error count is not zero */ 778 779 td->ctrl |= TD_CTRL_TIMEOUT; 780 err = (td->ctrl >> TD_CTRL_ERROR_SHIFT) & 3; 781 if (err != 0) { 782 err--; 783 if (err == 0) { 784 td->ctrl &= ~TD_CTRL_ACTIVE; 785 s->status |= UHCI_STS_USBERR; 786 if (td->ctrl & TD_CTRL_IOC) 787 *int_mask |= 0x01; 788 uhci_update_irq(s); 789 trace_usb_uhci_packet_complete_error(async->queue->token, 790 async->td); 791 } 792 } 793 td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) | 794 (err << TD_CTRL_ERROR_SHIFT); 795 return TD_RESULT_NEXT_QH; 796 } 797 798 static int uhci_handle_td(UHCIState *s, uint32_t addr, UHCI_TD *td, uint32_t *int_mask) 799 { 800 UHCIAsync *async; 801 int len = 0, max_len; 802 uint8_t pid; 803 USBDevice *dev; 804 USBEndpoint *ep; 805 806 /* Is active ? */ 807 if (!(td->ctrl & TD_CTRL_ACTIVE)) 808 return TD_RESULT_NEXT_QH; 809 810 async = uhci_async_find_td(s, addr, td); 811 if (async) { 812 /* Already submitted */ 813 async->queue->valid = 32; 814 815 if (!async->done) 816 return TD_RESULT_ASYNC_CONT; 817 818 uhci_async_unlink(async); 819 goto done; 820 } 821 822 /* Allocate new packet */ 823 async = uhci_async_alloc(uhci_queue_get(s, td), addr); 824 825 /* valid needs to be large enough to handle 10 frame delay 826 * for initial isochronous requests 827 */ 828 async->queue->valid = 32; 829 async->isoc = td->ctrl & TD_CTRL_IOS; 830 831 max_len = ((td->token >> 21) + 1) & 0x7ff; 832 pid = td->token & 0xff; 833 834 dev = uhci_find_device(s, (td->token >> 8) & 0x7f); 835 ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf); 836 usb_packet_setup(&async->packet, pid, ep); 837 qemu_sglist_add(&async->sgl, td->buffer, max_len); 838 usb_packet_map(&async->packet, &async->sgl); 839 840 switch(pid) { 841 case USB_TOKEN_OUT: 842 case USB_TOKEN_SETUP: 843 len = usb_handle_packet(dev, &async->packet); 844 if (len >= 0) 845 len = max_len; 846 break; 847 848 case USB_TOKEN_IN: 849 len = usb_handle_packet(dev, &async->packet); 850 break; 851 852 default: 853 /* invalid pid : frame interrupted */ 854 uhci_async_free(async); 855 s->status |= UHCI_STS_HCPERR; 856 uhci_update_irq(s); 857 return TD_RESULT_STOP_FRAME; 858 } 859 860 if (len == USB_RET_ASYNC) { 861 uhci_async_link(async); 862 return TD_RESULT_ASYNC_START; 863 } 864 865 async->packet.result = len; 866 867 done: 868 len = uhci_complete_td(s, td, async, int_mask); 869 usb_packet_unmap(&async->packet); 870 uhci_async_free(async); 871 return len; 872 } 873 874 static void uhci_async_complete(USBPort *port, USBPacket *packet) 875 { 876 UHCIAsync *async = container_of(packet, UHCIAsync, packet); 877 UHCIState *s = async->queue->uhci; 878 879 if (async->isoc) { 880 UHCI_TD td; 881 uint32_t link = async->td; 882 uint32_t int_mask = 0, val; 883 884 pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td)); 885 le32_to_cpus(&td.link); 886 le32_to_cpus(&td.ctrl); 887 le32_to_cpus(&td.token); 888 le32_to_cpus(&td.buffer); 889 890 uhci_async_unlink(async); 891 uhci_complete_td(s, &td, async, &int_mask); 892 s->pending_int_mask |= int_mask; 893 894 /* update the status bits of the TD */ 895 val = cpu_to_le32(td.ctrl); 896 pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); 897 uhci_async_free(async); 898 } else { 899 async->done = 1; 900 uhci_process_frame(s); 901 } 902 } 903 904 static int is_valid(uint32_t link) 905 { 906 return (link & 1) == 0; 907 } 908 909 static int is_qh(uint32_t link) 910 { 911 return (link & 2) != 0; 912 } 913 914 static int depth_first(uint32_t link) 915 { 916 return (link & 4) != 0; 917 } 918 919 /* QH DB used for detecting QH loops */ 920 #define UHCI_MAX_QUEUES 128 921 typedef struct { 922 uint32_t addr[UHCI_MAX_QUEUES]; 923 int count; 924 } QhDb; 925 926 static void qhdb_reset(QhDb *db) 927 { 928 db->count = 0; 929 } 930 931 /* Add QH to DB. Returns 1 if already present or DB is full. */ 932 static int qhdb_insert(QhDb *db, uint32_t addr) 933 { 934 int i; 935 for (i = 0; i < db->count; i++) 936 if (db->addr[i] == addr) 937 return 1; 938 939 if (db->count >= UHCI_MAX_QUEUES) 940 return 1; 941 942 db->addr[db->count++] = addr; 943 return 0; 944 } 945 946 static void uhci_fill_queue(UHCIState *s, UHCI_TD *td) 947 { 948 uint32_t int_mask = 0; 949 uint32_t plink = td->link; 950 uint32_t token = uhci_queue_token(td); 951 UHCI_TD ptd; 952 int ret; 953 954 while (is_valid(plink)) { 955 pci_dma_read(&s->dev, plink & ~0xf, &ptd, sizeof(ptd)); 956 le32_to_cpus(&ptd.link); 957 le32_to_cpus(&ptd.ctrl); 958 le32_to_cpus(&ptd.token); 959 le32_to_cpus(&ptd.buffer); 960 if (!(ptd.ctrl & TD_CTRL_ACTIVE)) { 961 break; 962 } 963 if (uhci_queue_token(&ptd) != token) { 964 break; 965 } 966 trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token); 967 ret = uhci_handle_td(s, plink, &ptd, &int_mask); 968 assert(ret == TD_RESULT_ASYNC_START); 969 assert(int_mask == 0); 970 plink = ptd.link; 971 } 972 } 973 974 static void uhci_process_frame(UHCIState *s) 975 { 976 uint32_t frame_addr, link, old_td_ctrl, val, int_mask; 977 uint32_t curr_qh, td_count = 0, bytes_count = 0; 978 int cnt, ret; 979 UHCI_TD td; 980 UHCI_QH qh; 981 QhDb qhdb; 982 983 frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); 984 985 pci_dma_read(&s->dev, frame_addr, &link, 4); 986 le32_to_cpus(&link); 987 988 int_mask = 0; 989 curr_qh = 0; 990 991 qhdb_reset(&qhdb); 992 993 for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) { 994 if (is_qh(link)) { 995 /* QH */ 996 trace_usb_uhci_qh_load(link & ~0xf); 997 998 if (qhdb_insert(&qhdb, link)) { 999 /* 1000 * We're going in circles. Which is not a bug because 1001 * HCD is allowed to do that as part of the BW management. 1002 * 1003 * Stop processing here if 1004 * (a) no transaction has been done since we've been 1005 * here last time, or 1006 * (b) we've reached the usb 1.1 bandwidth, which is 1007 * 1280 bytes/frame. 1008 */ 1009 if (td_count == 0) { 1010 trace_usb_uhci_frame_loop_stop_idle(); 1011 break; 1012 } else if (bytes_count >= 1280) { 1013 trace_usb_uhci_frame_loop_stop_bandwidth(); 1014 break; 1015 } else { 1016 trace_usb_uhci_frame_loop_continue(); 1017 td_count = 0; 1018 qhdb_reset(&qhdb); 1019 qhdb_insert(&qhdb, link); 1020 } 1021 } 1022 1023 pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh)); 1024 le32_to_cpus(&qh.link); 1025 le32_to_cpus(&qh.el_link); 1026 1027 if (!is_valid(qh.el_link)) { 1028 /* QH w/o elements */ 1029 curr_qh = 0; 1030 link = qh.link; 1031 } else { 1032 /* QH with elements */ 1033 curr_qh = link; 1034 link = qh.el_link; 1035 } 1036 continue; 1037 } 1038 1039 /* TD */ 1040 pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td)); 1041 le32_to_cpus(&td.link); 1042 le32_to_cpus(&td.ctrl); 1043 le32_to_cpus(&td.token); 1044 le32_to_cpus(&td.buffer); 1045 trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token); 1046 1047 old_td_ctrl = td.ctrl; 1048 ret = uhci_handle_td(s, link, &td, &int_mask); 1049 if (old_td_ctrl != td.ctrl) { 1050 /* update the status bits of the TD */ 1051 val = cpu_to_le32(td.ctrl); 1052 pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); 1053 } 1054 1055 switch (ret) { 1056 case TD_RESULT_STOP_FRAME: /* interrupted frame */ 1057 goto out; 1058 1059 case TD_RESULT_NEXT_QH: 1060 case TD_RESULT_ASYNC_CONT: 1061 trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf); 1062 link = curr_qh ? qh.link : td.link; 1063 continue; 1064 1065 case TD_RESULT_ASYNC_START: 1066 trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf); 1067 if (is_valid(td.link)) { 1068 uhci_fill_queue(s, &td); 1069 } 1070 link = curr_qh ? qh.link : td.link; 1071 continue; 1072 1073 case TD_RESULT_COMPLETE: 1074 trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf); 1075 link = td.link; 1076 td_count++; 1077 bytes_count += (td.ctrl & 0x7ff) + 1; 1078 1079 if (curr_qh) { 1080 /* update QH element link */ 1081 qh.el_link = link; 1082 val = cpu_to_le32(qh.el_link); 1083 pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val)); 1084 1085 if (!depth_first(link)) { 1086 /* done with this QH */ 1087 curr_qh = 0; 1088 link = qh.link; 1089 } 1090 } 1091 break; 1092 1093 default: 1094 assert(!"unknown return code"); 1095 } 1096 1097 /* go to the next entry */ 1098 } 1099 1100 out: 1101 s->pending_int_mask |= int_mask; 1102 } 1103 1104 static void uhci_frame_timer(void *opaque) 1105 { 1106 UHCIState *s = opaque; 1107 1108 /* prepare the timer for the next frame */ 1109 s->expire_time += (get_ticks_per_sec() / FRAME_TIMER_FREQ); 1110 1111 if (!(s->cmd & UHCI_CMD_RS)) { 1112 /* Full stop */ 1113 trace_usb_uhci_schedule_stop(); 1114 qemu_del_timer(s->frame_timer); 1115 uhci_async_cancel_all(s); 1116 /* set hchalted bit in status - UHCI11D 2.1.2 */ 1117 s->status |= UHCI_STS_HCHALTED; 1118 return; 1119 } 1120 1121 /* Complete the previous frame */ 1122 if (s->pending_int_mask) { 1123 s->status2 |= s->pending_int_mask; 1124 s->status |= UHCI_STS_USBINT; 1125 uhci_update_irq(s); 1126 } 1127 s->pending_int_mask = 0; 1128 1129 /* Start new frame */ 1130 s->frnum = (s->frnum + 1) & 0x7ff; 1131 1132 trace_usb_uhci_frame_start(s->frnum); 1133 1134 uhci_async_validate_begin(s); 1135 1136 uhci_process_frame(s); 1137 1138 uhci_async_validate_end(s); 1139 1140 qemu_mod_timer(s->frame_timer, s->expire_time); 1141 } 1142 1143 static const MemoryRegionPortio uhci_portio[] = { 1144 { 0, 32, 2, .write = uhci_ioport_writew, }, 1145 { 0, 32, 2, .read = uhci_ioport_readw, }, 1146 { 0, 32, 4, .write = uhci_ioport_writel, }, 1147 { 0, 32, 4, .read = uhci_ioport_readl, }, 1148 { 0, 32, 1, .write = uhci_ioport_writeb, }, 1149 { 0, 32, 1, .read = uhci_ioport_readb, }, 1150 PORTIO_END_OF_LIST() 1151 }; 1152 1153 static const MemoryRegionOps uhci_ioport_ops = { 1154 .old_portio = uhci_portio, 1155 }; 1156 1157 static USBPortOps uhci_port_ops = { 1158 .attach = uhci_attach, 1159 .detach = uhci_detach, 1160 .child_detach = uhci_child_detach, 1161 .wakeup = uhci_wakeup, 1162 .complete = uhci_async_complete, 1163 }; 1164 1165 static USBBusOps uhci_bus_ops = { 1166 }; 1167 1168 static int usb_uhci_common_initfn(PCIDevice *dev) 1169 { 1170 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1171 uint8_t *pci_conf = s->dev.config; 1172 int i; 1173 1174 pci_conf[PCI_CLASS_PROG] = 0x00; 1175 /* TODO: reset value should be 0. */ 1176 pci_conf[PCI_INTERRUPT_PIN] = 4; /* interrupt pin D */ 1177 pci_conf[USB_SBRN] = USB_RELEASE_1; // release number 1178 1179 if (s->masterbus) { 1180 USBPort *ports[NB_PORTS]; 1181 for(i = 0; i < NB_PORTS; i++) { 1182 ports[i] = &s->ports[i].port; 1183 } 1184 if (usb_register_companion(s->masterbus, ports, NB_PORTS, 1185 s->firstport, s, &uhci_port_ops, 1186 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) { 1187 return -1; 1188 } 1189 } else { 1190 usb_bus_new(&s->bus, &uhci_bus_ops, &s->dev.qdev); 1191 for (i = 0; i < NB_PORTS; i++) { 1192 usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, 1193 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); 1194 } 1195 } 1196 s->frame_timer = qemu_new_timer_ns(vm_clock, uhci_frame_timer, s); 1197 s->num_ports_vmstate = NB_PORTS; 1198 QTAILQ_INIT(&s->queues); 1199 1200 qemu_register_reset(uhci_reset, s); 1201 1202 memory_region_init_io(&s->io_bar, &uhci_ioport_ops, s, "uhci", 0x20); 1203 /* Use region 4 for consistency with real hardware. BSD guests seem 1204 to rely on this. */ 1205 pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); 1206 1207 return 0; 1208 } 1209 1210 static int usb_uhci_vt82c686b_initfn(PCIDevice *dev) 1211 { 1212 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1213 uint8_t *pci_conf = s->dev.config; 1214 1215 /* USB misc control 1/2 */ 1216 pci_set_long(pci_conf + 0x40,0x00001000); 1217 /* PM capability */ 1218 pci_set_long(pci_conf + 0x80,0x00020001); 1219 /* USB legacy support */ 1220 pci_set_long(pci_conf + 0xc0,0x00002000); 1221 1222 return usb_uhci_common_initfn(dev); 1223 } 1224 1225 static int usb_uhci_exit(PCIDevice *dev) 1226 { 1227 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1228 1229 memory_region_destroy(&s->io_bar); 1230 return 0; 1231 } 1232 1233 static Property uhci_properties[] = { 1234 DEFINE_PROP_STRING("masterbus", UHCIState, masterbus), 1235 DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), 1236 DEFINE_PROP_END_OF_LIST(), 1237 }; 1238 1239 static void piix3_uhci_class_init(ObjectClass *klass, void *data) 1240 { 1241 DeviceClass *dc = DEVICE_CLASS(klass); 1242 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1243 1244 k->init = usb_uhci_common_initfn; 1245 k->exit = usb_uhci_exit; 1246 k->vendor_id = PCI_VENDOR_ID_INTEL; 1247 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_2; 1248 k->revision = 0x01; 1249 k->class_id = PCI_CLASS_SERIAL_USB; 1250 dc->vmsd = &vmstate_uhci; 1251 dc->props = uhci_properties; 1252 } 1253 1254 static TypeInfo piix3_uhci_info = { 1255 .name = "piix3-usb-uhci", 1256 .parent = TYPE_PCI_DEVICE, 1257 .instance_size = sizeof(UHCIState), 1258 .class_init = piix3_uhci_class_init, 1259 }; 1260 1261 static void piix4_uhci_class_init(ObjectClass *klass, void *data) 1262 { 1263 DeviceClass *dc = DEVICE_CLASS(klass); 1264 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1265 1266 k->init = usb_uhci_common_initfn; 1267 k->exit = usb_uhci_exit; 1268 k->vendor_id = PCI_VENDOR_ID_INTEL; 1269 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_2; 1270 k->revision = 0x01; 1271 k->class_id = PCI_CLASS_SERIAL_USB; 1272 dc->vmsd = &vmstate_uhci; 1273 dc->props = uhci_properties; 1274 } 1275 1276 static TypeInfo piix4_uhci_info = { 1277 .name = "piix4-usb-uhci", 1278 .parent = TYPE_PCI_DEVICE, 1279 .instance_size = sizeof(UHCIState), 1280 .class_init = piix4_uhci_class_init, 1281 }; 1282 1283 static void vt82c686b_uhci_class_init(ObjectClass *klass, void *data) 1284 { 1285 DeviceClass *dc = DEVICE_CLASS(klass); 1286 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1287 1288 k->init = usb_uhci_vt82c686b_initfn; 1289 k->exit = usb_uhci_exit; 1290 k->vendor_id = PCI_VENDOR_ID_VIA; 1291 k->device_id = PCI_DEVICE_ID_VIA_UHCI; 1292 k->revision = 0x01; 1293 k->class_id = PCI_CLASS_SERIAL_USB; 1294 dc->vmsd = &vmstate_uhci; 1295 dc->props = uhci_properties; 1296 } 1297 1298 static TypeInfo vt82c686b_uhci_info = { 1299 .name = "vt82c686b-usb-uhci", 1300 .parent = TYPE_PCI_DEVICE, 1301 .instance_size = sizeof(UHCIState), 1302 .class_init = vt82c686b_uhci_class_init, 1303 }; 1304 1305 static void ich9_uhci1_class_init(ObjectClass *klass, void *data) 1306 { 1307 DeviceClass *dc = DEVICE_CLASS(klass); 1308 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1309 1310 k->init = usb_uhci_common_initfn; 1311 k->vendor_id = PCI_VENDOR_ID_INTEL; 1312 k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1; 1313 k->revision = 0x03; 1314 k->class_id = PCI_CLASS_SERIAL_USB; 1315 dc->vmsd = &vmstate_uhci; 1316 dc->props = uhci_properties; 1317 } 1318 1319 static TypeInfo ich9_uhci1_info = { 1320 .name = "ich9-usb-uhci1", 1321 .parent = TYPE_PCI_DEVICE, 1322 .instance_size = sizeof(UHCIState), 1323 .class_init = ich9_uhci1_class_init, 1324 }; 1325 1326 static void ich9_uhci2_class_init(ObjectClass *klass, void *data) 1327 { 1328 DeviceClass *dc = DEVICE_CLASS(klass); 1329 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1330 1331 k->init = usb_uhci_common_initfn; 1332 k->vendor_id = PCI_VENDOR_ID_INTEL; 1333 k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2; 1334 k->revision = 0x03; 1335 k->class_id = PCI_CLASS_SERIAL_USB; 1336 dc->vmsd = &vmstate_uhci; 1337 dc->props = uhci_properties; 1338 } 1339 1340 static TypeInfo ich9_uhci2_info = { 1341 .name = "ich9-usb-uhci2", 1342 .parent = TYPE_PCI_DEVICE, 1343 .instance_size = sizeof(UHCIState), 1344 .class_init = ich9_uhci2_class_init, 1345 }; 1346 1347 static void ich9_uhci3_class_init(ObjectClass *klass, void *data) 1348 { 1349 DeviceClass *dc = DEVICE_CLASS(klass); 1350 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1351 1352 k->init = usb_uhci_common_initfn; 1353 k->vendor_id = PCI_VENDOR_ID_INTEL; 1354 k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3; 1355 k->revision = 0x03; 1356 k->class_id = PCI_CLASS_SERIAL_USB; 1357 dc->vmsd = &vmstate_uhci; 1358 dc->props = uhci_properties; 1359 } 1360 1361 static TypeInfo ich9_uhci3_info = { 1362 .name = "ich9-usb-uhci3", 1363 .parent = TYPE_PCI_DEVICE, 1364 .instance_size = sizeof(UHCIState), 1365 .class_init = ich9_uhci3_class_init, 1366 }; 1367 1368 static void uhci_register_types(void) 1369 { 1370 type_register_static(&piix3_uhci_info); 1371 type_register_static(&piix4_uhci_info); 1372 type_register_static(&vt82c686b_uhci_info); 1373 type_register_static(&ich9_uhci1_info); 1374 type_register_static(&ich9_uhci2_info); 1375 type_register_static(&ich9_uhci3_info); 1376 } 1377 1378 type_init(uhci_register_types) 1379