1 /* 2 * USB UHCI controller emulation 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Copyright (c) 2008 Max Krasnyansky 7 * Magor rewrite of the UHCI data structures parser and frame processor 8 * Support for fully async operation and multiple outstanding transactions 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy 11 * of this software and associated documentation files (the "Software"), to deal 12 * in the Software without restriction, including without limitation the rights 13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 14 * copies of the Software, and to permit persons to whom the Software is 15 * furnished to do so, subject to the following conditions: 16 * 17 * The above copyright notice and this permission notice shall be included in 18 * all copies or substantial portions of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 26 * THE SOFTWARE. 27 */ 28 29 #include "qemu/osdep.h" 30 #include "hw/usb.h" 31 #include "hw/usb/uhci-regs.h" 32 #include "migration/vmstate.h" 33 #include "hw/pci/pci.h" 34 #include "hw/irq.h" 35 #include "hw/qdev-properties.h" 36 #include "qapi/error.h" 37 #include "qemu/timer.h" 38 #include "qemu/iov.h" 39 #include "system/dma.h" 40 #include "trace.h" 41 #include "qemu/main-loop.h" 42 #include "qemu/module.h" 43 #include "qom/object.h" 44 #include "hcd-uhci.h" 45 46 #define FRAME_TIMER_FREQ 1000 47 48 #define FRAME_MAX_LOOPS 256 49 50 /* Must be large enough to handle 10 frame delay for initial isoc requests */ 51 #define QH_VALID 32 52 53 #define MAX_FRAMES_PER_TICK (QH_VALID / 2) 54 55 enum { 56 TD_RESULT_STOP_FRAME = 10, 57 TD_RESULT_COMPLETE, 58 TD_RESULT_NEXT_QH, 59 TD_RESULT_ASYNC_START, 60 TD_RESULT_ASYNC_CONT, 61 }; 62 63 typedef struct UHCIAsync UHCIAsync; 64 65 struct UHCIPCIDeviceClass { 66 PCIDeviceClass parent_class; 67 UHCIInfo info; 68 }; 69 70 /* 71 * Pending async transaction. 72 * 'packet' must be the first field because completion 73 * handler does "(UHCIAsync *) pkt" cast. 74 */ 75 76 struct UHCIAsync { 77 USBPacket packet; 78 uint8_t static_buf[64]; /* 64 bytes is enough, except for isoc packets */ 79 uint8_t *buf; 80 UHCIQueue *queue; 81 QTAILQ_ENTRY(UHCIAsync) next; 82 uint32_t td_addr; 83 uint8_t done; 84 }; 85 86 struct UHCIQueue { 87 uint32_t qh_addr; 88 uint32_t token; 89 UHCIState *uhci; 90 USBEndpoint *ep; 91 QTAILQ_ENTRY(UHCIQueue) next; 92 QTAILQ_HEAD(, UHCIAsync) asyncs; 93 int8_t valid; 94 }; 95 96 typedef struct UHCI_TD { 97 uint32_t link; 98 uint32_t ctrl; /* see TD_CTRL_xxx */ 99 uint32_t token; 100 uint32_t buffer; 101 } UHCI_TD; 102 103 typedef struct UHCI_QH { 104 uint32_t link; 105 uint32_t el_link; 106 } UHCI_QH; 107 108 static void uhci_async_cancel(UHCIAsync *async); 109 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td); 110 static void uhci_resume(void *opaque); 111 112 static inline int32_t uhci_queue_token(UHCI_TD *td) 113 { 114 if ((td->token & (0xf << 15)) == 0) { 115 /* ctrl ep, cover ep and dev, not pid! */ 116 return td->token & 0x7ff00; 117 } else { 118 /* covers ep, dev, pid -> identifies the endpoint */ 119 return td->token & 0x7ffff; 120 } 121 } 122 123 static UHCIQueue *uhci_queue_new(UHCIState *s, uint32_t qh_addr, UHCI_TD *td, 124 USBEndpoint *ep) 125 { 126 UHCIQueue *queue; 127 128 queue = g_new0(UHCIQueue, 1); 129 queue->uhci = s; 130 queue->qh_addr = qh_addr; 131 queue->token = uhci_queue_token(td); 132 queue->ep = ep; 133 QTAILQ_INIT(&queue->asyncs); 134 QTAILQ_INSERT_HEAD(&s->queues, queue, next); 135 queue->valid = QH_VALID; 136 trace_usb_uhci_queue_add(queue->token); 137 return queue; 138 } 139 140 static void uhci_queue_free(UHCIQueue *queue, const char *reason) 141 { 142 UHCIState *s = queue->uhci; 143 UHCIAsync *async; 144 145 while (!QTAILQ_EMPTY(&queue->asyncs)) { 146 async = QTAILQ_FIRST(&queue->asyncs); 147 uhci_async_cancel(async); 148 } 149 usb_device_ep_stopped(queue->ep->dev, queue->ep); 150 151 trace_usb_uhci_queue_del(queue->token, reason); 152 QTAILQ_REMOVE(&s->queues, queue, next); 153 g_free(queue); 154 } 155 156 static UHCIQueue *uhci_queue_find(UHCIState *s, UHCI_TD *td) 157 { 158 uint32_t token = uhci_queue_token(td); 159 UHCIQueue *queue; 160 161 QTAILQ_FOREACH(queue, &s->queues, next) { 162 if (queue->token == token) { 163 return queue; 164 } 165 } 166 return NULL; 167 } 168 169 static bool uhci_queue_verify(UHCIQueue *queue, uint32_t qh_addr, UHCI_TD *td, 170 uint32_t td_addr, bool queuing) 171 { 172 UHCIAsync *first = QTAILQ_FIRST(&queue->asyncs); 173 uint32_t queue_token_addr = (queue->token >> 8) & 0x7f; 174 175 return queue->qh_addr == qh_addr && 176 queue->token == uhci_queue_token(td) && 177 queue_token_addr == queue->ep->dev->addr && 178 (queuing || !(td->ctrl & TD_CTRL_ACTIVE) || first == NULL || 179 first->td_addr == td_addr); 180 } 181 182 static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t td_addr) 183 { 184 UHCIAsync *async = g_new0(UHCIAsync, 1); 185 186 async->queue = queue; 187 async->td_addr = td_addr; 188 usb_packet_init(&async->packet); 189 trace_usb_uhci_packet_add(async->queue->token, async->td_addr); 190 191 return async; 192 } 193 194 static void uhci_async_free(UHCIAsync *async) 195 { 196 trace_usb_uhci_packet_del(async->queue->token, async->td_addr); 197 usb_packet_cleanup(&async->packet); 198 if (async->buf != async->static_buf) { 199 g_free(async->buf); 200 } 201 g_free(async); 202 } 203 204 static void uhci_async_link(UHCIAsync *async) 205 { 206 UHCIQueue *queue = async->queue; 207 QTAILQ_INSERT_TAIL(&queue->asyncs, async, next); 208 trace_usb_uhci_packet_link_async(async->queue->token, async->td_addr); 209 } 210 211 static void uhci_async_unlink(UHCIAsync *async) 212 { 213 UHCIQueue *queue = async->queue; 214 QTAILQ_REMOVE(&queue->asyncs, async, next); 215 trace_usb_uhci_packet_unlink_async(async->queue->token, async->td_addr); 216 } 217 218 static void uhci_async_cancel(UHCIAsync *async) 219 { 220 uhci_async_unlink(async); 221 trace_usb_uhci_packet_cancel(async->queue->token, async->td_addr, 222 async->done); 223 if (!async->done) { 224 usb_cancel_packet(&async->packet); 225 } 226 uhci_async_free(async); 227 } 228 229 /* 230 * Mark all outstanding async packets as invalid. 231 * This is used for canceling them when TDs are removed by the HCD. 232 */ 233 static void uhci_async_validate_begin(UHCIState *s) 234 { 235 UHCIQueue *queue; 236 237 QTAILQ_FOREACH(queue, &s->queues, next) { 238 queue->valid--; 239 } 240 } 241 242 /* 243 * Cancel async packets that are no longer valid 244 */ 245 static void uhci_async_validate_end(UHCIState *s) 246 { 247 UHCIQueue *queue, *n; 248 249 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 250 if (!queue->valid) { 251 uhci_queue_free(queue, "validate-end"); 252 } 253 } 254 } 255 256 static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev) 257 { 258 UHCIQueue *queue, *n; 259 260 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 261 if (queue->ep->dev == dev) { 262 uhci_queue_free(queue, "cancel-device"); 263 } 264 } 265 } 266 267 static void uhci_async_cancel_all(UHCIState *s) 268 { 269 UHCIQueue *queue, *nq; 270 271 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) { 272 uhci_queue_free(queue, "cancel-all"); 273 } 274 } 275 276 static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t td_addr) 277 { 278 UHCIQueue *queue; 279 UHCIAsync *async; 280 281 QTAILQ_FOREACH(queue, &s->queues, next) { 282 QTAILQ_FOREACH(async, &queue->asyncs, next) { 283 if (async->td_addr == td_addr) { 284 return async; 285 } 286 } 287 } 288 return NULL; 289 } 290 291 static void uhci_update_irq(UHCIState *s) 292 { 293 int level = 0; 294 if (((s->status2 & 1) && (s->intr & (1 << 2))) || 295 ((s->status2 & 2) && (s->intr & (1 << 3))) || 296 ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || 297 ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || 298 (s->status & UHCI_STS_HSERR) || 299 (s->status & UHCI_STS_HCPERR)) { 300 level = 1; 301 } 302 qemu_set_irq(s->irq, level); 303 } 304 305 static void uhci_reset(DeviceState *dev) 306 { 307 PCIDevice *d = PCI_DEVICE(dev); 308 UHCIState *s = UHCI(d); 309 uint8_t *pci_conf; 310 int i; 311 UHCIPort *port; 312 313 trace_usb_uhci_reset(); 314 315 pci_conf = s->dev.config; 316 317 pci_conf[0x6a] = 0x01; /* usb clock */ 318 pci_conf[0x6b] = 0x00; 319 s->cmd = 0; 320 s->status = UHCI_STS_HCHALTED; 321 s->status2 = 0; 322 s->intr = 0; 323 s->fl_base_addr = 0; 324 s->sof_timing = 64; 325 326 for (i = 0; i < UHCI_PORTS; i++) { 327 port = &s->ports[i]; 328 port->ctrl = 0x0080; 329 if (port->port.dev && port->port.dev->attached) { 330 usb_port_reset(&port->port); 331 } 332 } 333 334 uhci_async_cancel_all(s); 335 qemu_bh_cancel(s->bh); 336 uhci_update_irq(s); 337 } 338 339 static const VMStateDescription vmstate_uhci_port = { 340 .name = "uhci port", 341 .version_id = 1, 342 .minimum_version_id = 1, 343 .fields = (const VMStateField[]) { 344 VMSTATE_UINT16(ctrl, UHCIPort), 345 VMSTATE_END_OF_LIST() 346 } 347 }; 348 349 static int uhci_post_load(void *opaque, int version_id) 350 { 351 UHCIState *s = opaque; 352 353 if (version_id < 2) { 354 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 355 (NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ); 356 } 357 return 0; 358 } 359 360 static const VMStateDescription vmstate_uhci = { 361 .name = "uhci", 362 .version_id = 3, 363 .minimum_version_id = 1, 364 .post_load = uhci_post_load, 365 .fields = (const VMStateField[]) { 366 VMSTATE_PCI_DEVICE(dev, UHCIState), 367 VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState, NULL), 368 VMSTATE_STRUCT_ARRAY(ports, UHCIState, UHCI_PORTS, 1, 369 vmstate_uhci_port, UHCIPort), 370 VMSTATE_UINT16(cmd, UHCIState), 371 VMSTATE_UINT16(status, UHCIState), 372 VMSTATE_UINT16(intr, UHCIState), 373 VMSTATE_UINT16(frnum, UHCIState), 374 VMSTATE_UINT32(fl_base_addr, UHCIState), 375 VMSTATE_UINT8(sof_timing, UHCIState), 376 VMSTATE_UINT8(status2, UHCIState), 377 VMSTATE_TIMER_PTR(frame_timer, UHCIState), 378 VMSTATE_INT64_V(expire_time, UHCIState, 2), 379 VMSTATE_UINT32_V(pending_int_mask, UHCIState, 3), 380 VMSTATE_END_OF_LIST() 381 } 382 }; 383 384 static void uhci_port_write(void *opaque, hwaddr addr, 385 uint64_t val, unsigned size) 386 { 387 UHCIState *s = opaque; 388 389 trace_usb_uhci_mmio_writew(addr, val); 390 391 switch (addr) { 392 case UHCI_USBCMD: 393 if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) { 394 /* start frame processing */ 395 trace_usb_uhci_schedule_start(); 396 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 397 (NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ); 398 timer_mod(s->frame_timer, s->expire_time); 399 s->status &= ~UHCI_STS_HCHALTED; 400 } else if (!(val & UHCI_CMD_RS)) { 401 s->status |= UHCI_STS_HCHALTED; 402 } 403 if (val & UHCI_CMD_GRESET) { 404 UHCIPort *port; 405 int i; 406 407 /* send reset on the USB bus */ 408 for (i = 0; i < UHCI_PORTS; i++) { 409 port = &s->ports[i]; 410 usb_device_reset(port->port.dev); 411 } 412 uhci_reset(DEVICE(s)); 413 return; 414 } 415 if (val & UHCI_CMD_HCRESET) { 416 uhci_reset(DEVICE(s)); 417 return; 418 } 419 s->cmd = val; 420 if (val & UHCI_CMD_EGSM) { 421 if ((s->ports[0].ctrl & UHCI_PORT_RD) || 422 (s->ports[1].ctrl & UHCI_PORT_RD)) { 423 uhci_resume(s); 424 } 425 } 426 break; 427 case UHCI_USBSTS: 428 s->status &= ~val; 429 /* 430 * XXX: the chip spec is not coherent, so we add a hidden 431 * register to distinguish between IOC and SPD 432 */ 433 if (val & UHCI_STS_USBINT) { 434 s->status2 = 0; 435 } 436 uhci_update_irq(s); 437 break; 438 case UHCI_USBINTR: 439 s->intr = val; 440 uhci_update_irq(s); 441 break; 442 case UHCI_USBFRNUM: 443 if (s->status & UHCI_STS_HCHALTED) { 444 s->frnum = val & 0x7ff; 445 } 446 break; 447 case UHCI_USBFLBASEADD: 448 s->fl_base_addr &= 0xffff0000; 449 s->fl_base_addr |= val & ~0xfff; 450 break; 451 case UHCI_USBFLBASEADD + 2: 452 s->fl_base_addr &= 0x0000ffff; 453 s->fl_base_addr |= (val << 16); 454 break; 455 case UHCI_USBSOF: 456 s->sof_timing = val & 0xff; 457 break; 458 case UHCI_USBPORTSC1 ... UHCI_USBPORTSC4: 459 { 460 UHCIPort *port; 461 USBDevice *dev; 462 int n; 463 464 n = (addr >> 1) & 7; 465 if (n >= UHCI_PORTS) { 466 return; 467 } 468 port = &s->ports[n]; 469 dev = port->port.dev; 470 if (dev && dev->attached) { 471 /* port reset */ 472 if ((val & UHCI_PORT_RESET) && 473 !(port->ctrl & UHCI_PORT_RESET)) { 474 usb_device_reset(dev); 475 } 476 } 477 port->ctrl &= UHCI_PORT_READ_ONLY; 478 /* enabled may only be set if a device is connected */ 479 if (!(port->ctrl & UHCI_PORT_CCS)) { 480 val &= ~UHCI_PORT_EN; 481 } 482 port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); 483 /* some bits are reset when a '1' is written to them */ 484 port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); 485 } 486 break; 487 } 488 } 489 490 static uint64_t uhci_port_read(void *opaque, hwaddr addr, unsigned size) 491 { 492 UHCIState *s = opaque; 493 uint32_t val; 494 495 switch (addr) { 496 case UHCI_USBCMD: 497 val = s->cmd; 498 break; 499 case UHCI_USBSTS: 500 val = s->status; 501 break; 502 case UHCI_USBINTR: 503 val = s->intr; 504 break; 505 case UHCI_USBFRNUM: 506 val = s->frnum; 507 break; 508 case UHCI_USBFLBASEADD: 509 val = s->fl_base_addr & 0xffff; 510 break; 511 case UHCI_USBFLBASEADD + 2: 512 val = (s->fl_base_addr >> 16) & 0xffff; 513 break; 514 case UHCI_USBSOF: 515 val = s->sof_timing; 516 break; 517 case UHCI_USBPORTSC1 ... UHCI_USBPORTSC4: 518 { 519 UHCIPort *port; 520 int n; 521 n = (addr >> 1) & 7; 522 if (n >= UHCI_PORTS) { 523 goto read_default; 524 } 525 port = &s->ports[n]; 526 val = port->ctrl; 527 } 528 break; 529 default: 530 read_default: 531 val = 0xff7f; /* disabled port */ 532 break; 533 } 534 535 trace_usb_uhci_mmio_readw(addr, val); 536 537 return val; 538 } 539 540 /* signal resume if controller suspended */ 541 static void uhci_resume(void *opaque) 542 { 543 UHCIState *s = (UHCIState *)opaque; 544 545 if (!s) { 546 return; 547 } 548 549 if (s->cmd & UHCI_CMD_EGSM) { 550 s->cmd |= UHCI_CMD_FGR; 551 s->status |= UHCI_STS_RD; 552 uhci_update_irq(s); 553 } 554 } 555 556 static void uhci_attach(USBPort *port1) 557 { 558 UHCIState *s = port1->opaque; 559 UHCIPort *port = &s->ports[port1->index]; 560 561 /* set connect status */ 562 port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; 563 564 /* update speed */ 565 if (port->port.dev->speed == USB_SPEED_LOW) { 566 port->ctrl |= UHCI_PORT_LSDA; 567 } else { 568 port->ctrl &= ~UHCI_PORT_LSDA; 569 } 570 571 uhci_resume(s); 572 } 573 574 static void uhci_detach(USBPort *port1) 575 { 576 UHCIState *s = port1->opaque; 577 UHCIPort *port = &s->ports[port1->index]; 578 579 uhci_async_cancel_device(s, port1->dev); 580 581 /* set connect status */ 582 if (port->ctrl & UHCI_PORT_CCS) { 583 port->ctrl &= ~UHCI_PORT_CCS; 584 port->ctrl |= UHCI_PORT_CSC; 585 } 586 /* disable port */ 587 if (port->ctrl & UHCI_PORT_EN) { 588 port->ctrl &= ~UHCI_PORT_EN; 589 port->ctrl |= UHCI_PORT_ENC; 590 } 591 592 uhci_resume(s); 593 } 594 595 static void uhci_child_detach(USBPort *port1, USBDevice *child) 596 { 597 UHCIState *s = port1->opaque; 598 599 uhci_async_cancel_device(s, child); 600 } 601 602 static void uhci_wakeup(USBPort *port1) 603 { 604 UHCIState *s = port1->opaque; 605 UHCIPort *port = &s->ports[port1->index]; 606 607 if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) { 608 port->ctrl |= UHCI_PORT_RD; 609 uhci_resume(s); 610 } 611 } 612 613 static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr) 614 { 615 USBDevice *dev; 616 int i; 617 618 for (i = 0; i < UHCI_PORTS; i++) { 619 UHCIPort *port = &s->ports[i]; 620 if (!(port->ctrl & UHCI_PORT_EN)) { 621 continue; 622 } 623 dev = usb_find_device(&port->port, addr); 624 if (dev != NULL) { 625 return dev; 626 } 627 } 628 return NULL; 629 } 630 631 static void uhci_read_td(UHCIState *s, UHCI_TD *td, uint32_t link) 632 { 633 pci_dma_read(&s->dev, link & ~0xf, td, sizeof(*td)); 634 le32_to_cpus(&td->link); 635 le32_to_cpus(&td->ctrl); 636 le32_to_cpus(&td->token); 637 le32_to_cpus(&td->buffer); 638 } 639 640 static int uhci_handle_td_error(UHCIState *s, UHCI_TD *td, uint32_t td_addr, 641 int status, uint32_t *int_mask) 642 { 643 uint32_t queue_token = uhci_queue_token(td); 644 int ret; 645 646 switch (status) { 647 case USB_RET_NAK: 648 td->ctrl |= TD_CTRL_NAK; 649 return TD_RESULT_NEXT_QH; 650 651 case USB_RET_STALL: 652 td->ctrl |= TD_CTRL_STALL; 653 trace_usb_uhci_packet_complete_stall(queue_token, td_addr); 654 ret = TD_RESULT_NEXT_QH; 655 break; 656 657 case USB_RET_BABBLE: 658 td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; 659 /* frame interrupted */ 660 trace_usb_uhci_packet_complete_babble(queue_token, td_addr); 661 ret = TD_RESULT_STOP_FRAME; 662 break; 663 664 case USB_RET_IOERROR: 665 case USB_RET_NODEV: 666 default: 667 td->ctrl |= TD_CTRL_TIMEOUT; 668 td->ctrl &= ~(3 << TD_CTRL_ERROR_SHIFT); 669 trace_usb_uhci_packet_complete_error(queue_token, td_addr); 670 ret = TD_RESULT_NEXT_QH; 671 break; 672 } 673 674 td->ctrl &= ~TD_CTRL_ACTIVE; 675 s->status |= UHCI_STS_USBERR; 676 if (td->ctrl & TD_CTRL_IOC) { 677 *int_mask |= 0x01; 678 } 679 uhci_update_irq(s); 680 return ret; 681 } 682 683 static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, 684 uint32_t *int_mask) 685 { 686 int len = 0, max_len; 687 uint8_t pid; 688 689 max_len = ((td->token >> 21) + 1) & 0x7ff; 690 pid = td->token & 0xff; 691 692 if (td->ctrl & TD_CTRL_IOS) { 693 td->ctrl &= ~TD_CTRL_ACTIVE; 694 } 695 696 if (async->packet.status != USB_RET_SUCCESS) { 697 return uhci_handle_td_error(s, td, async->td_addr, 698 async->packet.status, int_mask); 699 } 700 701 len = async->packet.actual_length; 702 td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); 703 704 /* 705 * The NAK bit may have been set by a previous frame, so clear it 706 * here. The docs are somewhat unclear, but win2k relies on this 707 * behavior. 708 */ 709 td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); 710 if (td->ctrl & TD_CTRL_IOC) { 711 *int_mask |= 0x01; 712 } 713 714 if (pid == USB_TOKEN_IN) { 715 pci_dma_write(&s->dev, td->buffer, async->buf, len); 716 if ((td->ctrl & TD_CTRL_SPD) && len < max_len) { 717 *int_mask |= 0x02; 718 /* short packet: do not update QH */ 719 trace_usb_uhci_packet_complete_shortxfer(async->queue->token, 720 async->td_addr); 721 return TD_RESULT_NEXT_QH; 722 } 723 } 724 725 /* success */ 726 trace_usb_uhci_packet_complete_success(async->queue->token, 727 async->td_addr); 728 return TD_RESULT_COMPLETE; 729 } 730 731 static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr, 732 UHCI_TD *td, uint32_t td_addr, uint32_t *int_mask) 733 { 734 int ret, max_len; 735 bool spd; 736 bool queuing = (q != NULL); 737 uint8_t pid = td->token & 0xff; 738 UHCIAsync *async; 739 740 async = uhci_async_find_td(s, td_addr); 741 if (async) { 742 if (uhci_queue_verify(async->queue, qh_addr, td, td_addr, queuing)) { 743 assert(q == NULL || q == async->queue); 744 q = async->queue; 745 } else { 746 uhci_queue_free(async->queue, "guest re-used pending td"); 747 async = NULL; 748 } 749 } 750 751 if (q == NULL) { 752 q = uhci_queue_find(s, td); 753 if (q && !uhci_queue_verify(q, qh_addr, td, td_addr, queuing)) { 754 uhci_queue_free(q, "guest re-used qh"); 755 q = NULL; 756 } 757 } 758 759 if (q) { 760 q->valid = QH_VALID; 761 } 762 763 /* Is active ? */ 764 if (!(td->ctrl & TD_CTRL_ACTIVE)) { 765 if (async) { 766 /* Guest marked a pending td non-active, cancel the queue */ 767 uhci_queue_free(async->queue, "pending td non-active"); 768 } 769 /* 770 * ehci11d spec page 22: "Even if the Active bit in the TD is already 771 * cleared when the TD is fetched ... an IOC interrupt is generated" 772 */ 773 if (td->ctrl & TD_CTRL_IOC) { 774 *int_mask |= 0x01; 775 } 776 return TD_RESULT_NEXT_QH; 777 } 778 779 switch (pid) { 780 case USB_TOKEN_OUT: 781 case USB_TOKEN_SETUP: 782 case USB_TOKEN_IN: 783 break; 784 default: 785 /* invalid pid : frame interrupted */ 786 s->status |= UHCI_STS_HCPERR; 787 s->cmd &= ~UHCI_CMD_RS; 788 uhci_update_irq(s); 789 return TD_RESULT_STOP_FRAME; 790 } 791 792 if (async) { 793 if (queuing) { 794 /* 795 * we are busy filling the queue, we are not prepared 796 * to consume completed packages then, just leave them 797 * in async state 798 */ 799 return TD_RESULT_ASYNC_CONT; 800 } 801 if (!async->done) { 802 UHCI_TD last_td; 803 UHCIAsync *last = QTAILQ_LAST(&async->queue->asyncs); 804 /* 805 * While we are waiting for the current td to complete, the guest 806 * may have added more tds to the queue. Note we re-read the td 807 * rather then caching it, as we want to see guest made changes! 808 */ 809 uhci_read_td(s, &last_td, last->td_addr); 810 uhci_queue_fill(async->queue, &last_td); 811 812 return TD_RESULT_ASYNC_CONT; 813 } 814 uhci_async_unlink(async); 815 goto done; 816 } 817 818 if (s->completions_only) { 819 return TD_RESULT_ASYNC_CONT; 820 } 821 822 /* Allocate new packet */ 823 if (q == NULL) { 824 USBDevice *dev; 825 USBEndpoint *ep; 826 827 dev = uhci_find_device(s, (td->token >> 8) & 0x7f); 828 if (dev == NULL) { 829 return uhci_handle_td_error(s, td, td_addr, USB_RET_NODEV, 830 int_mask); 831 } 832 ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf); 833 q = uhci_queue_new(s, qh_addr, td, ep); 834 } 835 async = uhci_async_alloc(q, td_addr); 836 837 max_len = ((td->token >> 21) + 1) & 0x7ff; 838 spd = (pid == USB_TOKEN_IN && (td->ctrl & TD_CTRL_SPD) != 0); 839 usb_packet_setup(&async->packet, pid, q->ep, 0, td_addr, spd, 840 (td->ctrl & TD_CTRL_IOC) != 0); 841 if (max_len <= sizeof(async->static_buf)) { 842 async->buf = async->static_buf; 843 } else { 844 async->buf = g_malloc(max_len); 845 } 846 usb_packet_addbuf(&async->packet, async->buf, max_len); 847 848 switch (pid) { 849 case USB_TOKEN_OUT: 850 case USB_TOKEN_SETUP: 851 pci_dma_read(&s->dev, td->buffer, async->buf, max_len); 852 usb_handle_packet(q->ep->dev, &async->packet); 853 if (async->packet.status == USB_RET_SUCCESS) { 854 async->packet.actual_length = max_len; 855 } 856 break; 857 858 case USB_TOKEN_IN: 859 usb_handle_packet(q->ep->dev, &async->packet); 860 break; 861 862 default: 863 abort(); /* Never to execute */ 864 } 865 866 if (async->packet.status == USB_RET_ASYNC) { 867 uhci_async_link(async); 868 if (!queuing) { 869 uhci_queue_fill(q, td); 870 } 871 return TD_RESULT_ASYNC_START; 872 } 873 874 done: 875 ret = uhci_complete_td(s, td, async, int_mask); 876 uhci_async_free(async); 877 return ret; 878 } 879 880 static void uhci_async_complete(USBPort *port, USBPacket *packet) 881 { 882 UHCIAsync *async = container_of(packet, UHCIAsync, packet); 883 UHCIState *s = async->queue->uhci; 884 885 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { 886 uhci_async_cancel(async); 887 return; 888 } 889 890 async->done = 1; 891 /* Force processing of this packet *now*, needed for migration */ 892 s->completions_only = true; 893 qemu_bh_schedule(s->bh); 894 } 895 896 static int is_valid(uint32_t link) 897 { 898 return (link & 1) == 0; 899 } 900 901 static int is_qh(uint32_t link) 902 { 903 return (link & 2) != 0; 904 } 905 906 static int depth_first(uint32_t link) 907 { 908 return (link & 4) != 0; 909 } 910 911 /* QH DB used for detecting QH loops */ 912 #define UHCI_MAX_QUEUES 128 913 typedef struct { 914 uint32_t addr[UHCI_MAX_QUEUES]; 915 int count; 916 } QhDb; 917 918 static void qhdb_reset(QhDb *db) 919 { 920 db->count = 0; 921 } 922 923 /* Add QH to DB. Returns 1 if already present or DB is full. */ 924 static int qhdb_insert(QhDb *db, uint32_t addr) 925 { 926 int i; 927 for (i = 0; i < db->count; i++) { 928 if (db->addr[i] == addr) { 929 return 1; 930 } 931 } 932 933 if (db->count >= UHCI_MAX_QUEUES) { 934 return 1; 935 } 936 937 db->addr[db->count++] = addr; 938 return 0; 939 } 940 941 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td) 942 { 943 uint32_t int_mask = 0; 944 uint32_t plink = td->link; 945 UHCI_TD ptd; 946 int ret; 947 948 while (is_valid(plink)) { 949 uhci_read_td(q->uhci, &ptd, plink); 950 if (!(ptd.ctrl & TD_CTRL_ACTIVE)) { 951 break; 952 } 953 if (uhci_queue_token(&ptd) != q->token) { 954 break; 955 } 956 trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token); 957 ret = uhci_handle_td(q->uhci, q, q->qh_addr, &ptd, plink, &int_mask); 958 if (ret == TD_RESULT_ASYNC_CONT) { 959 break; 960 } 961 assert(ret == TD_RESULT_ASYNC_START); 962 assert(int_mask == 0); 963 plink = ptd.link; 964 } 965 usb_device_flush_ep_queue(q->ep->dev, q->ep); 966 } 967 968 static void uhci_process_frame(UHCIState *s) 969 { 970 uint32_t frame_addr, link, old_td_ctrl, val, int_mask; 971 uint32_t curr_qh, td_count = 0; 972 int cnt, ret; 973 UHCI_TD td; 974 UHCI_QH qh; 975 QhDb qhdb; 976 977 frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); 978 979 pci_dma_read(&s->dev, frame_addr, &link, 4); 980 le32_to_cpus(&link); 981 982 int_mask = 0; 983 curr_qh = 0; 984 985 qhdb_reset(&qhdb); 986 987 for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) { 988 if (!s->completions_only && s->frame_bytes >= s->frame_bandwidth) { 989 /* 990 * We've reached the usb 1.1 bandwidth, which is 991 * 1280 bytes/frame, stop processing 992 */ 993 trace_usb_uhci_frame_stop_bandwidth(); 994 break; 995 } 996 if (is_qh(link)) { 997 /* QH */ 998 trace_usb_uhci_qh_load(link & ~0xf); 999 1000 if (qhdb_insert(&qhdb, link)) { 1001 /* 1002 * We're going in circles. Which is not a bug because 1003 * HCD is allowed to do that as part of the BW management. 1004 * 1005 * Stop processing here if no transaction has been done 1006 * since we've been here last time. 1007 */ 1008 if (td_count == 0) { 1009 trace_usb_uhci_frame_loop_stop_idle(); 1010 break; 1011 } else { 1012 trace_usb_uhci_frame_loop_continue(); 1013 td_count = 0; 1014 qhdb_reset(&qhdb); 1015 qhdb_insert(&qhdb, link); 1016 } 1017 } 1018 1019 pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh)); 1020 le32_to_cpus(&qh.link); 1021 le32_to_cpus(&qh.el_link); 1022 1023 if (!is_valid(qh.el_link)) { 1024 /* QH w/o elements */ 1025 curr_qh = 0; 1026 link = qh.link; 1027 } else { 1028 /* QH with elements */ 1029 curr_qh = link; 1030 link = qh.el_link; 1031 } 1032 continue; 1033 } 1034 1035 /* TD */ 1036 uhci_read_td(s, &td, link); 1037 trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token); 1038 1039 old_td_ctrl = td.ctrl; 1040 ret = uhci_handle_td(s, NULL, curr_qh, &td, link, &int_mask); 1041 if (old_td_ctrl != td.ctrl) { 1042 /* update the status bits of the TD */ 1043 val = cpu_to_le32(td.ctrl); 1044 pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); 1045 } 1046 1047 switch (ret) { 1048 case TD_RESULT_STOP_FRAME: /* interrupted frame */ 1049 goto out; 1050 1051 case TD_RESULT_NEXT_QH: 1052 case TD_RESULT_ASYNC_CONT: 1053 trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf); 1054 link = curr_qh ? qh.link : td.link; 1055 continue; 1056 1057 case TD_RESULT_ASYNC_START: 1058 trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf); 1059 link = curr_qh ? qh.link : td.link; 1060 continue; 1061 1062 case TD_RESULT_COMPLETE: 1063 trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf); 1064 link = td.link; 1065 td_count++; 1066 s->frame_bytes += (td.ctrl & 0x7ff) + 1; 1067 1068 if (curr_qh) { 1069 /* update QH element link */ 1070 qh.el_link = link; 1071 val = cpu_to_le32(qh.el_link); 1072 pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val)); 1073 1074 if (!depth_first(link)) { 1075 /* done with this QH */ 1076 curr_qh = 0; 1077 link = qh.link; 1078 } 1079 } 1080 break; 1081 1082 default: 1083 assert(!"unknown return code"); 1084 } 1085 1086 /* go to the next entry */ 1087 } 1088 1089 out: 1090 s->pending_int_mask |= int_mask; 1091 } 1092 1093 static void uhci_bh(void *opaque) 1094 { 1095 UHCIState *s = opaque; 1096 uhci_process_frame(s); 1097 } 1098 1099 static void uhci_frame_timer(void *opaque) 1100 { 1101 UHCIState *s = opaque; 1102 uint64_t t_now, t_last_run; 1103 int i, frames; 1104 const uint64_t frame_t = NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ; 1105 1106 s->completions_only = false; 1107 qemu_bh_cancel(s->bh); 1108 1109 if (!(s->cmd & UHCI_CMD_RS)) { 1110 /* Full stop */ 1111 trace_usb_uhci_schedule_stop(); 1112 timer_del(s->frame_timer); 1113 uhci_async_cancel_all(s); 1114 /* set hchalted bit in status - UHCI11D 2.1.2 */ 1115 s->status |= UHCI_STS_HCHALTED; 1116 return; 1117 } 1118 1119 /* We still store expire_time in our state, for migration */ 1120 t_last_run = s->expire_time - frame_t; 1121 t_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1122 1123 /* Process up to MAX_FRAMES_PER_TICK frames */ 1124 frames = (t_now - t_last_run) / frame_t; 1125 if (frames > s->maxframes) { 1126 int skipped = frames - s->maxframes; 1127 s->expire_time += skipped * frame_t; 1128 s->frnum = (s->frnum + skipped) & 0x7ff; 1129 frames -= skipped; 1130 } 1131 if (frames > MAX_FRAMES_PER_TICK) { 1132 frames = MAX_FRAMES_PER_TICK; 1133 } 1134 1135 for (i = 0; i < frames; i++) { 1136 s->frame_bytes = 0; 1137 trace_usb_uhci_frame_start(s->frnum); 1138 uhci_async_validate_begin(s); 1139 uhci_process_frame(s); 1140 uhci_async_validate_end(s); 1141 /* 1142 * The spec says frnum is the frame currently being processed, and 1143 * the guest must look at frnum - 1 on interrupt, so inc frnum now 1144 */ 1145 s->frnum = (s->frnum + 1) & 0x7ff; 1146 s->expire_time += frame_t; 1147 } 1148 1149 /* Complete the previous frame(s) */ 1150 if (s->pending_int_mask) { 1151 s->status2 |= s->pending_int_mask; 1152 s->status |= UHCI_STS_USBINT; 1153 uhci_update_irq(s); 1154 } 1155 s->pending_int_mask = 0; 1156 1157 timer_mod(s->frame_timer, t_now + frame_t); 1158 } 1159 1160 static const MemoryRegionOps uhci_ioport_ops = { 1161 .read = uhci_port_read, 1162 .write = uhci_port_write, 1163 .valid.min_access_size = 1, 1164 .valid.max_access_size = 4, 1165 .impl.min_access_size = 2, 1166 .impl.max_access_size = 2, 1167 .endianness = DEVICE_LITTLE_ENDIAN, 1168 }; 1169 1170 static USBPortOps uhci_port_ops = { 1171 .attach = uhci_attach, 1172 .detach = uhci_detach, 1173 .child_detach = uhci_child_detach, 1174 .wakeup = uhci_wakeup, 1175 .complete = uhci_async_complete, 1176 }; 1177 1178 static USBBusOps uhci_bus_ops = { 1179 }; 1180 1181 void usb_uhci_common_realize(PCIDevice *dev, Error **errp) 1182 { 1183 Error *err = NULL; 1184 UHCIPCIDeviceClass *u = UHCI_GET_CLASS(dev); 1185 UHCIState *s = UHCI(dev); 1186 uint8_t *pci_conf = s->dev.config; 1187 int i; 1188 1189 pci_conf[PCI_CLASS_PROG] = 0x00; 1190 /* TODO: reset value should be 0. */ 1191 pci_conf[USB_SBRN] = USB_RELEASE_1; /* release number */ 1192 pci_config_set_interrupt_pin(pci_conf, u->info.irq_pin + 1); 1193 s->irq = pci_allocate_irq(dev); 1194 1195 if (s->masterbus) { 1196 USBPort *ports[UHCI_PORTS]; 1197 for (i = 0; i < UHCI_PORTS; i++) { 1198 ports[i] = &s->ports[i].port; 1199 } 1200 usb_register_companion(s->masterbus, ports, UHCI_PORTS, 1201 s->firstport, s, &uhci_port_ops, 1202 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL, 1203 &err); 1204 if (err) { 1205 error_propagate(errp, err); 1206 return; 1207 } 1208 } else { 1209 usb_bus_new(&s->bus, sizeof(s->bus), &uhci_bus_ops, DEVICE(dev)); 1210 for (i = 0; i < UHCI_PORTS; i++) { 1211 usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, 1212 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); 1213 } 1214 } 1215 s->bh = qemu_bh_new_guarded(uhci_bh, s, &DEVICE(dev)->mem_reentrancy_guard); 1216 s->frame_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, uhci_frame_timer, s); 1217 s->num_ports_vmstate = UHCI_PORTS; 1218 QTAILQ_INIT(&s->queues); 1219 1220 memory_region_init_io(&s->io_bar, OBJECT(s), &uhci_ioport_ops, s, 1221 "uhci", 0x20); 1222 1223 /* 1224 * Use region 4 for consistency with real hardware. BSD guests seem 1225 * to rely on this. 1226 */ 1227 pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); 1228 } 1229 1230 static void usb_uhci_exit(PCIDevice *dev) 1231 { 1232 UHCIState *s = UHCI(dev); 1233 1234 trace_usb_uhci_exit(); 1235 1236 if (s->frame_timer) { 1237 timer_free(s->frame_timer); 1238 s->frame_timer = NULL; 1239 } 1240 1241 if (s->bh) { 1242 qemu_bh_delete(s->bh); 1243 } 1244 1245 uhci_async_cancel_all(s); 1246 1247 if (!s->masterbus) { 1248 usb_bus_release(&s->bus); 1249 } 1250 } 1251 1252 static const Property uhci_properties_companion[] = { 1253 DEFINE_PROP_STRING("masterbus", UHCIState, masterbus), 1254 DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), 1255 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), 1256 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128), 1257 }; 1258 static const Property uhci_properties_standalone[] = { 1259 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), 1260 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128), 1261 }; 1262 1263 static void uhci_class_init(ObjectClass *klass, void *data) 1264 { 1265 DeviceClass *dc = DEVICE_CLASS(klass); 1266 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1267 1268 k->class_id = PCI_CLASS_SERIAL_USB; 1269 dc->vmsd = &vmstate_uhci; 1270 device_class_set_legacy_reset(dc, uhci_reset); 1271 set_bit(DEVICE_CATEGORY_USB, dc->categories); 1272 } 1273 1274 static const TypeInfo uhci_pci_type_info = { 1275 .name = TYPE_UHCI, 1276 .parent = TYPE_PCI_DEVICE, 1277 .instance_size = sizeof(UHCIState), 1278 .class_size = sizeof(UHCIPCIDeviceClass), 1279 .abstract = true, 1280 .class_init = uhci_class_init, 1281 .interfaces = (InterfaceInfo[]) { 1282 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1283 { }, 1284 }, 1285 }; 1286 1287 void uhci_data_class_init(ObjectClass *klass, void *data) 1288 { 1289 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1290 DeviceClass *dc = DEVICE_CLASS(klass); 1291 UHCIPCIDeviceClass *u = UHCI_CLASS(klass); 1292 const UHCIInfo *info = data; 1293 1294 k->realize = info->realize ? info->realize : usb_uhci_common_realize; 1295 k->exit = info->unplug ? usb_uhci_exit : NULL; 1296 k->vendor_id = info->vendor_id; 1297 k->device_id = info->device_id; 1298 k->revision = info->revision; 1299 if (!info->unplug) { 1300 /* uhci controllers in companion setups can't be hotplugged */ 1301 dc->hotpluggable = false; 1302 device_class_set_props(dc, uhci_properties_companion); 1303 } else { 1304 device_class_set_props(dc, uhci_properties_standalone); 1305 } 1306 if (info->notuser) { 1307 dc->user_creatable = false; 1308 } 1309 u->info = *info; 1310 } 1311 1312 static UHCIInfo uhci_info[] = { 1313 { 1314 .name = TYPE_PIIX3_USB_UHCI, 1315 .vendor_id = PCI_VENDOR_ID_INTEL, 1316 .device_id = PCI_DEVICE_ID_INTEL_82371SB_2, 1317 .revision = 0x01, 1318 .irq_pin = 3, 1319 .unplug = true, 1320 },{ 1321 .name = TYPE_PIIX4_USB_UHCI, 1322 .vendor_id = PCI_VENDOR_ID_INTEL, 1323 .device_id = PCI_DEVICE_ID_INTEL_82371AB_2, 1324 .revision = 0x01, 1325 .irq_pin = 3, 1326 .unplug = true, 1327 },{ 1328 .name = TYPE_ICH9_USB_UHCI(1), /* 00:1d.0 */ 1329 .vendor_id = PCI_VENDOR_ID_INTEL, 1330 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1, 1331 .revision = 0x03, 1332 .irq_pin = 0, 1333 .unplug = false, 1334 },{ 1335 .name = TYPE_ICH9_USB_UHCI(2), /* 00:1d.1 */ 1336 .vendor_id = PCI_VENDOR_ID_INTEL, 1337 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2, 1338 .revision = 0x03, 1339 .irq_pin = 1, 1340 .unplug = false, 1341 },{ 1342 .name = TYPE_ICH9_USB_UHCI(3), /* 00:1d.2 */ 1343 .vendor_id = PCI_VENDOR_ID_INTEL, 1344 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3, 1345 .revision = 0x03, 1346 .irq_pin = 2, 1347 .unplug = false, 1348 },{ 1349 .name = TYPE_ICH9_USB_UHCI(4), /* 00:1a.0 */ 1350 .vendor_id = PCI_VENDOR_ID_INTEL, 1351 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI4, 1352 .revision = 0x03, 1353 .irq_pin = 0, 1354 .unplug = false, 1355 },{ 1356 .name = TYPE_ICH9_USB_UHCI(5), /* 00:1a.1 */ 1357 .vendor_id = PCI_VENDOR_ID_INTEL, 1358 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI5, 1359 .revision = 0x03, 1360 .irq_pin = 1, 1361 .unplug = false, 1362 },{ 1363 .name = TYPE_ICH9_USB_UHCI(6), /* 00:1a.2 */ 1364 .vendor_id = PCI_VENDOR_ID_INTEL, 1365 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI6, 1366 .revision = 0x03, 1367 .irq_pin = 2, 1368 .unplug = false, 1369 } 1370 }; 1371 1372 static void uhci_register_types(void) 1373 { 1374 TypeInfo uhci_type_info = { 1375 .parent = TYPE_UHCI, 1376 .class_init = uhci_data_class_init, 1377 }; 1378 int i; 1379 1380 type_register_static(&uhci_pci_type_info); 1381 1382 for (i = 0; i < ARRAY_SIZE(uhci_info); i++) { 1383 uhci_type_info.name = uhci_info[i].name; 1384 uhci_type_info.class_data = uhci_info + i; 1385 type_register_static(&uhci_type_info); 1386 } 1387 } 1388 1389 type_init(uhci_register_types) 1390