1 /* 2 * tpm_tis.c - QEMU's TPM TIS interface emulator 3 * 4 * Copyright (C) 2006,2010-2013 IBM Corporation 5 * 6 * Authors: 7 * Stefan Berger <stefanb@us.ibm.com> 8 * David Safford <safford@us.ibm.com> 9 * 10 * Xen 4 support: Andrease Niederl <andreas.niederl@iaik.tugraz.at> 11 * 12 * This work is licensed under the terms of the GNU GPL, version 2 or later. 13 * See the COPYING file in the top-level directory. 14 * 15 * Implementation of the TIS interface according to specs found at 16 * http://www.trustedcomputinggroup.org. This implementation currently 17 * supports version 1.3, 21 March 2013 18 * In the developers menu choose the PC Client section then find the TIS 19 * specification. 20 * 21 * TPM TIS for TPM 2 implementation following TCG PC Client Platform 22 * TPM Profile (PTP) Specification, Familiy 2.0, Revision 00.43 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/isa/isa.h" 27 #include "qapi/error.h" 28 29 #include "hw/acpi/tpm.h" 30 #include "hw/pci/pci_ids.h" 31 #include "sysemu/tpm_backend.h" 32 #include "tpm_int.h" 33 #include "tpm_util.h" 34 35 #define TPM_TIS_NUM_LOCALITIES 5 /* per spec */ 36 #define TPM_TIS_LOCALITY_SHIFT 12 37 #define TPM_TIS_NO_LOCALITY 0xff 38 39 #define TPM_TIS_IS_VALID_LOCTY(x) ((x) < TPM_TIS_NUM_LOCALITIES) 40 41 #define TPM_TIS_BUFFER_MAX 4096 42 43 typedef enum { 44 TPM_TIS_STATE_IDLE = 0, 45 TPM_TIS_STATE_READY, 46 TPM_TIS_STATE_COMPLETION, 47 TPM_TIS_STATE_EXECUTION, 48 TPM_TIS_STATE_RECEPTION, 49 } TPMTISState; 50 51 /* locality data -- all fields are persisted */ 52 typedef struct TPMLocality { 53 TPMTISState state; 54 uint8_t access; 55 uint32_t sts; 56 uint32_t iface_id; 57 uint32_t inte; 58 uint32_t ints; 59 } TPMLocality; 60 61 typedef struct TPMState { 62 ISADevice busdev; 63 MemoryRegion mmio; 64 65 unsigned char buffer[TPM_TIS_BUFFER_MAX]; 66 uint16_t rw_offset; 67 68 uint8_t active_locty; 69 uint8_t aborting_locty; 70 uint8_t next_locty; 71 72 TPMLocality loc[TPM_TIS_NUM_LOCALITIES]; 73 74 qemu_irq irq; 75 uint32_t irq_num; 76 77 TPMBackendCmd cmd; 78 79 TPMBackend *be_driver; 80 TPMVersion be_tpm_version; 81 82 size_t be_buffer_size; 83 } TPMState; 84 85 #define TPM(obj) OBJECT_CHECK(TPMState, (obj), TYPE_TPM_TIS) 86 87 #define DEBUG_TIS 0 88 89 #define DPRINTF(fmt, ...) do { \ 90 if (DEBUG_TIS) { \ 91 printf(fmt, ## __VA_ARGS__); \ 92 } \ 93 } while (0) 94 95 /* tis registers */ 96 #define TPM_TIS_REG_ACCESS 0x00 97 #define TPM_TIS_REG_INT_ENABLE 0x08 98 #define TPM_TIS_REG_INT_VECTOR 0x0c 99 #define TPM_TIS_REG_INT_STATUS 0x10 100 #define TPM_TIS_REG_INTF_CAPABILITY 0x14 101 #define TPM_TIS_REG_STS 0x18 102 #define TPM_TIS_REG_DATA_FIFO 0x24 103 #define TPM_TIS_REG_INTERFACE_ID 0x30 104 #define TPM_TIS_REG_DATA_XFIFO 0x80 105 #define TPM_TIS_REG_DATA_XFIFO_END 0xbc 106 #define TPM_TIS_REG_DID_VID 0xf00 107 #define TPM_TIS_REG_RID 0xf04 108 109 /* vendor-specific registers */ 110 #define TPM_TIS_REG_DEBUG 0xf90 111 112 #define TPM_TIS_STS_TPM_FAMILY_MASK (0x3 << 26)/* TPM 2.0 */ 113 #define TPM_TIS_STS_TPM_FAMILY1_2 (0 << 26) /* TPM 2.0 */ 114 #define TPM_TIS_STS_TPM_FAMILY2_0 (1 << 26) /* TPM 2.0 */ 115 #define TPM_TIS_STS_RESET_ESTABLISHMENT_BIT (1 << 25) /* TPM 2.0 */ 116 #define TPM_TIS_STS_COMMAND_CANCEL (1 << 24) /* TPM 2.0 */ 117 118 #define TPM_TIS_STS_VALID (1 << 7) 119 #define TPM_TIS_STS_COMMAND_READY (1 << 6) 120 #define TPM_TIS_STS_TPM_GO (1 << 5) 121 #define TPM_TIS_STS_DATA_AVAILABLE (1 << 4) 122 #define TPM_TIS_STS_EXPECT (1 << 3) 123 #define TPM_TIS_STS_SELFTEST_DONE (1 << 2) 124 #define TPM_TIS_STS_RESPONSE_RETRY (1 << 1) 125 126 #define TPM_TIS_BURST_COUNT_SHIFT 8 127 #define TPM_TIS_BURST_COUNT(X) \ 128 ((X) << TPM_TIS_BURST_COUNT_SHIFT) 129 130 #define TPM_TIS_ACCESS_TPM_REG_VALID_STS (1 << 7) 131 #define TPM_TIS_ACCESS_ACTIVE_LOCALITY (1 << 5) 132 #define TPM_TIS_ACCESS_BEEN_SEIZED (1 << 4) 133 #define TPM_TIS_ACCESS_SEIZE (1 << 3) 134 #define TPM_TIS_ACCESS_PENDING_REQUEST (1 << 2) 135 #define TPM_TIS_ACCESS_REQUEST_USE (1 << 1) 136 #define TPM_TIS_ACCESS_TPM_ESTABLISHMENT (1 << 0) 137 138 #define TPM_TIS_INT_ENABLED (1 << 31) 139 #define TPM_TIS_INT_DATA_AVAILABLE (1 << 0) 140 #define TPM_TIS_INT_STS_VALID (1 << 1) 141 #define TPM_TIS_INT_LOCALITY_CHANGED (1 << 2) 142 #define TPM_TIS_INT_COMMAND_READY (1 << 7) 143 144 #define TPM_TIS_INT_POLARITY_MASK (3 << 3) 145 #define TPM_TIS_INT_POLARITY_LOW_LEVEL (1 << 3) 146 147 #define TPM_TIS_INTERRUPTS_SUPPORTED (TPM_TIS_INT_LOCALITY_CHANGED | \ 148 TPM_TIS_INT_DATA_AVAILABLE | \ 149 TPM_TIS_INT_STS_VALID | \ 150 TPM_TIS_INT_COMMAND_READY) 151 152 #define TPM_TIS_CAP_INTERFACE_VERSION1_3 (2 << 28) 153 #define TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 (3 << 28) 154 #define TPM_TIS_CAP_DATA_TRANSFER_64B (3 << 9) 155 #define TPM_TIS_CAP_DATA_TRANSFER_LEGACY (0 << 9) 156 #define TPM_TIS_CAP_BURST_COUNT_DYNAMIC (0 << 8) 157 #define TPM_TIS_CAP_INTERRUPT_LOW_LEVEL (1 << 4) /* support is mandatory */ 158 #define TPM_TIS_CAPABILITIES_SUPPORTED1_3 \ 159 (TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \ 160 TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \ 161 TPM_TIS_CAP_DATA_TRANSFER_64B | \ 162 TPM_TIS_CAP_INTERFACE_VERSION1_3 | \ 163 TPM_TIS_INTERRUPTS_SUPPORTED) 164 165 #define TPM_TIS_CAPABILITIES_SUPPORTED2_0 \ 166 (TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \ 167 TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \ 168 TPM_TIS_CAP_DATA_TRANSFER_64B | \ 169 TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 | \ 170 TPM_TIS_INTERRUPTS_SUPPORTED) 171 172 #define TPM_TIS_IFACE_ID_INTERFACE_TIS1_3 (0xf) /* TPM 2.0 */ 173 #define TPM_TIS_IFACE_ID_INTERFACE_FIFO (0x0) /* TPM 2.0 */ 174 #define TPM_TIS_IFACE_ID_INTERFACE_VER_FIFO (0 << 4) /* TPM 2.0 */ 175 #define TPM_TIS_IFACE_ID_CAP_5_LOCALITIES (1 << 8) /* TPM 2.0 */ 176 #define TPM_TIS_IFACE_ID_CAP_TIS_SUPPORTED (1 << 13) /* TPM 2.0 */ 177 #define TPM_TIS_IFACE_ID_INT_SEL_LOCK (1 << 19) /* TPM 2.0 */ 178 179 #define TPM_TIS_IFACE_ID_SUPPORTED_FLAGS1_3 \ 180 (TPM_TIS_IFACE_ID_INTERFACE_TIS1_3 | \ 181 (~0u << 4)/* all of it is don't care */) 182 183 /* if backend was a TPM 2.0: */ 184 #define TPM_TIS_IFACE_ID_SUPPORTED_FLAGS2_0 \ 185 (TPM_TIS_IFACE_ID_INTERFACE_FIFO | \ 186 TPM_TIS_IFACE_ID_INTERFACE_VER_FIFO | \ 187 TPM_TIS_IFACE_ID_CAP_5_LOCALITIES | \ 188 TPM_TIS_IFACE_ID_CAP_TIS_SUPPORTED) 189 190 #define TPM_TIS_TPM_DID 0x0001 191 #define TPM_TIS_TPM_VID PCI_VENDOR_ID_IBM 192 #define TPM_TIS_TPM_RID 0x0001 193 194 #define TPM_TIS_NO_DATA_BYTE 0xff 195 196 /* local prototypes */ 197 198 static uint64_t tpm_tis_mmio_read(void *opaque, hwaddr addr, 199 unsigned size); 200 201 /* utility functions */ 202 203 static uint8_t tpm_tis_locality_from_addr(hwaddr addr) 204 { 205 return (uint8_t)((addr >> TPM_TIS_LOCALITY_SHIFT) & 0x7); 206 } 207 208 static void tpm_tis_show_buffer(const unsigned char *buffer, 209 size_t buffer_size, const char *string) 210 { 211 #ifdef DEBUG_TIS 212 uint32_t len, i; 213 214 len = MIN(tpm_cmd_get_size(buffer), buffer_size); 215 DPRINTF("tpm_tis: %s length = %d\n", string, len); 216 for (i = 0; i < len; i++) { 217 if (i && !(i % 16)) { 218 DPRINTF("\n"); 219 } 220 DPRINTF("%.2X ", buffer[i]); 221 } 222 DPRINTF("\n"); 223 #endif 224 } 225 226 /* 227 * Set the given flags in the STS register by clearing the register but 228 * preserving the SELFTEST_DONE and TPM_FAMILY_MASK flags and then setting 229 * the new flags. 230 * 231 * The SELFTEST_DONE flag is acquired from the backend that determines it by 232 * peeking into TPM commands. 233 * 234 * A VM suspend/resume will preserve the flag by storing it into the VM 235 * device state, but the backend will not remember it when QEMU is started 236 * again. Therefore, we cache the flag here. Once set, it will not be unset 237 * except by a reset. 238 */ 239 static void tpm_tis_sts_set(TPMLocality *l, uint32_t flags) 240 { 241 l->sts &= TPM_TIS_STS_SELFTEST_DONE | TPM_TIS_STS_TPM_FAMILY_MASK; 242 l->sts |= flags; 243 } 244 245 /* 246 * Send a request to the TPM. 247 */ 248 static void tpm_tis_tpm_send(TPMState *s, uint8_t locty) 249 { 250 tpm_tis_show_buffer(s->buffer, s->be_buffer_size, 251 "tpm_tis: To TPM"); 252 253 /* 254 * rw_offset serves as length indicator for length of data; 255 * it's reset when the response comes back 256 */ 257 s->loc[locty].state = TPM_TIS_STATE_EXECUTION; 258 259 s->cmd = (TPMBackendCmd) { 260 .locty = locty, 261 .in = s->buffer, 262 .in_len = s->rw_offset, 263 .out = s->buffer, 264 .out_len = s->be_buffer_size, 265 }; 266 267 tpm_backend_deliver_request(s->be_driver, &s->cmd); 268 } 269 270 /* raise an interrupt if allowed */ 271 static void tpm_tis_raise_irq(TPMState *s, uint8_t locty, uint32_t irqmask) 272 { 273 if (!TPM_TIS_IS_VALID_LOCTY(locty)) { 274 return; 275 } 276 277 if ((s->loc[locty].inte & TPM_TIS_INT_ENABLED) && 278 (s->loc[locty].inte & irqmask)) { 279 DPRINTF("tpm_tis: Raising IRQ for flag %08x\n", irqmask); 280 qemu_irq_raise(s->irq); 281 s->loc[locty].ints |= irqmask; 282 } 283 } 284 285 static uint32_t tpm_tis_check_request_use_except(TPMState *s, uint8_t locty) 286 { 287 uint8_t l; 288 289 for (l = 0; l < TPM_TIS_NUM_LOCALITIES; l++) { 290 if (l == locty) { 291 continue; 292 } 293 if ((s->loc[l].access & TPM_TIS_ACCESS_REQUEST_USE)) { 294 return 1; 295 } 296 } 297 298 return 0; 299 } 300 301 static void tpm_tis_new_active_locality(TPMState *s, uint8_t new_active_locty) 302 { 303 bool change = (s->active_locty != new_active_locty); 304 bool is_seize; 305 uint8_t mask; 306 307 if (change && TPM_TIS_IS_VALID_LOCTY(s->active_locty)) { 308 is_seize = TPM_TIS_IS_VALID_LOCTY(new_active_locty) && 309 s->loc[new_active_locty].access & TPM_TIS_ACCESS_SEIZE; 310 311 if (is_seize) { 312 mask = ~(TPM_TIS_ACCESS_ACTIVE_LOCALITY); 313 } else { 314 mask = ~(TPM_TIS_ACCESS_ACTIVE_LOCALITY| 315 TPM_TIS_ACCESS_REQUEST_USE); 316 } 317 /* reset flags on the old active locality */ 318 s->loc[s->active_locty].access &= mask; 319 320 if (is_seize) { 321 s->loc[s->active_locty].access |= TPM_TIS_ACCESS_BEEN_SEIZED; 322 } 323 } 324 325 s->active_locty = new_active_locty; 326 327 DPRINTF("tpm_tis: Active locality is now %d\n", s->active_locty); 328 329 if (TPM_TIS_IS_VALID_LOCTY(new_active_locty)) { 330 /* set flags on the new active locality */ 331 s->loc[new_active_locty].access |= TPM_TIS_ACCESS_ACTIVE_LOCALITY; 332 s->loc[new_active_locty].access &= ~(TPM_TIS_ACCESS_REQUEST_USE | 333 TPM_TIS_ACCESS_SEIZE); 334 } 335 336 if (change) { 337 tpm_tis_raise_irq(s, s->active_locty, TPM_TIS_INT_LOCALITY_CHANGED); 338 } 339 } 340 341 /* abort -- this function switches the locality */ 342 static void tpm_tis_abort(TPMState *s, uint8_t locty) 343 { 344 s->rw_offset = 0; 345 346 DPRINTF("tpm_tis: tis_abort: new active locality is %d\n", s->next_locty); 347 348 /* 349 * Need to react differently depending on who's aborting now and 350 * which locality will become active afterwards. 351 */ 352 if (s->aborting_locty == s->next_locty) { 353 s->loc[s->aborting_locty].state = TPM_TIS_STATE_READY; 354 tpm_tis_sts_set(&s->loc[s->aborting_locty], 355 TPM_TIS_STS_COMMAND_READY); 356 tpm_tis_raise_irq(s, s->aborting_locty, TPM_TIS_INT_COMMAND_READY); 357 } 358 359 /* locality after abort is another one than the current one */ 360 tpm_tis_new_active_locality(s, s->next_locty); 361 362 s->next_locty = TPM_TIS_NO_LOCALITY; 363 /* nobody's aborting a command anymore */ 364 s->aborting_locty = TPM_TIS_NO_LOCALITY; 365 } 366 367 /* prepare aborting current command */ 368 static void tpm_tis_prep_abort(TPMState *s, uint8_t locty, uint8_t newlocty) 369 { 370 uint8_t busy_locty; 371 372 s->aborting_locty = locty; 373 s->next_locty = newlocty; /* locality after successful abort */ 374 375 /* 376 * only abort a command using an interrupt if currently executing 377 * a command AND if there's a valid connection to the vTPM. 378 */ 379 for (busy_locty = 0; busy_locty < TPM_TIS_NUM_LOCALITIES; busy_locty++) { 380 if (s->loc[busy_locty].state == TPM_TIS_STATE_EXECUTION) { 381 /* 382 * request the backend to cancel. Some backends may not 383 * support it 384 */ 385 tpm_backend_cancel_cmd(s->be_driver); 386 return; 387 } 388 } 389 390 tpm_tis_abort(s, locty); 391 } 392 393 /* 394 * Callback from the TPM to indicate that the response was received. 395 */ 396 static void tpm_tis_request_completed(TPMIf *ti, int ret) 397 { 398 TPMState *s = TPM(ti); 399 uint8_t locty = s->cmd.locty; 400 uint8_t l; 401 402 if (s->cmd.selftest_done) { 403 for (l = 0; l < TPM_TIS_NUM_LOCALITIES; l++) { 404 s->loc[locty].sts |= TPM_TIS_STS_SELFTEST_DONE; 405 } 406 } 407 408 /* FIXME: report error if ret != 0 */ 409 tpm_tis_sts_set(&s->loc[locty], 410 TPM_TIS_STS_VALID | TPM_TIS_STS_DATA_AVAILABLE); 411 s->loc[locty].state = TPM_TIS_STATE_COMPLETION; 412 s->rw_offset = 0; 413 414 tpm_tis_show_buffer(s->buffer, s->be_buffer_size, 415 "tpm_tis: From TPM"); 416 417 if (TPM_TIS_IS_VALID_LOCTY(s->next_locty)) { 418 tpm_tis_abort(s, locty); 419 } 420 421 tpm_tis_raise_irq(s, locty, 422 TPM_TIS_INT_DATA_AVAILABLE | TPM_TIS_INT_STS_VALID); 423 } 424 425 /* 426 * Read a byte of response data 427 */ 428 static uint32_t tpm_tis_data_read(TPMState *s, uint8_t locty) 429 { 430 uint32_t ret = TPM_TIS_NO_DATA_BYTE; 431 uint16_t len; 432 433 if ((s->loc[locty].sts & TPM_TIS_STS_DATA_AVAILABLE)) { 434 len = MIN(tpm_cmd_get_size(&s->buffer), 435 s->be_buffer_size); 436 437 ret = s->buffer[s->rw_offset++]; 438 if (s->rw_offset >= len) { 439 /* got last byte */ 440 tpm_tis_sts_set(&s->loc[locty], TPM_TIS_STS_VALID); 441 tpm_tis_raise_irq(s, locty, TPM_TIS_INT_STS_VALID); 442 } 443 DPRINTF("tpm_tis: tpm_tis_data_read byte 0x%02x [%d]\n", 444 ret, s->rw_offset - 1); 445 } 446 447 return ret; 448 } 449 450 #ifdef DEBUG_TIS 451 static void tpm_tis_dump_state(void *opaque, hwaddr addr) 452 { 453 static const unsigned regs[] = { 454 TPM_TIS_REG_ACCESS, 455 TPM_TIS_REG_INT_ENABLE, 456 TPM_TIS_REG_INT_VECTOR, 457 TPM_TIS_REG_INT_STATUS, 458 TPM_TIS_REG_INTF_CAPABILITY, 459 TPM_TIS_REG_STS, 460 TPM_TIS_REG_DID_VID, 461 TPM_TIS_REG_RID, 462 0xfff}; 463 int idx; 464 uint8_t locty = tpm_tis_locality_from_addr(addr); 465 hwaddr base = addr & ~0xfff; 466 TPMState *s = opaque; 467 468 DPRINTF("tpm_tis: active locality : %d\n" 469 "tpm_tis: state of locality %d : %d\n" 470 "tpm_tis: register dump:\n", 471 s->active_locty, 472 locty, s->loc[locty].state); 473 474 for (idx = 0; regs[idx] != 0xfff; idx++) { 475 DPRINTF("tpm_tis: 0x%04x : 0x%08x\n", regs[idx], 476 (int)tpm_tis_mmio_read(opaque, base + regs[idx], 4)); 477 } 478 479 DPRINTF("tpm_tis: r/w offset : %d\n" 480 "tpm_tis: result buffer : ", 481 s->rw_offset); 482 for (idx = 0; 483 idx < MIN(tpm_cmd_get_size(&s->buffer), s->be_buffer_size); 484 idx++) { 485 DPRINTF("%c%02x%s", 486 s->rw_offset == idx ? '>' : ' ', 487 s->buffer[idx], 488 ((idx & 0xf) == 0xf) ? "\ntpm_tis: " : ""); 489 } 490 DPRINTF("\n"); 491 } 492 #endif 493 494 /* 495 * Read a register of the TIS interface 496 * See specs pages 33-63 for description of the registers 497 */ 498 static uint64_t tpm_tis_mmio_read(void *opaque, hwaddr addr, 499 unsigned size) 500 { 501 TPMState *s = opaque; 502 uint16_t offset = addr & 0xffc; 503 uint8_t shift = (addr & 0x3) * 8; 504 uint32_t val = 0xffffffff; 505 uint8_t locty = tpm_tis_locality_from_addr(addr); 506 uint32_t avail; 507 uint8_t v; 508 509 if (tpm_backend_had_startup_error(s->be_driver)) { 510 return 0; 511 } 512 513 switch (offset) { 514 case TPM_TIS_REG_ACCESS: 515 /* never show the SEIZE flag even though we use it internally */ 516 val = s->loc[locty].access & ~TPM_TIS_ACCESS_SEIZE; 517 /* the pending flag is always calculated */ 518 if (tpm_tis_check_request_use_except(s, locty)) { 519 val |= TPM_TIS_ACCESS_PENDING_REQUEST; 520 } 521 val |= !tpm_backend_get_tpm_established_flag(s->be_driver); 522 break; 523 case TPM_TIS_REG_INT_ENABLE: 524 val = s->loc[locty].inte; 525 break; 526 case TPM_TIS_REG_INT_VECTOR: 527 val = s->irq_num; 528 break; 529 case TPM_TIS_REG_INT_STATUS: 530 val = s->loc[locty].ints; 531 break; 532 case TPM_TIS_REG_INTF_CAPABILITY: 533 switch (s->be_tpm_version) { 534 case TPM_VERSION_UNSPEC: 535 val = 0; 536 break; 537 case TPM_VERSION_1_2: 538 val = TPM_TIS_CAPABILITIES_SUPPORTED1_3; 539 break; 540 case TPM_VERSION_2_0: 541 val = TPM_TIS_CAPABILITIES_SUPPORTED2_0; 542 break; 543 } 544 break; 545 case TPM_TIS_REG_STS: 546 if (s->active_locty == locty) { 547 if ((s->loc[locty].sts & TPM_TIS_STS_DATA_AVAILABLE)) { 548 val = TPM_TIS_BURST_COUNT( 549 MIN(tpm_cmd_get_size(&s->buffer), 550 s->be_buffer_size) 551 - s->rw_offset) | s->loc[locty].sts; 552 } else { 553 avail = s->be_buffer_size - s->rw_offset; 554 /* 555 * byte-sized reads should not return 0x00 for 0x100 556 * available bytes. 557 */ 558 if (size == 1 && avail > 0xff) { 559 avail = 0xff; 560 } 561 val = TPM_TIS_BURST_COUNT(avail) | s->loc[locty].sts; 562 } 563 } 564 break; 565 case TPM_TIS_REG_DATA_FIFO: 566 case TPM_TIS_REG_DATA_XFIFO ... TPM_TIS_REG_DATA_XFIFO_END: 567 if (s->active_locty == locty) { 568 if (size > 4 - (addr & 0x3)) { 569 /* prevent access beyond FIFO */ 570 size = 4 - (addr & 0x3); 571 } 572 val = 0; 573 shift = 0; 574 while (size > 0) { 575 switch (s->loc[locty].state) { 576 case TPM_TIS_STATE_COMPLETION: 577 v = tpm_tis_data_read(s, locty); 578 break; 579 default: 580 v = TPM_TIS_NO_DATA_BYTE; 581 break; 582 } 583 val |= (v << shift); 584 shift += 8; 585 size--; 586 } 587 shift = 0; /* no more adjustments */ 588 } 589 break; 590 case TPM_TIS_REG_INTERFACE_ID: 591 val = s->loc[locty].iface_id; 592 break; 593 case TPM_TIS_REG_DID_VID: 594 val = (TPM_TIS_TPM_DID << 16) | TPM_TIS_TPM_VID; 595 break; 596 case TPM_TIS_REG_RID: 597 val = TPM_TIS_TPM_RID; 598 break; 599 #ifdef DEBUG_TIS 600 case TPM_TIS_REG_DEBUG: 601 tpm_tis_dump_state(opaque, addr); 602 break; 603 #endif 604 } 605 606 if (shift) { 607 val >>= shift; 608 } 609 610 DPRINTF("tpm_tis: read.%u(%08x) = %08x\n", size, (int)addr, (int)val); 611 612 return val; 613 } 614 615 /* 616 * Write a value to a register of the TIS interface 617 * See specs pages 33-63 for description of the registers 618 */ 619 static void tpm_tis_mmio_write(void *opaque, hwaddr addr, 620 uint64_t val, unsigned size) 621 { 622 TPMState *s = opaque; 623 uint16_t off = addr & 0xffc; 624 uint8_t shift = (addr & 0x3) * 8; 625 uint8_t locty = tpm_tis_locality_from_addr(addr); 626 uint8_t active_locty, l; 627 int c, set_new_locty = 1; 628 uint16_t len; 629 uint32_t mask = (size == 1) ? 0xff : ((size == 2) ? 0xffff : ~0); 630 631 DPRINTF("tpm_tis: write.%u(%08x) = %08x\n", size, (int)addr, (int)val); 632 633 if (locty == 4) { 634 DPRINTF("tpm_tis: Access to locality 4 only allowed from hardware\n"); 635 return; 636 } 637 638 if (tpm_backend_had_startup_error(s->be_driver)) { 639 return; 640 } 641 642 val &= mask; 643 644 if (shift) { 645 val <<= shift; 646 mask <<= shift; 647 } 648 649 mask ^= 0xffffffff; 650 651 switch (off) { 652 case TPM_TIS_REG_ACCESS: 653 654 if ((val & TPM_TIS_ACCESS_SEIZE)) { 655 val &= ~(TPM_TIS_ACCESS_REQUEST_USE | 656 TPM_TIS_ACCESS_ACTIVE_LOCALITY); 657 } 658 659 active_locty = s->active_locty; 660 661 if ((val & TPM_TIS_ACCESS_ACTIVE_LOCALITY)) { 662 /* give up locality if currently owned */ 663 if (s->active_locty == locty) { 664 DPRINTF("tpm_tis: Releasing locality %d\n", locty); 665 666 uint8_t newlocty = TPM_TIS_NO_LOCALITY; 667 /* anybody wants the locality ? */ 668 for (c = TPM_TIS_NUM_LOCALITIES - 1; c >= 0; c--) { 669 if ((s->loc[c].access & TPM_TIS_ACCESS_REQUEST_USE)) { 670 DPRINTF("tpm_tis: Locality %d requests use.\n", c); 671 newlocty = c; 672 break; 673 } 674 } 675 DPRINTF("tpm_tis: TPM_TIS_ACCESS_ACTIVE_LOCALITY: " 676 "Next active locality: %d\n", 677 newlocty); 678 679 if (TPM_TIS_IS_VALID_LOCTY(newlocty)) { 680 set_new_locty = 0; 681 tpm_tis_prep_abort(s, locty, newlocty); 682 } else { 683 active_locty = TPM_TIS_NO_LOCALITY; 684 } 685 } else { 686 /* not currently the owner; clear a pending request */ 687 s->loc[locty].access &= ~TPM_TIS_ACCESS_REQUEST_USE; 688 } 689 } 690 691 if ((val & TPM_TIS_ACCESS_BEEN_SEIZED)) { 692 s->loc[locty].access &= ~TPM_TIS_ACCESS_BEEN_SEIZED; 693 } 694 695 if ((val & TPM_TIS_ACCESS_SEIZE)) { 696 /* 697 * allow seize if a locality is active and the requesting 698 * locality is higher than the one that's active 699 * OR 700 * allow seize for requesting locality if no locality is 701 * active 702 */ 703 while ((TPM_TIS_IS_VALID_LOCTY(s->active_locty) && 704 locty > s->active_locty) || 705 !TPM_TIS_IS_VALID_LOCTY(s->active_locty)) { 706 bool higher_seize = FALSE; 707 708 /* already a pending SEIZE ? */ 709 if ((s->loc[locty].access & TPM_TIS_ACCESS_SEIZE)) { 710 break; 711 } 712 713 /* check for ongoing seize by a higher locality */ 714 for (l = locty + 1; l < TPM_TIS_NUM_LOCALITIES; l++) { 715 if ((s->loc[l].access & TPM_TIS_ACCESS_SEIZE)) { 716 higher_seize = TRUE; 717 break; 718 } 719 } 720 721 if (higher_seize) { 722 break; 723 } 724 725 /* cancel any seize by a lower locality */ 726 for (l = 0; l < locty - 1; l++) { 727 s->loc[l].access &= ~TPM_TIS_ACCESS_SEIZE; 728 } 729 730 s->loc[locty].access |= TPM_TIS_ACCESS_SEIZE; 731 DPRINTF("tpm_tis: TPM_TIS_ACCESS_SEIZE: " 732 "Locality %d seized from locality %d\n", 733 locty, s->active_locty); 734 DPRINTF("tpm_tis: TPM_TIS_ACCESS_SEIZE: Initiating abort.\n"); 735 set_new_locty = 0; 736 tpm_tis_prep_abort(s, s->active_locty, locty); 737 break; 738 } 739 } 740 741 if ((val & TPM_TIS_ACCESS_REQUEST_USE)) { 742 if (s->active_locty != locty) { 743 if (TPM_TIS_IS_VALID_LOCTY(s->active_locty)) { 744 s->loc[locty].access |= TPM_TIS_ACCESS_REQUEST_USE; 745 } else { 746 /* no locality active -> make this one active now */ 747 active_locty = locty; 748 } 749 } 750 } 751 752 if (set_new_locty) { 753 tpm_tis_new_active_locality(s, active_locty); 754 } 755 756 break; 757 case TPM_TIS_REG_INT_ENABLE: 758 if (s->active_locty != locty) { 759 break; 760 } 761 762 s->loc[locty].inte &= mask; 763 s->loc[locty].inte |= (val & (TPM_TIS_INT_ENABLED | 764 TPM_TIS_INT_POLARITY_MASK | 765 TPM_TIS_INTERRUPTS_SUPPORTED)); 766 break; 767 case TPM_TIS_REG_INT_VECTOR: 768 /* hard wired -- ignore */ 769 break; 770 case TPM_TIS_REG_INT_STATUS: 771 if (s->active_locty != locty) { 772 break; 773 } 774 775 /* clearing of interrupt flags */ 776 if (((val & TPM_TIS_INTERRUPTS_SUPPORTED)) && 777 (s->loc[locty].ints & TPM_TIS_INTERRUPTS_SUPPORTED)) { 778 s->loc[locty].ints &= ~val; 779 if (s->loc[locty].ints == 0) { 780 qemu_irq_lower(s->irq); 781 DPRINTF("tpm_tis: Lowering IRQ\n"); 782 } 783 } 784 s->loc[locty].ints &= ~(val & TPM_TIS_INTERRUPTS_SUPPORTED); 785 break; 786 case TPM_TIS_REG_STS: 787 if (s->active_locty != locty) { 788 break; 789 } 790 791 if (s->be_tpm_version == TPM_VERSION_2_0) { 792 /* some flags that are only supported for TPM 2 */ 793 if (val & TPM_TIS_STS_COMMAND_CANCEL) { 794 if (s->loc[locty].state == TPM_TIS_STATE_EXECUTION) { 795 /* 796 * request the backend to cancel. Some backends may not 797 * support it 798 */ 799 tpm_backend_cancel_cmd(s->be_driver); 800 } 801 } 802 803 if (val & TPM_TIS_STS_RESET_ESTABLISHMENT_BIT) { 804 if (locty == 3 || locty == 4) { 805 tpm_backend_reset_tpm_established_flag(s->be_driver, locty); 806 } 807 } 808 } 809 810 val &= (TPM_TIS_STS_COMMAND_READY | TPM_TIS_STS_TPM_GO | 811 TPM_TIS_STS_RESPONSE_RETRY); 812 813 if (val == TPM_TIS_STS_COMMAND_READY) { 814 switch (s->loc[locty].state) { 815 816 case TPM_TIS_STATE_READY: 817 s->rw_offset = 0; 818 break; 819 820 case TPM_TIS_STATE_IDLE: 821 tpm_tis_sts_set(&s->loc[locty], TPM_TIS_STS_COMMAND_READY); 822 s->loc[locty].state = TPM_TIS_STATE_READY; 823 tpm_tis_raise_irq(s, locty, TPM_TIS_INT_COMMAND_READY); 824 break; 825 826 case TPM_TIS_STATE_EXECUTION: 827 case TPM_TIS_STATE_RECEPTION: 828 /* abort currently running command */ 829 DPRINTF("tpm_tis: %s: Initiating abort.\n", 830 __func__); 831 tpm_tis_prep_abort(s, locty, locty); 832 break; 833 834 case TPM_TIS_STATE_COMPLETION: 835 s->rw_offset = 0; 836 /* shortcut to ready state with C/R set */ 837 s->loc[locty].state = TPM_TIS_STATE_READY; 838 if (!(s->loc[locty].sts & TPM_TIS_STS_COMMAND_READY)) { 839 tpm_tis_sts_set(&s->loc[locty], 840 TPM_TIS_STS_COMMAND_READY); 841 tpm_tis_raise_irq(s, locty, TPM_TIS_INT_COMMAND_READY); 842 } 843 s->loc[locty].sts &= ~(TPM_TIS_STS_DATA_AVAILABLE); 844 break; 845 846 } 847 } else if (val == TPM_TIS_STS_TPM_GO) { 848 switch (s->loc[locty].state) { 849 case TPM_TIS_STATE_RECEPTION: 850 if ((s->loc[locty].sts & TPM_TIS_STS_EXPECT) == 0) { 851 tpm_tis_tpm_send(s, locty); 852 } 853 break; 854 default: 855 /* ignore */ 856 break; 857 } 858 } else if (val == TPM_TIS_STS_RESPONSE_RETRY) { 859 switch (s->loc[locty].state) { 860 case TPM_TIS_STATE_COMPLETION: 861 s->rw_offset = 0; 862 tpm_tis_sts_set(&s->loc[locty], 863 TPM_TIS_STS_VALID| 864 TPM_TIS_STS_DATA_AVAILABLE); 865 break; 866 default: 867 /* ignore */ 868 break; 869 } 870 } 871 break; 872 case TPM_TIS_REG_DATA_FIFO: 873 case TPM_TIS_REG_DATA_XFIFO ... TPM_TIS_REG_DATA_XFIFO_END: 874 /* data fifo */ 875 if (s->active_locty != locty) { 876 break; 877 } 878 879 if (s->loc[locty].state == TPM_TIS_STATE_IDLE || 880 s->loc[locty].state == TPM_TIS_STATE_EXECUTION || 881 s->loc[locty].state == TPM_TIS_STATE_COMPLETION) { 882 /* drop the byte */ 883 } else { 884 DPRINTF("tpm_tis: Data to send to TPM: %08x (size=%d)\n", 885 (int)val, size); 886 if (s->loc[locty].state == TPM_TIS_STATE_READY) { 887 s->loc[locty].state = TPM_TIS_STATE_RECEPTION; 888 tpm_tis_sts_set(&s->loc[locty], 889 TPM_TIS_STS_EXPECT | TPM_TIS_STS_VALID); 890 } 891 892 val >>= shift; 893 if (size > 4 - (addr & 0x3)) { 894 /* prevent access beyond FIFO */ 895 size = 4 - (addr & 0x3); 896 } 897 898 while ((s->loc[locty].sts & TPM_TIS_STS_EXPECT) && size > 0) { 899 if (s->rw_offset < s->be_buffer_size) { 900 s->buffer[s->rw_offset++] = 901 (uint8_t)val; 902 val >>= 8; 903 size--; 904 } else { 905 tpm_tis_sts_set(&s->loc[locty], TPM_TIS_STS_VALID); 906 } 907 } 908 909 /* check for complete packet */ 910 if (s->rw_offset > 5 && 911 (s->loc[locty].sts & TPM_TIS_STS_EXPECT)) { 912 /* we have a packet length - see if we have all of it */ 913 bool need_irq = !(s->loc[locty].sts & TPM_TIS_STS_VALID); 914 915 len = tpm_cmd_get_size(&s->buffer); 916 if (len > s->rw_offset) { 917 tpm_tis_sts_set(&s->loc[locty], 918 TPM_TIS_STS_EXPECT | TPM_TIS_STS_VALID); 919 } else { 920 /* packet complete */ 921 tpm_tis_sts_set(&s->loc[locty], TPM_TIS_STS_VALID); 922 } 923 if (need_irq) { 924 tpm_tis_raise_irq(s, locty, TPM_TIS_INT_STS_VALID); 925 } 926 } 927 } 928 break; 929 case TPM_TIS_REG_INTERFACE_ID: 930 if (val & TPM_TIS_IFACE_ID_INT_SEL_LOCK) { 931 for (l = 0; l < TPM_TIS_NUM_LOCALITIES; l++) { 932 s->loc[l].iface_id |= TPM_TIS_IFACE_ID_INT_SEL_LOCK; 933 } 934 } 935 break; 936 } 937 } 938 939 static const MemoryRegionOps tpm_tis_memory_ops = { 940 .read = tpm_tis_mmio_read, 941 .write = tpm_tis_mmio_write, 942 .endianness = DEVICE_LITTLE_ENDIAN, 943 .valid = { 944 .min_access_size = 1, 945 .max_access_size = 4, 946 }, 947 }; 948 949 /* 950 * Get the TPMVersion of the backend device being used 951 */ 952 static enum TPMVersion tpm_tis_get_tpm_version(TPMIf *ti) 953 { 954 TPMState *s = TPM(ti); 955 956 if (tpm_backend_had_startup_error(s->be_driver)) { 957 return TPM_VERSION_UNSPEC; 958 } 959 960 return tpm_backend_get_tpm_version(s->be_driver); 961 } 962 963 /* 964 * This function is called when the machine starts, resets or due to 965 * S3 resume. 966 */ 967 static void tpm_tis_reset(DeviceState *dev) 968 { 969 TPMState *s = TPM(dev); 970 int c; 971 972 s->be_tpm_version = tpm_backend_get_tpm_version(s->be_driver); 973 s->be_buffer_size = MIN(tpm_backend_get_buffer_size(s->be_driver), 974 TPM_TIS_BUFFER_MAX); 975 976 tpm_backend_reset(s->be_driver); 977 978 s->active_locty = TPM_TIS_NO_LOCALITY; 979 s->next_locty = TPM_TIS_NO_LOCALITY; 980 s->aborting_locty = TPM_TIS_NO_LOCALITY; 981 982 for (c = 0; c < TPM_TIS_NUM_LOCALITIES; c++) { 983 s->loc[c].access = TPM_TIS_ACCESS_TPM_REG_VALID_STS; 984 switch (s->be_tpm_version) { 985 case TPM_VERSION_UNSPEC: 986 break; 987 case TPM_VERSION_1_2: 988 s->loc[c].sts = TPM_TIS_STS_TPM_FAMILY1_2; 989 s->loc[c].iface_id = TPM_TIS_IFACE_ID_SUPPORTED_FLAGS1_3; 990 break; 991 case TPM_VERSION_2_0: 992 s->loc[c].sts = TPM_TIS_STS_TPM_FAMILY2_0; 993 s->loc[c].iface_id = TPM_TIS_IFACE_ID_SUPPORTED_FLAGS2_0; 994 break; 995 } 996 s->loc[c].inte = TPM_TIS_INT_POLARITY_LOW_LEVEL; 997 s->loc[c].ints = 0; 998 s->loc[c].state = TPM_TIS_STATE_IDLE; 999 1000 s->rw_offset = 0; 1001 } 1002 1003 tpm_backend_startup_tpm(s->be_driver, s->be_buffer_size); 1004 } 1005 1006 static const VMStateDescription vmstate_tpm_tis = { 1007 .name = "tpm", 1008 .unmigratable = 1, 1009 }; 1010 1011 static Property tpm_tis_properties[] = { 1012 DEFINE_PROP_UINT32("irq", TPMState, irq_num, TPM_TIS_IRQ), 1013 DEFINE_PROP_TPMBE("tpmdev", TPMState, be_driver), 1014 DEFINE_PROP_END_OF_LIST(), 1015 }; 1016 1017 static void tpm_tis_realizefn(DeviceState *dev, Error **errp) 1018 { 1019 TPMState *s = TPM(dev); 1020 1021 if (!tpm_find()) { 1022 error_setg(errp, "at most one TPM device is permitted"); 1023 return; 1024 } 1025 1026 if (!s->be_driver) { 1027 error_setg(errp, "'tpmdev' property is required"); 1028 return; 1029 } 1030 if (s->irq_num > 15) { 1031 error_setg(errp, "IRQ %d is outside valid range of 0 to 15", 1032 s->irq_num); 1033 return; 1034 } 1035 1036 isa_init_irq(&s->busdev, &s->irq, s->irq_num); 1037 1038 memory_region_add_subregion(isa_address_space(ISA_DEVICE(dev)), 1039 TPM_TIS_ADDR_BASE, &s->mmio); 1040 } 1041 1042 static void tpm_tis_initfn(Object *obj) 1043 { 1044 TPMState *s = TPM(obj); 1045 1046 memory_region_init_io(&s->mmio, OBJECT(s), &tpm_tis_memory_ops, 1047 s, "tpm-tis-mmio", 1048 TPM_TIS_NUM_LOCALITIES << TPM_TIS_LOCALITY_SHIFT); 1049 } 1050 1051 static void tpm_tis_class_init(ObjectClass *klass, void *data) 1052 { 1053 DeviceClass *dc = DEVICE_CLASS(klass); 1054 TPMIfClass *tc = TPM_IF_CLASS(klass); 1055 1056 dc->realize = tpm_tis_realizefn; 1057 dc->props = tpm_tis_properties; 1058 dc->reset = tpm_tis_reset; 1059 dc->vmsd = &vmstate_tpm_tis; 1060 tc->model = TPM_MODEL_TPM_TIS; 1061 tc->get_version = tpm_tis_get_tpm_version; 1062 tc->request_completed = tpm_tis_request_completed; 1063 } 1064 1065 static const TypeInfo tpm_tis_info = { 1066 .name = TYPE_TPM_TIS, 1067 .parent = TYPE_ISA_DEVICE, 1068 .instance_size = sizeof(TPMState), 1069 .instance_init = tpm_tis_initfn, 1070 .class_init = tpm_tis_class_init, 1071 .interfaces = (InterfaceInfo[]) { 1072 { TYPE_TPM_IF }, 1073 { } 1074 } 1075 }; 1076 1077 static void tpm_tis_register(void) 1078 { 1079 type_register_static(&tpm_tis_info); 1080 } 1081 1082 type_init(tpm_tis_register) 1083