1 /* 2 * tpm_crb.c - QEMU's TPM CRB interface emulator 3 * 4 * Copyright (c) 2018 Red Hat, Inc. 5 * 6 * Authors: 7 * Marc-André Lureau <marcandre.lureau@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 * 12 * tpm_crb is a device for TPM 2.0 Command Response Buffer (CRB) Interface 13 * as defined in TCG PC Client Platform TPM Profile (PTP) Specification 14 * Family “2.0” Level 00 Revision 01.03 v22 15 */ 16 17 #include "qemu/osdep.h" 18 19 #include "qemu-common.h" 20 #include "qapi/error.h" 21 #include "exec/address-spaces.h" 22 23 #include "hw/qdev-core.h" 24 #include "hw/qdev-properties.h" 25 #include "hw/pci/pci_ids.h" 26 #include "hw/acpi/tpm.h" 27 #include "migration/vmstate.h" 28 #include "sysemu/tpm_backend.h" 29 #include "sysemu/reset.h" 30 #include "tpm_int.h" 31 #include "tpm_util.h" 32 #include "trace.h" 33 34 typedef struct CRBState { 35 DeviceState parent_obj; 36 37 TPMBackend *tpmbe; 38 TPMBackendCmd cmd; 39 uint32_t regs[TPM_CRB_R_MAX]; 40 MemoryRegion mmio; 41 MemoryRegion cmdmem; 42 43 size_t be_buffer_size; 44 } CRBState; 45 46 #define CRB(obj) OBJECT_CHECK(CRBState, (obj), TYPE_TPM_CRB) 47 48 #define CRB_INTF_TYPE_CRB_ACTIVE 0b1 49 #define CRB_INTF_VERSION_CRB 0b1 50 #define CRB_INTF_CAP_LOCALITY_0_ONLY 0b0 51 #define CRB_INTF_CAP_IDLE_FAST 0b0 52 #define CRB_INTF_CAP_XFER_SIZE_64 0b11 53 #define CRB_INTF_CAP_FIFO_NOT_SUPPORTED 0b0 54 #define CRB_INTF_CAP_CRB_SUPPORTED 0b1 55 #define CRB_INTF_IF_SELECTOR_CRB 0b1 56 57 #define CRB_CTRL_CMD_SIZE (TPM_CRB_ADDR_SIZE - A_CRB_DATA_BUFFER) 58 59 enum crb_loc_ctrl { 60 CRB_LOC_CTRL_REQUEST_ACCESS = BIT(0), 61 CRB_LOC_CTRL_RELINQUISH = BIT(1), 62 CRB_LOC_CTRL_SEIZE = BIT(2), 63 CRB_LOC_CTRL_RESET_ESTABLISHMENT_BIT = BIT(3), 64 }; 65 66 enum crb_ctrl_req { 67 CRB_CTRL_REQ_CMD_READY = BIT(0), 68 CRB_CTRL_REQ_GO_IDLE = BIT(1), 69 }; 70 71 enum crb_start { 72 CRB_START_INVOKE = BIT(0), 73 }; 74 75 enum crb_cancel { 76 CRB_CANCEL_INVOKE = BIT(0), 77 }; 78 79 static uint64_t tpm_crb_mmio_read(void *opaque, hwaddr addr, 80 unsigned size) 81 { 82 CRBState *s = CRB(opaque); 83 void *regs = (void *)&s->regs + (addr & ~3); 84 unsigned offset = addr & 3; 85 uint32_t val = *(uint32_t *)regs >> (8 * offset); 86 87 switch (addr) { 88 case A_CRB_LOC_STATE: 89 val |= !tpm_backend_get_tpm_established_flag(s->tpmbe); 90 break; 91 } 92 93 trace_tpm_crb_mmio_read(addr, size, val); 94 95 return val; 96 } 97 98 static void tpm_crb_mmio_write(void *opaque, hwaddr addr, 99 uint64_t val, unsigned size) 100 { 101 CRBState *s = CRB(opaque); 102 103 trace_tpm_crb_mmio_write(addr, size, val); 104 105 switch (addr) { 106 case A_CRB_CTRL_REQ: 107 switch (val) { 108 case CRB_CTRL_REQ_CMD_READY: 109 ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, 110 tpmIdle, 0); 111 break; 112 case CRB_CTRL_REQ_GO_IDLE: 113 ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, 114 tpmIdle, 1); 115 break; 116 } 117 break; 118 case A_CRB_CTRL_CANCEL: 119 if (val == CRB_CANCEL_INVOKE && 120 s->regs[R_CRB_CTRL_START] & CRB_START_INVOKE) { 121 tpm_backend_cancel_cmd(s->tpmbe); 122 } 123 break; 124 case A_CRB_CTRL_START: 125 if (val == CRB_START_INVOKE && 126 !(s->regs[R_CRB_CTRL_START] & CRB_START_INVOKE)) { 127 void *mem = memory_region_get_ram_ptr(&s->cmdmem); 128 129 s->regs[R_CRB_CTRL_START] |= CRB_START_INVOKE; 130 s->cmd = (TPMBackendCmd) { 131 .in = mem, 132 .in_len = MIN(tpm_cmd_get_size(mem), s->be_buffer_size), 133 .out = mem, 134 .out_len = s->be_buffer_size, 135 }; 136 137 tpm_backend_deliver_request(s->tpmbe, &s->cmd); 138 } 139 break; 140 case A_CRB_LOC_CTRL: 141 switch (val) { 142 case CRB_LOC_CTRL_RESET_ESTABLISHMENT_BIT: 143 /* not loc 3 or 4 */ 144 break; 145 case CRB_LOC_CTRL_RELINQUISH: 146 ARRAY_FIELD_DP32(s->regs, CRB_LOC_STATE, 147 locAssigned, 0); 148 break; 149 case CRB_LOC_CTRL_REQUEST_ACCESS: 150 ARRAY_FIELD_DP32(s->regs, CRB_LOC_STS, 151 Granted, 1); 152 ARRAY_FIELD_DP32(s->regs, CRB_LOC_STS, 153 beenSeized, 0); 154 ARRAY_FIELD_DP32(s->regs, CRB_LOC_STATE, 155 locAssigned, 1); 156 break; 157 } 158 break; 159 } 160 } 161 162 static const MemoryRegionOps tpm_crb_memory_ops = { 163 .read = tpm_crb_mmio_read, 164 .write = tpm_crb_mmio_write, 165 .endianness = DEVICE_LITTLE_ENDIAN, 166 .valid = { 167 .min_access_size = 1, 168 .max_access_size = 4, 169 }, 170 }; 171 172 static void tpm_crb_request_completed(TPMIf *ti, int ret) 173 { 174 CRBState *s = CRB(ti); 175 176 s->regs[R_CRB_CTRL_START] &= ~CRB_START_INVOKE; 177 if (ret != 0) { 178 ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, 179 tpmSts, 1); /* fatal error */ 180 } 181 } 182 183 static enum TPMVersion tpm_crb_get_version(TPMIf *ti) 184 { 185 CRBState *s = CRB(ti); 186 187 return tpm_backend_get_tpm_version(s->tpmbe); 188 } 189 190 static int tpm_crb_pre_save(void *opaque) 191 { 192 CRBState *s = opaque; 193 194 tpm_backend_finish_sync(s->tpmbe); 195 196 return 0; 197 } 198 199 static const VMStateDescription vmstate_tpm_crb = { 200 .name = "tpm-crb", 201 .pre_save = tpm_crb_pre_save, 202 .fields = (VMStateField[]) { 203 VMSTATE_UINT32_ARRAY(regs, CRBState, TPM_CRB_R_MAX), 204 VMSTATE_END_OF_LIST(), 205 } 206 }; 207 208 static Property tpm_crb_properties[] = { 209 DEFINE_PROP_TPMBE("tpmdev", CRBState, tpmbe), 210 DEFINE_PROP_END_OF_LIST(), 211 }; 212 213 static void tpm_crb_reset(void *dev) 214 { 215 CRBState *s = CRB(dev); 216 217 tpm_backend_reset(s->tpmbe); 218 219 memset(s->regs, 0, sizeof(s->regs)); 220 221 ARRAY_FIELD_DP32(s->regs, CRB_LOC_STATE, 222 tpmRegValidSts, 1); 223 ARRAY_FIELD_DP32(s->regs, CRB_CTRL_STS, 224 tpmIdle, 1); 225 ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, 226 InterfaceType, CRB_INTF_TYPE_CRB_ACTIVE); 227 ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, 228 InterfaceVersion, CRB_INTF_VERSION_CRB); 229 ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, 230 CapLocality, CRB_INTF_CAP_LOCALITY_0_ONLY); 231 ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, 232 CapCRBIdleBypass, CRB_INTF_CAP_IDLE_FAST); 233 ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, 234 CapDataXferSizeSupport, CRB_INTF_CAP_XFER_SIZE_64); 235 ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, 236 CapFIFO, CRB_INTF_CAP_FIFO_NOT_SUPPORTED); 237 ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, 238 CapCRB, CRB_INTF_CAP_CRB_SUPPORTED); 239 ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, 240 InterfaceSelector, CRB_INTF_IF_SELECTOR_CRB); 241 ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID, 242 RID, 0b0000); 243 ARRAY_FIELD_DP32(s->regs, CRB_INTF_ID2, 244 VID, PCI_VENDOR_ID_IBM); 245 246 s->regs[R_CRB_CTRL_CMD_SIZE] = CRB_CTRL_CMD_SIZE; 247 s->regs[R_CRB_CTRL_CMD_LADDR] = TPM_CRB_ADDR_BASE + A_CRB_DATA_BUFFER; 248 s->regs[R_CRB_CTRL_RSP_SIZE] = CRB_CTRL_CMD_SIZE; 249 s->regs[R_CRB_CTRL_RSP_ADDR] = TPM_CRB_ADDR_BASE + A_CRB_DATA_BUFFER; 250 251 s->be_buffer_size = MIN(tpm_backend_get_buffer_size(s->tpmbe), 252 CRB_CTRL_CMD_SIZE); 253 254 tpm_backend_startup_tpm(s->tpmbe, s->be_buffer_size); 255 } 256 257 static void tpm_crb_realize(DeviceState *dev, Error **errp) 258 { 259 CRBState *s = CRB(dev); 260 261 if (!tpm_find()) { 262 error_setg(errp, "at most one TPM device is permitted"); 263 return; 264 } 265 if (!s->tpmbe) { 266 error_setg(errp, "'tpmdev' property is required"); 267 return; 268 } 269 270 memory_region_init_io(&s->mmio, OBJECT(s), &tpm_crb_memory_ops, s, 271 "tpm-crb-mmio", sizeof(s->regs)); 272 memory_region_init_ram(&s->cmdmem, OBJECT(s), 273 "tpm-crb-cmd", CRB_CTRL_CMD_SIZE, errp); 274 275 memory_region_add_subregion(get_system_memory(), 276 TPM_CRB_ADDR_BASE, &s->mmio); 277 memory_region_add_subregion(get_system_memory(), 278 TPM_CRB_ADDR_BASE + sizeof(s->regs), &s->cmdmem); 279 280 qemu_register_reset(tpm_crb_reset, dev); 281 } 282 283 static void tpm_crb_class_init(ObjectClass *klass, void *data) 284 { 285 DeviceClass *dc = DEVICE_CLASS(klass); 286 TPMIfClass *tc = TPM_IF_CLASS(klass); 287 288 dc->realize = tpm_crb_realize; 289 dc->props = tpm_crb_properties; 290 dc->vmsd = &vmstate_tpm_crb; 291 dc->user_creatable = true; 292 tc->model = TPM_MODEL_TPM_CRB; 293 tc->get_version = tpm_crb_get_version; 294 tc->request_completed = tpm_crb_request_completed; 295 296 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 297 } 298 299 static const TypeInfo tpm_crb_info = { 300 .name = TYPE_TPM_CRB, 301 /* could be TYPE_SYS_BUS_DEVICE (or LPC etc) */ 302 .parent = TYPE_DEVICE, 303 .instance_size = sizeof(CRBState), 304 .class_init = tpm_crb_class_init, 305 .interfaces = (InterfaceInfo[]) { 306 { TYPE_TPM_IF }, 307 { } 308 } 309 }; 310 311 static void tpm_crb_register(void) 312 { 313 type_register_static(&tpm_crb_info); 314 } 315 316 type_init(tpm_crb_register) 317