xref: /qemu/hw/timer/xilinx_timer.c (revision 0b8fa32f551e863bb548a11394239239270dd3dc)
1388f60b1SEdgar E. Iglesias /*
2388f60b1SEdgar E. Iglesias  * QEMU model of the Xilinx timer block.
3388f60b1SEdgar E. Iglesias  *
4388f60b1SEdgar E. Iglesias  * Copyright (c) 2009 Edgar E. Iglesias.
5388f60b1SEdgar E. Iglesias  *
6388f60b1SEdgar E. Iglesias  * Permission is hereby granted, free of charge, to any person obtaining a copy
7388f60b1SEdgar E. Iglesias  * of this software and associated documentation files (the "Software"), to deal
8388f60b1SEdgar E. Iglesias  * in the Software without restriction, including without limitation the rights
9388f60b1SEdgar E. Iglesias  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10388f60b1SEdgar E. Iglesias  * copies of the Software, and to permit persons to whom the Software is
11388f60b1SEdgar E. Iglesias  * furnished to do so, subject to the following conditions:
12388f60b1SEdgar E. Iglesias  *
13388f60b1SEdgar E. Iglesias  * The above copyright notice and this permission notice shall be included in
14388f60b1SEdgar E. Iglesias  * all copies or substantial portions of the Software.
15388f60b1SEdgar E. Iglesias  *
16388f60b1SEdgar E. Iglesias  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17388f60b1SEdgar E. Iglesias  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18388f60b1SEdgar E. Iglesias  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19388f60b1SEdgar E. Iglesias  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20388f60b1SEdgar E. Iglesias  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21388f60b1SEdgar E. Iglesias  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22388f60b1SEdgar E. Iglesias  * THE SOFTWARE.
23388f60b1SEdgar E. Iglesias  */
24388f60b1SEdgar E. Iglesias 
25282bc81eSPeter Maydell #include "qemu/osdep.h"
2683c9f4caSPaolo Bonzini #include "hw/sysbus.h"
2783c9f4caSPaolo Bonzini #include "hw/ptimer.h"
281de7afc9SPaolo Bonzini #include "qemu/log.h"
296a1751b7SAlex Bligh #include "qemu/main-loop.h"
30*0b8fa32fSMarkus Armbruster #include "qemu/module.h"
31388f60b1SEdgar E. Iglesias 
32388f60b1SEdgar E. Iglesias #define D(x)
33388f60b1SEdgar E. Iglesias 
34388f60b1SEdgar E. Iglesias #define R_TCSR     0
35388f60b1SEdgar E. Iglesias #define R_TLR      1
36388f60b1SEdgar E. Iglesias #define R_TCR      2
37388f60b1SEdgar E. Iglesias #define R_MAX      4
38388f60b1SEdgar E. Iglesias 
39388f60b1SEdgar E. Iglesias #define TCSR_MDT        (1<<0)
40388f60b1SEdgar E. Iglesias #define TCSR_UDT        (1<<1)
41388f60b1SEdgar E. Iglesias #define TCSR_GENT       (1<<2)
42388f60b1SEdgar E. Iglesias #define TCSR_CAPT       (1<<3)
43388f60b1SEdgar E. Iglesias #define TCSR_ARHT       (1<<4)
44388f60b1SEdgar E. Iglesias #define TCSR_LOAD       (1<<5)
45388f60b1SEdgar E. Iglesias #define TCSR_ENIT       (1<<6)
46388f60b1SEdgar E. Iglesias #define TCSR_ENT        (1<<7)
47388f60b1SEdgar E. Iglesias #define TCSR_TINT       (1<<8)
48388f60b1SEdgar E. Iglesias #define TCSR_PWMA       (1<<9)
49388f60b1SEdgar E. Iglesias #define TCSR_ENALL      (1<<10)
50388f60b1SEdgar E. Iglesias 
51388f60b1SEdgar E. Iglesias struct xlx_timer
52388f60b1SEdgar E. Iglesias {
53388f60b1SEdgar E. Iglesias     QEMUBH *bh;
54388f60b1SEdgar E. Iglesias     ptimer_state *ptimer;
55388f60b1SEdgar E. Iglesias     void *parent;
56388f60b1SEdgar E. Iglesias     int nr; /* for debug.  */
57388f60b1SEdgar E. Iglesias 
58388f60b1SEdgar E. Iglesias     unsigned long timer_div;
59388f60b1SEdgar E. Iglesias 
60388f60b1SEdgar E. Iglesias     uint32_t regs[R_MAX];
61388f60b1SEdgar E. Iglesias };
62388f60b1SEdgar E. Iglesias 
63760d1d00SAndreas Färber #define TYPE_XILINX_TIMER "xlnx.xps-timer"
64760d1d00SAndreas Färber #define XILINX_TIMER(obj) \
65760d1d00SAndreas Färber     OBJECT_CHECK(struct timerblock, (obj), TYPE_XILINX_TIMER)
66760d1d00SAndreas Färber 
67388f60b1SEdgar E. Iglesias struct timerblock
68388f60b1SEdgar E. Iglesias {
69760d1d00SAndreas Färber     SysBusDevice parent_obj;
70760d1d00SAndreas Färber 
71010f3f5fSEdgar E. Iglesias     MemoryRegion mmio;
72388f60b1SEdgar E. Iglesias     qemu_irq irq;
73abe098e4SPeter A. G. Crosthwaite     uint8_t one_timer_only;
74ee6847d1SGerd Hoffmann     uint32_t freq_hz;
75388f60b1SEdgar E. Iglesias     struct xlx_timer *timers;
76388f60b1SEdgar E. Iglesias };
77388f60b1SEdgar E. Iglesias 
78abe098e4SPeter A. G. Crosthwaite static inline unsigned int num_timers(struct timerblock *t)
79abe098e4SPeter A. G. Crosthwaite {
80abe098e4SPeter A. G. Crosthwaite     return 2 - t->one_timer_only;
81abe098e4SPeter A. G. Crosthwaite }
82abe098e4SPeter A. G. Crosthwaite 
83a8170e5eSAvi Kivity static inline unsigned int timer_from_addr(hwaddr addr)
84388f60b1SEdgar E. Iglesias {
85388f60b1SEdgar E. Iglesias     /* Timers get a 4x32bit control reg area each.  */
86388f60b1SEdgar E. Iglesias     return addr >> 2;
87388f60b1SEdgar E. Iglesias }
88388f60b1SEdgar E. Iglesias 
89388f60b1SEdgar E. Iglesias static void timer_update_irq(struct timerblock *t)
90388f60b1SEdgar E. Iglesias {
91388f60b1SEdgar E. Iglesias     unsigned int i, irq = 0;
92388f60b1SEdgar E. Iglesias     uint32_t csr;
93388f60b1SEdgar E. Iglesias 
94abe098e4SPeter A. G. Crosthwaite     for (i = 0; i < num_timers(t); i++) {
95388f60b1SEdgar E. Iglesias         csr = t->timers[i].regs[R_TCSR];
96388f60b1SEdgar E. Iglesias         irq |= (csr & TCSR_TINT) && (csr & TCSR_ENIT);
97388f60b1SEdgar E. Iglesias     }
98388f60b1SEdgar E. Iglesias 
99388f60b1SEdgar E. Iglesias     /* All timers within the same slave share a single IRQ line.  */
100388f60b1SEdgar E. Iglesias     qemu_set_irq(t->irq, !!irq);
101388f60b1SEdgar E. Iglesias }
102388f60b1SEdgar E. Iglesias 
103010f3f5fSEdgar E. Iglesias static uint64_t
104a8170e5eSAvi Kivity timer_read(void *opaque, hwaddr addr, unsigned int size)
105388f60b1SEdgar E. Iglesias {
106388f60b1SEdgar E. Iglesias     struct timerblock *t = opaque;
107388f60b1SEdgar E. Iglesias     struct xlx_timer *xt;
108388f60b1SEdgar E. Iglesias     uint32_t r = 0;
109388f60b1SEdgar E. Iglesias     unsigned int timer;
110388f60b1SEdgar E. Iglesias 
111388f60b1SEdgar E. Iglesias     addr >>= 2;
112388f60b1SEdgar E. Iglesias     timer = timer_from_addr(addr);
113388f60b1SEdgar E. Iglesias     xt = &t->timers[timer];
114388f60b1SEdgar E. Iglesias     /* Further decoding to address a specific timers reg.  */
115388f60b1SEdgar E. Iglesias     addr &= 0x3;
116388f60b1SEdgar E. Iglesias     switch (addr)
117388f60b1SEdgar E. Iglesias     {
118388f60b1SEdgar E. Iglesias         case R_TCR:
119388f60b1SEdgar E. Iglesias                 r = ptimer_get_count(xt->ptimer);
120388f60b1SEdgar E. Iglesias                 if (!(xt->regs[R_TCSR] & TCSR_UDT))
121388f60b1SEdgar E. Iglesias                     r = ~r;
122388f60b1SEdgar E. Iglesias                 D(qemu_log("xlx_timer t=%d read counter=%x udt=%d\n",
123388f60b1SEdgar E. Iglesias                          timer, r, xt->regs[R_TCSR] & TCSR_UDT));
124388f60b1SEdgar E. Iglesias             break;
125388f60b1SEdgar E. Iglesias         default:
126388f60b1SEdgar E. Iglesias             if (addr < ARRAY_SIZE(xt->regs))
127388f60b1SEdgar E. Iglesias                 r = xt->regs[addr];
128388f60b1SEdgar E. Iglesias             break;
129388f60b1SEdgar E. Iglesias 
130388f60b1SEdgar E. Iglesias     }
131e03377aeSPeter A. G. Crosthwaite     D(fprintf(stderr, "%s timer=%d %x=%x\n", __func__, timer, addr * 4, r));
132388f60b1SEdgar E. Iglesias     return r;
133388f60b1SEdgar E. Iglesias }
134388f60b1SEdgar E. Iglesias 
135388f60b1SEdgar E. Iglesias static void timer_enable(struct xlx_timer *xt)
136388f60b1SEdgar E. Iglesias {
137388f60b1SEdgar E. Iglesias     uint64_t count;
138388f60b1SEdgar E. Iglesias 
139e03377aeSPeter A. G. Crosthwaite     D(fprintf(stderr, "%s timer=%d down=%d\n", __func__,
140388f60b1SEdgar E. Iglesias               xt->nr, xt->regs[R_TCSR] & TCSR_UDT));
141388f60b1SEdgar E. Iglesias 
142388f60b1SEdgar E. Iglesias     ptimer_stop(xt->ptimer);
143388f60b1SEdgar E. Iglesias 
144388f60b1SEdgar E. Iglesias     if (xt->regs[R_TCSR] & TCSR_UDT)
145388f60b1SEdgar E. Iglesias         count = xt->regs[R_TLR];
146388f60b1SEdgar E. Iglesias     else
147388f60b1SEdgar E. Iglesias         count = ~0 - xt->regs[R_TLR];
1487798a882SPeter A. G. Crosthwaite     ptimer_set_limit(xt->ptimer, count, 1);
149388f60b1SEdgar E. Iglesias     ptimer_run(xt->ptimer, 1);
150388f60b1SEdgar E. Iglesias }
151388f60b1SEdgar E. Iglesias 
152388f60b1SEdgar E. Iglesias static void
153a8170e5eSAvi Kivity timer_write(void *opaque, hwaddr addr,
154010f3f5fSEdgar E. Iglesias             uint64_t val64, unsigned int size)
155388f60b1SEdgar E. Iglesias {
156388f60b1SEdgar E. Iglesias     struct timerblock *t = opaque;
157388f60b1SEdgar E. Iglesias     struct xlx_timer *xt;
158388f60b1SEdgar E. Iglesias     unsigned int timer;
159010f3f5fSEdgar E. Iglesias     uint32_t value = val64;
160388f60b1SEdgar E. Iglesias 
161388f60b1SEdgar E. Iglesias     addr >>= 2;
162388f60b1SEdgar E. Iglesias     timer = timer_from_addr(addr);
163388f60b1SEdgar E. Iglesias     xt = &t->timers[timer];
164e03377aeSPeter A. G. Crosthwaite     D(fprintf(stderr, "%s addr=%x val=%x (timer=%d off=%d)\n",
165388f60b1SEdgar E. Iglesias              __func__, addr * 4, value, timer, addr & 3));
166388f60b1SEdgar E. Iglesias     /* Further decoding to address a specific timers reg.  */
167388f60b1SEdgar E. Iglesias     addr &= 3;
168388f60b1SEdgar E. Iglesias     switch (addr)
169388f60b1SEdgar E. Iglesias     {
170388f60b1SEdgar E. Iglesias         case R_TCSR:
171388f60b1SEdgar E. Iglesias             if (value & TCSR_TINT)
172388f60b1SEdgar E. Iglesias                 value &= ~TCSR_TINT;
173388f60b1SEdgar E. Iglesias 
1747dfba6dfSGuenter Roeck             xt->regs[addr] = value & 0x7ff;
175388f60b1SEdgar E. Iglesias             if (value & TCSR_ENT)
176388f60b1SEdgar E. Iglesias                 timer_enable(xt);
177388f60b1SEdgar E. Iglesias             break;
178388f60b1SEdgar E. Iglesias 
179388f60b1SEdgar E. Iglesias         default:
180388f60b1SEdgar E. Iglesias             if (addr < ARRAY_SIZE(xt->regs))
181388f60b1SEdgar E. Iglesias                 xt->regs[addr] = value;
182388f60b1SEdgar E. Iglesias             break;
183388f60b1SEdgar E. Iglesias     }
184388f60b1SEdgar E. Iglesias     timer_update_irq(t);
185388f60b1SEdgar E. Iglesias }
186388f60b1SEdgar E. Iglesias 
187010f3f5fSEdgar E. Iglesias static const MemoryRegionOps timer_ops = {
188010f3f5fSEdgar E. Iglesias     .read = timer_read,
189010f3f5fSEdgar E. Iglesias     .write = timer_write,
190010f3f5fSEdgar E. Iglesias     .endianness = DEVICE_NATIVE_ENDIAN,
191010f3f5fSEdgar E. Iglesias     .valid = {
192010f3f5fSEdgar E. Iglesias         .min_access_size = 4,
193010f3f5fSEdgar E. Iglesias         .max_access_size = 4
194010f3f5fSEdgar E. Iglesias     }
195388f60b1SEdgar E. Iglesias };
196388f60b1SEdgar E. Iglesias 
197388f60b1SEdgar E. Iglesias static void timer_hit(void *opaque)
198388f60b1SEdgar E. Iglesias {
199388f60b1SEdgar E. Iglesias     struct xlx_timer *xt = opaque;
200388f60b1SEdgar E. Iglesias     struct timerblock *t = xt->parent;
2018354cd72SChris Wulff     D(fprintf(stderr, "%s %d\n", __func__, xt->nr));
202388f60b1SEdgar E. Iglesias     xt->regs[R_TCSR] |= TCSR_TINT;
203388f60b1SEdgar E. Iglesias 
204388f60b1SEdgar E. Iglesias     if (xt->regs[R_TCSR] & TCSR_ARHT)
205388f60b1SEdgar E. Iglesias         timer_enable(xt);
206388f60b1SEdgar E. Iglesias     timer_update_irq(t);
207388f60b1SEdgar E. Iglesias }
208388f60b1SEdgar E. Iglesias 
20904bb4d86SPeter Crosthwaite static void xilinx_timer_realize(DeviceState *dev, Error **errp)
210388f60b1SEdgar E. Iglesias {
211760d1d00SAndreas Färber     struct timerblock *t = XILINX_TIMER(dev);
212388f60b1SEdgar E. Iglesias     unsigned int i;
213388f60b1SEdgar E. Iglesias 
214388f60b1SEdgar E. Iglesias     /* Init all the ptimers.  */
215abe098e4SPeter A. G. Crosthwaite     t->timers = g_malloc0(sizeof t->timers[0] * num_timers(t));
216abe098e4SPeter A. G. Crosthwaite     for (i = 0; i < num_timers(t); i++) {
217388f60b1SEdgar E. Iglesias         struct xlx_timer *xt = &t->timers[i];
218388f60b1SEdgar E. Iglesias 
219388f60b1SEdgar E. Iglesias         xt->parent = t;
220388f60b1SEdgar E. Iglesias         xt->nr = i;
221388f60b1SEdgar E. Iglesias         xt->bh = qemu_bh_new(timer_hit, xt);
222e7ea81c3SDmitry Osipenko         xt->ptimer = ptimer_init(xt->bh, PTIMER_POLICY_DEFAULT);
223ee6847d1SGerd Hoffmann         ptimer_set_freq(xt->ptimer, t->freq_hz);
224388f60b1SEdgar E. Iglesias     }
225388f60b1SEdgar E. Iglesias 
226853dca12SPaolo Bonzini     memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, "xlnx.xps-timer",
227abe098e4SPeter A. G. Crosthwaite                           R_MAX * 4 * num_timers(t));
22804bb4d86SPeter Crosthwaite     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &t->mmio);
22904bb4d86SPeter Crosthwaite }
23004bb4d86SPeter Crosthwaite 
23104bb4d86SPeter Crosthwaite static void xilinx_timer_init(Object *obj)
23204bb4d86SPeter Crosthwaite {
23304bb4d86SPeter Crosthwaite     struct timerblock *t = XILINX_TIMER(obj);
23404bb4d86SPeter Crosthwaite 
23504bb4d86SPeter Crosthwaite     /* All timers share a single irq line.  */
23604bb4d86SPeter Crosthwaite     sysbus_init_irq(SYS_BUS_DEVICE(obj), &t->irq);
237388f60b1SEdgar E. Iglesias }
238388f60b1SEdgar E. Iglesias 
239999e12bbSAnthony Liguori static Property xilinx_timer_properties[] = {
240919f89f4SPeter A. G. Crosthwaite     DEFINE_PROP_UINT32("clock-frequency", struct timerblock, freq_hz,
241919f89f4SPeter A. G. Crosthwaite                                                                 62 * 1000000),
242abe098e4SPeter A. G. Crosthwaite     DEFINE_PROP_UINT8("one-timer-only", struct timerblock, one_timer_only, 0),
243ea2b7271SGerd Hoffmann     DEFINE_PROP_END_OF_LIST(),
244999e12bbSAnthony Liguori };
245999e12bbSAnthony Liguori 
246999e12bbSAnthony Liguori static void xilinx_timer_class_init(ObjectClass *klass, void *data)
247999e12bbSAnthony Liguori {
24839bffca2SAnthony Liguori     DeviceClass *dc = DEVICE_CLASS(klass);
249999e12bbSAnthony Liguori 
25004bb4d86SPeter Crosthwaite     dc->realize = xilinx_timer_realize;
25139bffca2SAnthony Liguori     dc->props = xilinx_timer_properties;
252ee6847d1SGerd Hoffmann }
253999e12bbSAnthony Liguori 
2548c43a6f0SAndreas Färber static const TypeInfo xilinx_timer_info = {
255760d1d00SAndreas Färber     .name          = TYPE_XILINX_TIMER,
25639bffca2SAnthony Liguori     .parent        = TYPE_SYS_BUS_DEVICE,
25739bffca2SAnthony Liguori     .instance_size = sizeof(struct timerblock),
25804bb4d86SPeter Crosthwaite     .instance_init = xilinx_timer_init,
259999e12bbSAnthony Liguori     .class_init    = xilinx_timer_class_init,
260ee6847d1SGerd Hoffmann };
261ee6847d1SGerd Hoffmann 
26283f7d43aSAndreas Färber static void xilinx_timer_register_types(void)
263388f60b1SEdgar E. Iglesias {
26439bffca2SAnthony Liguori     type_register_static(&xilinx_timer_info);
265388f60b1SEdgar E. Iglesias }
266388f60b1SEdgar E. Iglesias 
26783f7d43aSAndreas Färber type_init(xilinx_timer_register_types)
268