1 /* 2 * SuperH Timer modules. 3 * 4 * Copyright (c) 2007 Magnus Damm 5 * Based on arm_timer.c by Paul Brook 6 * Copyright (c) 2005-2006 CodeSourcery. 7 * 8 * This code is licensed under the GPL. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "exec/memory.h" 13 #include "hw/hw.h" 14 #include "hw/irq.h" 15 #include "hw/sh4/sh.h" 16 #include "qemu/timer.h" 17 #include "hw/timer/tmu012.h" 18 #include "hw/ptimer.h" 19 20 //#define DEBUG_TIMER 21 22 #define TIMER_TCR_TPSC (7 << 0) 23 #define TIMER_TCR_CKEG (3 << 3) 24 #define TIMER_TCR_UNIE (1 << 5) 25 #define TIMER_TCR_ICPE (3 << 6) 26 #define TIMER_TCR_UNF (1 << 8) 27 #define TIMER_TCR_ICPF (1 << 9) 28 #define TIMER_TCR_RESERVED (0x3f << 10) 29 30 #define TIMER_FEAT_CAPT (1 << 0) 31 #define TIMER_FEAT_EXTCLK (1 << 1) 32 33 #define OFFSET_TCOR 0 34 #define OFFSET_TCNT 1 35 #define OFFSET_TCR 2 36 #define OFFSET_TCPR 3 37 38 typedef struct { 39 ptimer_state *timer; 40 uint32_t tcnt; 41 uint32_t tcor; 42 uint32_t tcr; 43 uint32_t tcpr; 44 int freq; 45 int int_level; 46 int old_level; 47 int feat; 48 int enabled; 49 qemu_irq irq; 50 } sh_timer_state; 51 52 /* Check all active timers, and schedule the next timer interrupt. */ 53 54 static void sh_timer_update(sh_timer_state *s) 55 { 56 int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE); 57 58 if (new_level != s->old_level) 59 qemu_set_irq (s->irq, new_level); 60 61 s->old_level = s->int_level; 62 s->int_level = new_level; 63 } 64 65 static uint32_t sh_timer_read(void *opaque, hwaddr offset) 66 { 67 sh_timer_state *s = (sh_timer_state *)opaque; 68 69 switch (offset >> 2) { 70 case OFFSET_TCOR: 71 return s->tcor; 72 case OFFSET_TCNT: 73 return ptimer_get_count(s->timer); 74 case OFFSET_TCR: 75 return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0); 76 case OFFSET_TCPR: 77 if (s->feat & TIMER_FEAT_CAPT) 78 return s->tcpr; 79 /* fall through */ 80 default: 81 hw_error("sh_timer_read: Bad offset %x\n", (int)offset); 82 return 0; 83 } 84 } 85 86 static void sh_timer_write(void *opaque, hwaddr offset, 87 uint32_t value) 88 { 89 sh_timer_state *s = (sh_timer_state *)opaque; 90 int freq; 91 92 switch (offset >> 2) { 93 case OFFSET_TCOR: 94 s->tcor = value; 95 ptimer_transaction_begin(s->timer); 96 ptimer_set_limit(s->timer, s->tcor, 0); 97 ptimer_transaction_commit(s->timer); 98 break; 99 case OFFSET_TCNT: 100 s->tcnt = value; 101 ptimer_transaction_begin(s->timer); 102 ptimer_set_count(s->timer, s->tcnt); 103 ptimer_transaction_commit(s->timer); 104 break; 105 case OFFSET_TCR: 106 ptimer_transaction_begin(s->timer); 107 if (s->enabled) { 108 /* Pause the timer if it is running. This may cause some 109 inaccuracy dure to rounding, but avoids a whole lot of other 110 messyness. */ 111 ptimer_stop(s->timer); 112 } 113 freq = s->freq; 114 /* ??? Need to recalculate expiry time after changing divisor. */ 115 switch (value & TIMER_TCR_TPSC) { 116 case 0: freq >>= 2; break; 117 case 1: freq >>= 4; break; 118 case 2: freq >>= 6; break; 119 case 3: freq >>= 8; break; 120 case 4: freq >>= 10; break; 121 case 6: 122 case 7: if (s->feat & TIMER_FEAT_EXTCLK) break; 123 default: hw_error("sh_timer_write: Reserved TPSC value\n"); break; 124 } 125 switch ((value & TIMER_TCR_CKEG) >> 3) { 126 case 0: break; 127 case 1: 128 case 2: 129 case 3: if (s->feat & TIMER_FEAT_EXTCLK) break; 130 default: hw_error("sh_timer_write: Reserved CKEG value\n"); break; 131 } 132 switch ((value & TIMER_TCR_ICPE) >> 6) { 133 case 0: break; 134 case 2: 135 case 3: if (s->feat & TIMER_FEAT_CAPT) break; 136 default: hw_error("sh_timer_write: Reserved ICPE value\n"); break; 137 } 138 if ((value & TIMER_TCR_UNF) == 0) 139 s->int_level = 0; 140 141 value &= ~TIMER_TCR_UNF; 142 143 if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT))) 144 hw_error("sh_timer_write: Reserved ICPF value\n"); 145 146 value &= ~TIMER_TCR_ICPF; /* capture not supported */ 147 148 if (value & TIMER_TCR_RESERVED) 149 hw_error("sh_timer_write: Reserved TCR bits set\n"); 150 s->tcr = value; 151 ptimer_set_limit(s->timer, s->tcor, 0); 152 ptimer_set_freq(s->timer, freq); 153 if (s->enabled) { 154 /* Restart the timer if still enabled. */ 155 ptimer_run(s->timer, 0); 156 } 157 ptimer_transaction_commit(s->timer); 158 break; 159 case OFFSET_TCPR: 160 if (s->feat & TIMER_FEAT_CAPT) { 161 s->tcpr = value; 162 break; 163 } 164 default: 165 hw_error("sh_timer_write: Bad offset %x\n", (int)offset); 166 } 167 sh_timer_update(s); 168 } 169 170 static void sh_timer_start_stop(void *opaque, int enable) 171 { 172 sh_timer_state *s = (sh_timer_state *)opaque; 173 174 #ifdef DEBUG_TIMER 175 printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled); 176 #endif 177 178 ptimer_transaction_begin(s->timer); 179 if (s->enabled && !enable) { 180 ptimer_stop(s->timer); 181 } 182 if (!s->enabled && enable) { 183 ptimer_run(s->timer, 0); 184 } 185 ptimer_transaction_commit(s->timer); 186 s->enabled = !!enable; 187 188 #ifdef DEBUG_TIMER 189 printf("sh_timer_start_stop done %d\n", s->enabled); 190 #endif 191 } 192 193 static void sh_timer_tick(void *opaque) 194 { 195 sh_timer_state *s = (sh_timer_state *)opaque; 196 s->int_level = s->enabled; 197 sh_timer_update(s); 198 } 199 200 static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq) 201 { 202 sh_timer_state *s; 203 204 s = (sh_timer_state *)g_malloc0(sizeof(sh_timer_state)); 205 s->freq = freq; 206 s->feat = feat; 207 s->tcor = 0xffffffff; 208 s->tcnt = 0xffffffff; 209 s->tcpr = 0xdeadbeef; 210 s->tcr = 0; 211 s->enabled = 0; 212 s->irq = irq; 213 214 s->timer = ptimer_init(sh_timer_tick, s, PTIMER_POLICY_DEFAULT); 215 216 sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor); 217 sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt); 218 sh_timer_write(s, OFFSET_TCPR >> 2, s->tcpr); 219 sh_timer_write(s, OFFSET_TCR >> 2, s->tcpr); 220 /* ??? Save/restore. */ 221 return s; 222 } 223 224 typedef struct { 225 MemoryRegion iomem; 226 MemoryRegion iomem_p4; 227 MemoryRegion iomem_a7; 228 void *timer[3]; 229 int level[3]; 230 uint32_t tocr; 231 uint32_t tstr; 232 int feat; 233 } tmu012_state; 234 235 static uint64_t tmu012_read(void *opaque, hwaddr offset, 236 unsigned size) 237 { 238 tmu012_state *s = (tmu012_state *)opaque; 239 240 #ifdef DEBUG_TIMER 241 printf("tmu012_read 0x%lx\n", (unsigned long) offset); 242 #endif 243 244 if (offset >= 0x20) { 245 if (!(s->feat & TMU012_FEAT_3CHAN)) 246 hw_error("tmu012_write: Bad channel offset %x\n", (int)offset); 247 return sh_timer_read(s->timer[2], offset - 0x20); 248 } 249 250 if (offset >= 0x14) 251 return sh_timer_read(s->timer[1], offset - 0x14); 252 253 if (offset >= 0x08) 254 return sh_timer_read(s->timer[0], offset - 0x08); 255 256 if (offset == 4) 257 return s->tstr; 258 259 if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) 260 return s->tocr; 261 262 hw_error("tmu012_write: Bad offset %x\n", (int)offset); 263 return 0; 264 } 265 266 static void tmu012_write(void *opaque, hwaddr offset, 267 uint64_t value, unsigned size) 268 { 269 tmu012_state *s = (tmu012_state *)opaque; 270 271 #ifdef DEBUG_TIMER 272 printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset, value); 273 #endif 274 275 if (offset >= 0x20) { 276 if (!(s->feat & TMU012_FEAT_3CHAN)) 277 hw_error("tmu012_write: Bad channel offset %x\n", (int)offset); 278 sh_timer_write(s->timer[2], offset - 0x20, value); 279 return; 280 } 281 282 if (offset >= 0x14) { 283 sh_timer_write(s->timer[1], offset - 0x14, value); 284 return; 285 } 286 287 if (offset >= 0x08) { 288 sh_timer_write(s->timer[0], offset - 0x08, value); 289 return; 290 } 291 292 if (offset == 4) { 293 sh_timer_start_stop(s->timer[0], value & (1 << 0)); 294 sh_timer_start_stop(s->timer[1], value & (1 << 1)); 295 if (s->feat & TMU012_FEAT_3CHAN) 296 sh_timer_start_stop(s->timer[2], value & (1 << 2)); 297 else 298 if (value & (1 << 2)) 299 hw_error("tmu012_write: Bad channel\n"); 300 301 s->tstr = value; 302 return; 303 } 304 305 if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) { 306 s->tocr = value & (1 << 0); 307 } 308 } 309 310 static const MemoryRegionOps tmu012_ops = { 311 .read = tmu012_read, 312 .write = tmu012_write, 313 .endianness = DEVICE_NATIVE_ENDIAN, 314 }; 315 316 void tmu012_init(MemoryRegion *sysmem, hwaddr base, 317 int feat, uint32_t freq, 318 qemu_irq ch0_irq, qemu_irq ch1_irq, 319 qemu_irq ch2_irq0, qemu_irq ch2_irq1) 320 { 321 tmu012_state *s; 322 int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0; 323 324 s = (tmu012_state *)g_malloc0(sizeof(tmu012_state)); 325 s->feat = feat; 326 s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq); 327 s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq); 328 if (feat & TMU012_FEAT_3CHAN) 329 s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT, 330 ch2_irq0); /* ch2_irq1 not supported */ 331 332 memory_region_init_io(&s->iomem, NULL, &tmu012_ops, s, 333 "timer", 0x100000000ULL); 334 335 memory_region_init_alias(&s->iomem_p4, NULL, "timer-p4", 336 &s->iomem, 0, 0x1000); 337 memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4); 338 339 memory_region_init_alias(&s->iomem_a7, NULL, "timer-a7", 340 &s->iomem, 0, 0x1000); 341 memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7); 342 /* ??? Save/restore. */ 343 } 344