1 /* 2 * SuperH Timer modules. 3 * 4 * Copyright (c) 2007 Magnus Damm 5 * Based on arm_timer.c by Paul Brook 6 * Copyright (c) 2005-2006 CodeSourcery. 7 * 8 * This code is licensed under the GPL. 9 */ 10 11 #include "qemu/osdep.h" 12 #include "exec/memory.h" 13 #include "hw/hw.h" 14 #include "hw/irq.h" 15 #include "hw/sh4/sh.h" 16 #include "hw/timer/tmu012.h" 17 #include "hw/ptimer.h" 18 19 //#define DEBUG_TIMER 20 21 #define TIMER_TCR_TPSC (7 << 0) 22 #define TIMER_TCR_CKEG (3 << 3) 23 #define TIMER_TCR_UNIE (1 << 5) 24 #define TIMER_TCR_ICPE (3 << 6) 25 #define TIMER_TCR_UNF (1 << 8) 26 #define TIMER_TCR_ICPF (1 << 9) 27 #define TIMER_TCR_RESERVED (0x3f << 10) 28 29 #define TIMER_FEAT_CAPT (1 << 0) 30 #define TIMER_FEAT_EXTCLK (1 << 1) 31 32 #define OFFSET_TCOR 0 33 #define OFFSET_TCNT 1 34 #define OFFSET_TCR 2 35 #define OFFSET_TCPR 3 36 37 typedef struct { 38 ptimer_state *timer; 39 uint32_t tcnt; 40 uint32_t tcor; 41 uint32_t tcr; 42 uint32_t tcpr; 43 int freq; 44 int int_level; 45 int old_level; 46 int feat; 47 int enabled; 48 qemu_irq irq; 49 } sh_timer_state; 50 51 /* Check all active timers, and schedule the next timer interrupt. */ 52 53 static void sh_timer_update(sh_timer_state *s) 54 { 55 int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE); 56 57 if (new_level != s->old_level) { 58 qemu_set_irq(s->irq, new_level); 59 } 60 s->old_level = s->int_level; 61 s->int_level = new_level; 62 } 63 64 static uint32_t sh_timer_read(void *opaque, hwaddr offset) 65 { 66 sh_timer_state *s = (sh_timer_state *)opaque; 67 68 switch (offset >> 2) { 69 case OFFSET_TCOR: 70 return s->tcor; 71 case OFFSET_TCNT: 72 return ptimer_get_count(s->timer); 73 case OFFSET_TCR: 74 return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0); 75 case OFFSET_TCPR: 76 if (s->feat & TIMER_FEAT_CAPT) { 77 return s->tcpr; 78 } 79 /* fall through */ 80 default: 81 hw_error("sh_timer_read: Bad offset %x\n", (int)offset); 82 return 0; 83 } 84 } 85 86 static void sh_timer_write(void *opaque, hwaddr offset, 87 uint32_t value) 88 { 89 sh_timer_state *s = (sh_timer_state *)opaque; 90 int freq; 91 92 switch (offset >> 2) { 93 case OFFSET_TCOR: 94 s->tcor = value; 95 ptimer_transaction_begin(s->timer); 96 ptimer_set_limit(s->timer, s->tcor, 0); 97 ptimer_transaction_commit(s->timer); 98 break; 99 case OFFSET_TCNT: 100 s->tcnt = value; 101 ptimer_transaction_begin(s->timer); 102 ptimer_set_count(s->timer, s->tcnt); 103 ptimer_transaction_commit(s->timer); 104 break; 105 case OFFSET_TCR: 106 ptimer_transaction_begin(s->timer); 107 if (s->enabled) { 108 /* 109 * Pause the timer if it is running. This may cause some inaccuracy 110 * due to rounding, but avoids a whole lot of other messiness 111 */ 112 ptimer_stop(s->timer); 113 } 114 freq = s->freq; 115 /* ??? Need to recalculate expiry time after changing divisor. */ 116 switch (value & TIMER_TCR_TPSC) { 117 case 0: 118 freq >>= 2; 119 break; 120 case 1: 121 freq >>= 4; 122 break; 123 case 2: 124 freq >>= 6; 125 break; 126 case 3: 127 freq >>= 8; 128 break; 129 case 4: 130 freq >>= 10; 131 break; 132 case 6: 133 case 7: 134 if (s->feat & TIMER_FEAT_EXTCLK) { 135 break; 136 } 137 /* fallthrough */ 138 default: 139 hw_error("sh_timer_write: Reserved TPSC value\n"); 140 } 141 switch ((value & TIMER_TCR_CKEG) >> 3) { 142 case 0: 143 break; 144 case 1: 145 case 2: 146 case 3: 147 if (s->feat & TIMER_FEAT_EXTCLK) { 148 break; 149 } 150 /* fallthrough */ 151 default: 152 hw_error("sh_timer_write: Reserved CKEG value\n"); 153 } 154 switch ((value & TIMER_TCR_ICPE) >> 6) { 155 case 0: 156 break; 157 case 2: 158 case 3: 159 if (s->feat & TIMER_FEAT_CAPT) { 160 break; 161 } 162 /* fallthrough */ 163 default: 164 hw_error("sh_timer_write: Reserved ICPE value\n"); 165 } 166 if ((value & TIMER_TCR_UNF) == 0) { 167 s->int_level = 0; 168 } 169 170 value &= ~TIMER_TCR_UNF; 171 172 if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT))) { 173 hw_error("sh_timer_write: Reserved ICPF value\n"); 174 } 175 176 value &= ~TIMER_TCR_ICPF; /* capture not supported */ 177 178 if (value & TIMER_TCR_RESERVED) { 179 hw_error("sh_timer_write: Reserved TCR bits set\n"); 180 } 181 s->tcr = value; 182 ptimer_set_limit(s->timer, s->tcor, 0); 183 ptimer_set_freq(s->timer, freq); 184 if (s->enabled) { 185 /* Restart the timer if still enabled. */ 186 ptimer_run(s->timer, 0); 187 } 188 ptimer_transaction_commit(s->timer); 189 break; 190 case OFFSET_TCPR: 191 if (s->feat & TIMER_FEAT_CAPT) { 192 s->tcpr = value; 193 break; 194 } 195 /* fallthrough */ 196 default: 197 hw_error("sh_timer_write: Bad offset %x\n", (int)offset); 198 } 199 sh_timer_update(s); 200 } 201 202 static void sh_timer_start_stop(void *opaque, int enable) 203 { 204 sh_timer_state *s = (sh_timer_state *)opaque; 205 206 #ifdef DEBUG_TIMER 207 printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled); 208 #endif 209 210 ptimer_transaction_begin(s->timer); 211 if (s->enabled && !enable) { 212 ptimer_stop(s->timer); 213 } 214 if (!s->enabled && enable) { 215 ptimer_run(s->timer, 0); 216 } 217 ptimer_transaction_commit(s->timer); 218 s->enabled = !!enable; 219 220 #ifdef DEBUG_TIMER 221 printf("sh_timer_start_stop done %d\n", s->enabled); 222 #endif 223 } 224 225 static void sh_timer_tick(void *opaque) 226 { 227 sh_timer_state *s = (sh_timer_state *)opaque; 228 s->int_level = s->enabled; 229 sh_timer_update(s); 230 } 231 232 static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq) 233 { 234 sh_timer_state *s; 235 236 s = g_malloc0(sizeof(*s)); 237 s->freq = freq; 238 s->feat = feat; 239 s->tcor = 0xffffffff; 240 s->tcnt = 0xffffffff; 241 s->tcpr = 0xdeadbeef; 242 s->tcr = 0; 243 s->enabled = 0; 244 s->irq = irq; 245 246 s->timer = ptimer_init(sh_timer_tick, s, PTIMER_POLICY_DEFAULT); 247 248 sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor); 249 sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt); 250 sh_timer_write(s, OFFSET_TCPR >> 2, s->tcpr); 251 sh_timer_write(s, OFFSET_TCR >> 2, s->tcpr); 252 /* ??? Save/restore. */ 253 return s; 254 } 255 256 typedef struct { 257 MemoryRegion iomem; 258 MemoryRegion iomem_p4; 259 MemoryRegion iomem_a7; 260 void *timer[3]; 261 int level[3]; 262 uint32_t tocr; 263 uint32_t tstr; 264 int feat; 265 } tmu012_state; 266 267 static uint64_t tmu012_read(void *opaque, hwaddr offset, 268 unsigned size) 269 { 270 tmu012_state *s = (tmu012_state *)opaque; 271 272 #ifdef DEBUG_TIMER 273 printf("tmu012_read 0x%lx\n", (unsigned long) offset); 274 #endif 275 276 if (offset >= 0x20) { 277 if (!(s->feat & TMU012_FEAT_3CHAN)) { 278 hw_error("tmu012_write: Bad channel offset %x\n", (int)offset); 279 } 280 return sh_timer_read(s->timer[2], offset - 0x20); 281 } 282 283 if (offset >= 0x14) { 284 return sh_timer_read(s->timer[1], offset - 0x14); 285 } 286 if (offset >= 0x08) { 287 return sh_timer_read(s->timer[0], offset - 0x08); 288 } 289 if (offset == 4) { 290 return s->tstr; 291 } 292 if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) { 293 return s->tocr; 294 } 295 296 hw_error("tmu012_write: Bad offset %x\n", (int)offset); 297 return 0; 298 } 299 300 static void tmu012_write(void *opaque, hwaddr offset, 301 uint64_t value, unsigned size) 302 { 303 tmu012_state *s = (tmu012_state *)opaque; 304 305 #ifdef DEBUG_TIMER 306 printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset, value); 307 #endif 308 309 if (offset >= 0x20) { 310 if (!(s->feat & TMU012_FEAT_3CHAN)) { 311 hw_error("tmu012_write: Bad channel offset %x\n", (int)offset); 312 } 313 sh_timer_write(s->timer[2], offset - 0x20, value); 314 return; 315 } 316 317 if (offset >= 0x14) { 318 sh_timer_write(s->timer[1], offset - 0x14, value); 319 return; 320 } 321 322 if (offset >= 0x08) { 323 sh_timer_write(s->timer[0], offset - 0x08, value); 324 return; 325 } 326 327 if (offset == 4) { 328 sh_timer_start_stop(s->timer[0], value & (1 << 0)); 329 sh_timer_start_stop(s->timer[1], value & (1 << 1)); 330 if (s->feat & TMU012_FEAT_3CHAN) { 331 sh_timer_start_stop(s->timer[2], value & (1 << 2)); 332 } else { 333 if (value & (1 << 2)) { 334 hw_error("tmu012_write: Bad channel\n"); 335 } 336 } 337 338 s->tstr = value; 339 return; 340 } 341 342 if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) { 343 s->tocr = value & (1 << 0); 344 } 345 } 346 347 static const MemoryRegionOps tmu012_ops = { 348 .read = tmu012_read, 349 .write = tmu012_write, 350 .endianness = DEVICE_NATIVE_ENDIAN, 351 }; 352 353 void tmu012_init(MemoryRegion *sysmem, hwaddr base, 354 int feat, uint32_t freq, 355 qemu_irq ch0_irq, qemu_irq ch1_irq, 356 qemu_irq ch2_irq0, qemu_irq ch2_irq1) 357 { 358 tmu012_state *s; 359 int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0; 360 361 s = g_malloc0(sizeof(*s)); 362 s->feat = feat; 363 s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq); 364 s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq); 365 if (feat & TMU012_FEAT_3CHAN) { 366 s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT, 367 ch2_irq0); /* ch2_irq1 not supported */ 368 } 369 370 memory_region_init_io(&s->iomem, NULL, &tmu012_ops, s, 371 "timer", 0x100000000ULL); 372 373 memory_region_init_alias(&s->iomem_p4, NULL, "timer-p4", 374 &s->iomem, 0, 0x1000); 375 memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4); 376 377 memory_region_init_alias(&s->iomem_a7, NULL, "timer-a7", 378 &s->iomem, 0, 0x1000); 379 memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7); 380 /* ??? Save/restore. */ 381 } 382