1 /* 2 * IMX GPT Timer 3 * 4 * Copyright (c) 2008 OK Labs 5 * Copyright (c) 2011 NICTA Pty Ltd 6 * Originally written by Hans Jiang 7 * Updated by Peter Chubb 8 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> 9 * 10 * This code is licensed under GPL version 2 or later. See 11 * the COPYING file in the top-level directory. 12 * 13 */ 14 15 #include "qemu/osdep.h" 16 #include "hw/irq.h" 17 #include "hw/timer/imx_gpt.h" 18 #include "migration/vmstate.h" 19 #include "qemu/module.h" 20 #include "qemu/log.h" 21 #include "trace.h" 22 23 static const char *imx_gpt_reg_name(uint32_t reg) 24 { 25 switch (reg) { 26 case 0: 27 return "CR"; 28 case 1: 29 return "PR"; 30 case 2: 31 return "SR"; 32 case 3: 33 return "IR"; 34 case 4: 35 return "OCR1"; 36 case 5: 37 return "OCR2"; 38 case 6: 39 return "OCR3"; 40 case 7: 41 return "ICR1"; 42 case 8: 43 return "ICR2"; 44 case 9: 45 return "CNT"; 46 default: 47 return "[?]"; 48 } 49 } 50 51 static const VMStateDescription vmstate_imx_timer_gpt = { 52 .name = TYPE_IMX_GPT, 53 .version_id = 3, 54 .minimum_version_id = 3, 55 .fields = (const VMStateField[]) { 56 VMSTATE_UINT32(cr, IMXGPTState), 57 VMSTATE_UINT32(pr, IMXGPTState), 58 VMSTATE_UINT32(sr, IMXGPTState), 59 VMSTATE_UINT32(ir, IMXGPTState), 60 VMSTATE_UINT32(ocr1, IMXGPTState), 61 VMSTATE_UINT32(ocr2, IMXGPTState), 62 VMSTATE_UINT32(ocr3, IMXGPTState), 63 VMSTATE_UINT32(icr1, IMXGPTState), 64 VMSTATE_UINT32(icr2, IMXGPTState), 65 VMSTATE_UINT32(cnt, IMXGPTState), 66 VMSTATE_UINT32(next_timeout, IMXGPTState), 67 VMSTATE_UINT32(next_int, IMXGPTState), 68 VMSTATE_UINT32(freq, IMXGPTState), 69 VMSTATE_PTIMER(timer, IMXGPTState), 70 VMSTATE_END_OF_LIST() 71 } 72 }; 73 74 static const IMXClk imx25_gpt_clocks[] = { 75 CLK_NONE, /* 000 No clock source */ 76 CLK_IPG, /* 001 ipg_clk, 532MHz*/ 77 CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ 78 CLK_NONE, /* 011 not defined */ 79 CLK_32k, /* 100 ipg_clk_32k */ 80 CLK_32k, /* 101 ipg_clk_32k */ 81 CLK_32k, /* 110 ipg_clk_32k */ 82 CLK_32k, /* 111 ipg_clk_32k */ 83 }; 84 85 static const IMXClk imx31_gpt_clocks[] = { 86 CLK_NONE, /* 000 No clock source */ 87 CLK_IPG, /* 001 ipg_clk, 532MHz*/ 88 CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ 89 CLK_NONE, /* 011 not defined */ 90 CLK_32k, /* 100 ipg_clk_32k */ 91 CLK_NONE, /* 101 not defined */ 92 CLK_NONE, /* 110 not defined */ 93 CLK_NONE, /* 111 not defined */ 94 }; 95 96 static const IMXClk imx6_gpt_clocks[] = { 97 CLK_NONE, /* 000 No clock source */ 98 CLK_IPG, /* 001 ipg_clk, 532MHz*/ 99 CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ 100 CLK_EXT, /* 011 External clock */ 101 CLK_32k, /* 100 ipg_clk_32k */ 102 CLK_HIGH_DIV, /* 101 reference clock / 8 */ 103 CLK_NONE, /* 110 not defined */ 104 CLK_HIGH, /* 111 reference clock */ 105 }; 106 107 static const IMXClk imx6ul_gpt_clocks[] = { 108 CLK_NONE, /* 000 No clock source */ 109 CLK_IPG, /* 001 ipg_clk, 532MHz*/ 110 CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ 111 CLK_EXT, /* 011 External clock */ 112 CLK_32k, /* 100 ipg_clk_32k */ 113 CLK_NONE, /* 101 not defined */ 114 CLK_NONE, /* 110 not defined */ 115 CLK_NONE, /* 111 not defined */ 116 }; 117 118 static const IMXClk imx7_gpt_clocks[] = { 119 CLK_NONE, /* 000 No clock source */ 120 CLK_IPG, /* 001 ipg_clk, 532MHz*/ 121 CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ 122 CLK_EXT, /* 011 External clock */ 123 CLK_32k, /* 100 ipg_clk_32k */ 124 CLK_HIGH, /* 101 reference clock */ 125 CLK_NONE, /* 110 not defined */ 126 CLK_NONE, /* 111 not defined */ 127 }; 128 129 static const IMXClk imx8mp_gpt_clocks[] = { 130 CLK_NONE, /* 000 No clock source */ 131 CLK_IPG, /* 001 ipg_clk, 532MHz */ 132 CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ 133 CLK_EXT, /* 011 External clock */ 134 CLK_32k, /* 100 ipg_clk_32k */ 135 CLK_HIGH, /* 101 ipg_clk_16M */ 136 CLK_NONE, /* 110 not defined */ 137 CLK_NONE, /* 111 not defined */ 138 }; 139 140 /* Must be called from within ptimer_transaction_begin/commit block */ 141 static void imx_gpt_set_freq(IMXGPTState *s) 142 { 143 uint32_t clksrc = extract32(s->cr, GPT_CR_CLKSRC_SHIFT, 3); 144 145 s->freq = imx_ccm_get_clock_frequency(s->ccm, 146 s->clocks[clksrc]) / (1 + s->pr); 147 148 trace_imx_gpt_set_freq(clksrc, s->freq); 149 150 if (s->freq) { 151 ptimer_set_freq(s->timer, s->freq); 152 } 153 } 154 155 static void imx_gpt_update_int(IMXGPTState *s) 156 { 157 if ((s->sr & s->ir) && (s->cr & GPT_CR_EN)) { 158 qemu_irq_raise(s->irq); 159 } else { 160 qemu_irq_lower(s->irq); 161 } 162 } 163 164 static uint32_t imx_gpt_update_count(IMXGPTState *s) 165 { 166 s->cnt = s->next_timeout - (uint32_t)ptimer_get_count(s->timer); 167 168 return s->cnt; 169 } 170 171 static inline uint32_t imx_gpt_find_limit(uint32_t count, uint32_t reg, 172 uint32_t timeout) 173 { 174 if ((count < reg) && (timeout > reg)) { 175 timeout = reg; 176 } 177 178 return timeout; 179 } 180 181 /* Must be called from within ptimer_transaction_begin/commit block */ 182 static void imx_gpt_compute_next_timeout(IMXGPTState *s, bool event) 183 { 184 uint32_t timeout = GPT_TIMER_MAX; 185 uint32_t count; 186 long long limit; 187 188 if (!(s->cr & GPT_CR_EN)) { 189 /* if not enabled just return */ 190 return; 191 } 192 193 /* update the count */ 194 count = imx_gpt_update_count(s); 195 196 if (event) { 197 /* 198 * This is an event (the ptimer reached 0 and stopped), and the 199 * timer counter is now equal to s->next_timeout. 200 */ 201 if (!(s->cr & GPT_CR_FRR) && (count == s->ocr1)) { 202 /* We are in restart mode and we crossed the compare channel 1 203 * value. We need to reset the counter to 0. 204 */ 205 count = s->cnt = s->next_timeout = 0; 206 } else if (count == GPT_TIMER_MAX) { 207 /* We reached GPT_TIMER_MAX so we need to rollover */ 208 count = s->cnt = s->next_timeout = 0; 209 } 210 } 211 212 /* now, find the next timeout related to count */ 213 214 if (s->ir & GPT_IR_OF1IE) { 215 timeout = imx_gpt_find_limit(count, s->ocr1, timeout); 216 } 217 if (s->ir & GPT_IR_OF2IE) { 218 timeout = imx_gpt_find_limit(count, s->ocr2, timeout); 219 } 220 if (s->ir & GPT_IR_OF3IE) { 221 timeout = imx_gpt_find_limit(count, s->ocr3, timeout); 222 } 223 224 /* find the next set of interrupts to raise for next timer event */ 225 226 s->next_int = 0; 227 if ((s->ir & GPT_IR_OF1IE) && (timeout == s->ocr1)) { 228 s->next_int |= GPT_SR_OF1; 229 } 230 if ((s->ir & GPT_IR_OF2IE) && (timeout == s->ocr2)) { 231 s->next_int |= GPT_SR_OF2; 232 } 233 if ((s->ir & GPT_IR_OF3IE) && (timeout == s->ocr3)) { 234 s->next_int |= GPT_SR_OF3; 235 } 236 if ((s->ir & GPT_IR_ROVIE) && (timeout == GPT_TIMER_MAX)) { 237 s->next_int |= GPT_SR_ROV; 238 } 239 240 /* the new range to count down from */ 241 limit = timeout - imx_gpt_update_count(s); 242 243 if (limit < 0) { 244 /* 245 * if we reach here, then QEMU is running too slow and we pass the 246 * timeout limit while computing it. Let's deliver the interrupt 247 * and compute a new limit. 248 */ 249 s->sr |= s->next_int; 250 251 imx_gpt_compute_next_timeout(s, event); 252 253 imx_gpt_update_int(s); 254 } else { 255 /* New timeout value */ 256 s->next_timeout = timeout; 257 258 /* reset the limit to the computed range */ 259 ptimer_set_limit(s->timer, limit, 1); 260 } 261 } 262 263 static uint64_t imx_gpt_read(void *opaque, hwaddr offset, unsigned size) 264 { 265 IMXGPTState *s = IMX_GPT(opaque); 266 uint32_t reg_value = 0; 267 268 switch (offset >> 2) { 269 case 0: /* Control Register */ 270 reg_value = s->cr; 271 break; 272 273 case 1: /* prescaler */ 274 reg_value = s->pr; 275 break; 276 277 case 2: /* Status Register */ 278 reg_value = s->sr; 279 break; 280 281 case 3: /* Interrupt Register */ 282 reg_value = s->ir; 283 break; 284 285 case 4: /* Output Compare Register 1 */ 286 reg_value = s->ocr1; 287 break; 288 289 case 5: /* Output Compare Register 2 */ 290 reg_value = s->ocr2; 291 break; 292 293 case 6: /* Output Compare Register 3 */ 294 reg_value = s->ocr3; 295 break; 296 297 case 7: /* input Capture Register 1 */ 298 qemu_log_mask(LOG_UNIMP, "[%s]%s: icr1 feature is not implemented\n", 299 TYPE_IMX_GPT, __func__); 300 reg_value = s->icr1; 301 break; 302 303 case 8: /* input Capture Register 2 */ 304 qemu_log_mask(LOG_UNIMP, "[%s]%s: icr2 feature is not implemented\n", 305 TYPE_IMX_GPT, __func__); 306 reg_value = s->icr2; 307 break; 308 309 case 9: /* cnt */ 310 imx_gpt_update_count(s); 311 reg_value = s->cnt; 312 break; 313 314 default: 315 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 316 HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset); 317 break; 318 } 319 320 trace_imx_gpt_read(imx_gpt_reg_name(offset >> 2), reg_value); 321 322 return reg_value; 323 } 324 325 326 static void imx_gpt_reset_common(IMXGPTState *s, bool is_soft_reset) 327 { 328 ptimer_transaction_begin(s->timer); 329 /* stop timer */ 330 ptimer_stop(s->timer); 331 332 /* Soft reset and hard reset differ only in their handling of the CR 333 * register -- soft reset preserves the values of some bits there. 334 */ 335 if (is_soft_reset) { 336 /* Clear all CR bits except those that are preserved by soft reset. */ 337 s->cr &= GPT_CR_EN | GPT_CR_ENMOD | GPT_CR_STOPEN | GPT_CR_DOZEN | 338 GPT_CR_WAITEN | GPT_CR_DBGEN | 339 (GPT_CR_CLKSRC_MASK << GPT_CR_CLKSRC_SHIFT); 340 } else { 341 s->cr = 0; 342 } 343 s->sr = 0; 344 s->pr = 0; 345 s->ir = 0; 346 s->cnt = 0; 347 s->ocr1 = GPT_TIMER_MAX; 348 s->ocr2 = GPT_TIMER_MAX; 349 s->ocr3 = GPT_TIMER_MAX; 350 s->icr1 = 0; 351 s->icr2 = 0; 352 353 s->next_timeout = GPT_TIMER_MAX; 354 s->next_int = 0; 355 356 /* compute new freq */ 357 imx_gpt_set_freq(s); 358 359 /* reset the limit to GPT_TIMER_MAX */ 360 ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1); 361 362 /* if the timer is still enabled, restart it */ 363 if (s->freq && (s->cr & GPT_CR_EN)) { 364 ptimer_run(s->timer, 1); 365 } 366 ptimer_transaction_commit(s->timer); 367 } 368 369 static void imx_gpt_soft_reset(DeviceState *dev) 370 { 371 IMXGPTState *s = IMX_GPT(dev); 372 imx_gpt_reset_common(s, true); 373 } 374 375 static void imx_gpt_reset(DeviceState *dev) 376 { 377 IMXGPTState *s = IMX_GPT(dev); 378 imx_gpt_reset_common(s, false); 379 } 380 381 static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value, 382 unsigned size) 383 { 384 IMXGPTState *s = IMX_GPT(opaque); 385 uint32_t oldreg; 386 387 trace_imx_gpt_write(imx_gpt_reg_name(offset >> 2), (uint32_t)value); 388 389 switch (offset >> 2) { 390 case 0: 391 oldreg = s->cr; 392 s->cr = value & ~0x7c14; 393 if (s->cr & GPT_CR_SWR) { /* force reset */ 394 /* handle the reset */ 395 imx_gpt_soft_reset(DEVICE(s)); 396 } else { 397 /* set our freq, as the source might have changed */ 398 ptimer_transaction_begin(s->timer); 399 imx_gpt_set_freq(s); 400 401 if ((oldreg ^ s->cr) & GPT_CR_EN) { 402 if (s->cr & GPT_CR_EN) { 403 if (s->cr & GPT_CR_ENMOD) { 404 s->next_timeout = GPT_TIMER_MAX; 405 ptimer_set_count(s->timer, GPT_TIMER_MAX); 406 imx_gpt_compute_next_timeout(s, false); 407 } 408 ptimer_run(s->timer, 1); 409 } else { 410 /* stop timer */ 411 ptimer_stop(s->timer); 412 } 413 } 414 ptimer_transaction_commit(s->timer); 415 } 416 break; 417 418 case 1: /* Prescaler */ 419 s->pr = value & 0xfff; 420 ptimer_transaction_begin(s->timer); 421 imx_gpt_set_freq(s); 422 ptimer_transaction_commit(s->timer); 423 break; 424 425 case 2: /* SR */ 426 s->sr &= ~(value & 0x3f); 427 imx_gpt_update_int(s); 428 break; 429 430 case 3: /* IR -- interrupt register */ 431 s->ir = value & 0x3f; 432 imx_gpt_update_int(s); 433 434 ptimer_transaction_begin(s->timer); 435 imx_gpt_compute_next_timeout(s, false); 436 ptimer_transaction_commit(s->timer); 437 438 break; 439 440 case 4: /* OCR1 -- output compare register */ 441 s->ocr1 = value; 442 443 ptimer_transaction_begin(s->timer); 444 /* In non-freerun mode, reset count when this register is written */ 445 if (!(s->cr & GPT_CR_FRR)) { 446 s->next_timeout = GPT_TIMER_MAX; 447 ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1); 448 } 449 450 /* compute the new timeout */ 451 imx_gpt_compute_next_timeout(s, false); 452 ptimer_transaction_commit(s->timer); 453 454 break; 455 456 case 5: /* OCR2 -- output compare register */ 457 s->ocr2 = value; 458 459 /* compute the new timeout */ 460 ptimer_transaction_begin(s->timer); 461 imx_gpt_compute_next_timeout(s, false); 462 ptimer_transaction_commit(s->timer); 463 464 break; 465 466 case 6: /* OCR3 -- output compare register */ 467 s->ocr3 = value; 468 469 /* compute the new timeout */ 470 ptimer_transaction_begin(s->timer); 471 imx_gpt_compute_next_timeout(s, false); 472 ptimer_transaction_commit(s->timer); 473 474 break; 475 476 default: 477 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 478 HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset); 479 break; 480 } 481 } 482 483 static void imx_gpt_timeout(void *opaque) 484 { 485 IMXGPTState *s = IMX_GPT(opaque); 486 487 trace_imx_gpt_timeout(); 488 489 s->sr |= s->next_int; 490 s->next_int = 0; 491 492 imx_gpt_compute_next_timeout(s, true); 493 494 imx_gpt_update_int(s); 495 496 if (s->freq && (s->cr & GPT_CR_EN)) { 497 ptimer_run(s->timer, 1); 498 } 499 } 500 501 static const MemoryRegionOps imx_gpt_ops = { 502 .read = imx_gpt_read, 503 .write = imx_gpt_write, 504 .endianness = DEVICE_NATIVE_ENDIAN, 505 }; 506 507 508 static void imx_gpt_realize(DeviceState *dev, Error **errp) 509 { 510 IMXGPTState *s = IMX_GPT(dev); 511 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 512 513 sysbus_init_irq(sbd, &s->irq); 514 memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpt_ops, s, TYPE_IMX_GPT, 515 0x00001000); 516 sysbus_init_mmio(sbd, &s->iomem); 517 518 s->timer = ptimer_init(imx_gpt_timeout, s, PTIMER_POLICY_LEGACY); 519 } 520 521 static void imx_gpt_class_init(ObjectClass *klass, const void *data) 522 { 523 DeviceClass *dc = DEVICE_CLASS(klass); 524 525 dc->realize = imx_gpt_realize; 526 device_class_set_legacy_reset(dc, imx_gpt_reset); 527 dc->vmsd = &vmstate_imx_timer_gpt; 528 dc->desc = "i.MX general timer"; 529 } 530 531 static void imx25_gpt_init(Object *obj) 532 { 533 IMXGPTState *s = IMX_GPT(obj); 534 535 s->clocks = imx25_gpt_clocks; 536 } 537 538 static void imx31_gpt_init(Object *obj) 539 { 540 IMXGPTState *s = IMX_GPT(obj); 541 542 s->clocks = imx31_gpt_clocks; 543 } 544 545 static void imx6_gpt_init(Object *obj) 546 { 547 IMXGPTState *s = IMX_GPT(obj); 548 549 s->clocks = imx6_gpt_clocks; 550 } 551 552 static void imx6ul_gpt_init(Object *obj) 553 { 554 IMXGPTState *s = IMX_GPT(obj); 555 556 s->clocks = imx6ul_gpt_clocks; 557 } 558 559 static void imx7_gpt_init(Object *obj) 560 { 561 IMXGPTState *s = IMX_GPT(obj); 562 563 s->clocks = imx7_gpt_clocks; 564 } 565 566 static void imx8mp_gpt_init(Object *obj) 567 { 568 IMXGPTState *s = IMX_GPT(obj); 569 570 s->clocks = imx8mp_gpt_clocks; 571 } 572 573 static const TypeInfo imx25_gpt_info = { 574 .name = TYPE_IMX25_GPT, 575 .parent = TYPE_SYS_BUS_DEVICE, 576 .instance_size = sizeof(IMXGPTState), 577 .instance_init = imx25_gpt_init, 578 .class_init = imx_gpt_class_init, 579 }; 580 581 static const TypeInfo imx31_gpt_info = { 582 .name = TYPE_IMX31_GPT, 583 .parent = TYPE_IMX25_GPT, 584 .instance_init = imx31_gpt_init, 585 }; 586 587 static const TypeInfo imx6_gpt_info = { 588 .name = TYPE_IMX6_GPT, 589 .parent = TYPE_IMX25_GPT, 590 .instance_init = imx6_gpt_init, 591 }; 592 593 static const TypeInfo imx6ul_gpt_info = { 594 .name = TYPE_IMX6UL_GPT, 595 .parent = TYPE_IMX25_GPT, 596 .instance_init = imx6ul_gpt_init, 597 }; 598 599 static const TypeInfo imx7_gpt_info = { 600 .name = TYPE_IMX7_GPT, 601 .parent = TYPE_IMX25_GPT, 602 .instance_init = imx7_gpt_init, 603 }; 604 605 static const TypeInfo imx8mp_gpt_info = { 606 .name = TYPE_IMX8MP_GPT, 607 .parent = TYPE_IMX25_GPT, 608 .instance_init = imx8mp_gpt_init, 609 }; 610 611 static void imx_gpt_register_types(void) 612 { 613 type_register_static(&imx25_gpt_info); 614 type_register_static(&imx31_gpt_info); 615 type_register_static(&imx6_gpt_info); 616 type_register_static(&imx6ul_gpt_info); 617 type_register_static(&imx7_gpt_info); 618 type_register_static(&imx8mp_gpt_info); 619 } 620 621 type_init(imx_gpt_register_types) 622