1 /* 2 * IMX EPIT Timer 3 * 4 * Copyright (c) 2008 OK Labs 5 * Copyright (c) 2011 NICTA Pty Ltd 6 * Originally written by Hans Jiang 7 * Updated by Peter Chubb 8 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> 9 * 10 * This code is licensed under GPL version 2 or later. See 11 * the COPYING file in the top-level directory. 12 * 13 */ 14 15 #include "qemu/osdep.h" 16 #include "hw/timer/imx_epit.h" 17 #include "migration/vmstate.h" 18 #include "hw/irq.h" 19 #include "hw/misc/imx_ccm.h" 20 #include "qemu/module.h" 21 #include "qemu/log.h" 22 23 #ifndef DEBUG_IMX_EPIT 24 #define DEBUG_IMX_EPIT 0 25 #endif 26 27 #define DPRINTF(fmt, args...) \ 28 do { \ 29 if (DEBUG_IMX_EPIT) { \ 30 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_EPIT, \ 31 __func__, ##args); \ 32 } \ 33 } while (0) 34 35 static const char *imx_epit_reg_name(uint32_t reg) 36 { 37 switch (reg) { 38 case 0: 39 return "CR"; 40 case 1: 41 return "SR"; 42 case 2: 43 return "LR"; 44 case 3: 45 return "CMP"; 46 case 4: 47 return "CNT"; 48 default: 49 return "[?]"; 50 } 51 } 52 53 /* 54 * Exact clock frequencies vary from board to board. 55 * These are typical. 56 */ 57 static const IMXClk imx_epit_clocks[] = { 58 CLK_NONE, /* 00 disabled */ 59 CLK_IPG, /* 01 ipg_clk, ~532MHz */ 60 CLK_IPG_HIGH, /* 10 ipg_clk_highfreq */ 61 CLK_32k, /* 11 ipg_clk_32k -- ~32kHz */ 62 }; 63 64 /* 65 * Update interrupt status 66 */ 67 static void imx_epit_update_int(IMXEPITState *s) 68 { 69 if ((s->sr & SR_OCIF) && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) { 70 qemu_irq_raise(s->irq); 71 } else { 72 qemu_irq_lower(s->irq); 73 } 74 } 75 76 static uint32_t imx_epit_get_freq(IMXEPITState *s) 77 { 78 uint32_t clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS); 79 uint32_t prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRESCALE_BITS); 80 uint32_t f_in = imx_ccm_get_clock_frequency(s->ccm, imx_epit_clocks[clksrc]); 81 uint32_t freq = f_in / prescaler; 82 DPRINTF("ptimer frequency is %u\n", freq); 83 return freq; 84 } 85 86 /* 87 * This is called both on hardware (device) reset and software reset. 88 */ 89 static void imx_epit_reset(IMXEPITState *s, bool is_hard_reset) 90 { 91 /* Soft reset doesn't touch some bits; hard reset clears them */ 92 if (is_hard_reset) { 93 s->cr = 0; 94 } else { 95 s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN); 96 } 97 s->sr = 0; 98 s->lr = EPIT_TIMER_MAX; 99 s->cmp = 0; 100 ptimer_transaction_begin(s->timer_cmp); 101 ptimer_transaction_begin(s->timer_reload); 102 103 /* 104 * The reset switches off the input clock, so even if the CR.EN is still 105 * set, the timers are no longer running. 106 */ 107 assert(imx_epit_get_freq(s) == 0); 108 ptimer_stop(s->timer_cmp); 109 ptimer_stop(s->timer_reload); 110 /* init both timers to EPIT_TIMER_MAX */ 111 ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1); 112 ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1); 113 ptimer_transaction_commit(s->timer_cmp); 114 ptimer_transaction_commit(s->timer_reload); 115 } 116 117 static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size) 118 { 119 IMXEPITState *s = IMX_EPIT(opaque); 120 uint32_t reg_value = 0; 121 122 switch (offset >> 2) { 123 case 0: /* Control Register */ 124 reg_value = s->cr; 125 break; 126 127 case 1: /* Status Register */ 128 reg_value = s->sr; 129 break; 130 131 case 2: /* LR - ticks*/ 132 reg_value = s->lr; 133 break; 134 135 case 3: /* CMP */ 136 reg_value = s->cmp; 137 break; 138 139 case 4: /* CNT */ 140 reg_value = ptimer_get_count(s->timer_reload); 141 break; 142 143 default: 144 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 145 HWADDR_PRIx "\n", TYPE_IMX_EPIT, __func__, offset); 146 break; 147 } 148 149 DPRINTF("(%s) = 0x%08x\n", imx_epit_reg_name(offset >> 2), reg_value); 150 151 return reg_value; 152 } 153 154 /* Must be called from ptimer_transaction_begin/commit block for s->timer_cmp */ 155 static void imx_epit_reload_compare_timer(IMXEPITState *s) 156 { 157 if ((s->cr & (CR_EN | CR_OCIEN)) == (CR_EN | CR_OCIEN)) { 158 /* if the compare feature is on and timers are running */ 159 uint32_t tmp = ptimer_get_count(s->timer_reload); 160 uint64_t next; 161 if (tmp > s->cmp) { 162 /* It'll fire in this round of the timer */ 163 next = tmp - s->cmp; 164 } else { /* catch it next time around */ 165 next = tmp - s->cmp + ((s->cr & CR_RLD) ? EPIT_TIMER_MAX : s->lr); 166 } 167 ptimer_set_count(s->timer_cmp, next); 168 } 169 } 170 171 static void imx_epit_write_cr(IMXEPITState *s, uint32_t value) 172 { 173 uint32_t freq = 0; 174 uint32_t oldcr = s->cr; 175 176 s->cr = value & 0x03ffffff; 177 178 if (s->cr & CR_SWR) { 179 /* handle the reset */ 180 imx_epit_reset(s, false); 181 } 182 183 /* 184 * The interrupt state can change due to: 185 * - reset clears both SR.OCIF and CR.OCIE 186 * - write to CR.EN or CR.OCIE 187 */ 188 imx_epit_update_int(s); 189 190 /* 191 * TODO: could we 'break' here for reset? following operations appear 192 * to duplicate the work imx_epit_reset() already did. 193 */ 194 195 ptimer_transaction_begin(s->timer_cmp); 196 ptimer_transaction_begin(s->timer_reload); 197 198 /* 199 * Update the frequency. In case of a reset the input clock was 200 * switched off, so this can be skipped. 201 */ 202 if (!(s->cr & CR_SWR)) { 203 freq = imx_epit_get_freq(s); 204 if (freq) { 205 ptimer_set_freq(s->timer_reload, freq); 206 ptimer_set_freq(s->timer_cmp, freq); 207 } 208 } 209 210 if (freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) { 211 if (s->cr & CR_ENMOD) { 212 if (s->cr & CR_RLD) { 213 ptimer_set_limit(s->timer_reload, s->lr, 1); 214 ptimer_set_limit(s->timer_cmp, s->lr, 1); 215 } else { 216 ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1); 217 ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1); 218 } 219 } 220 221 imx_epit_reload_compare_timer(s); 222 ptimer_run(s->timer_reload, 0); 223 if (s->cr & CR_OCIEN) { 224 ptimer_run(s->timer_cmp, 0); 225 } else { 226 ptimer_stop(s->timer_cmp); 227 } 228 } else if (!(s->cr & CR_EN)) { 229 /* stop both timers */ 230 ptimer_stop(s->timer_reload); 231 ptimer_stop(s->timer_cmp); 232 } else if (s->cr & CR_OCIEN) { 233 if (!(oldcr & CR_OCIEN)) { 234 imx_epit_reload_compare_timer(s); 235 ptimer_run(s->timer_cmp, 0); 236 } 237 } else { 238 ptimer_stop(s->timer_cmp); 239 } 240 241 ptimer_transaction_commit(s->timer_cmp); 242 ptimer_transaction_commit(s->timer_reload); 243 } 244 245 static void imx_epit_write_sr(IMXEPITState *s, uint32_t value) 246 { 247 /* writing 1 to SR.OCIF clears this bit and turns the interrupt off */ 248 if (value & SR_OCIF) { 249 s->sr = 0; /* SR.OCIF is the only bit in this register anyway */ 250 imx_epit_update_int(s); 251 } 252 } 253 254 static void imx_epit_write_lr(IMXEPITState *s, uint32_t value) 255 { 256 s->lr = value; 257 258 ptimer_transaction_begin(s->timer_cmp); 259 ptimer_transaction_begin(s->timer_reload); 260 if (s->cr & CR_RLD) { 261 /* Also set the limit if the LRD bit is set */ 262 /* If IOVW bit is set then set the timer value */ 263 ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW); 264 ptimer_set_limit(s->timer_cmp, s->lr, 0); 265 } else if (s->cr & CR_IOVW) { 266 /* If IOVW bit is set then set the timer value */ 267 ptimer_set_count(s->timer_reload, s->lr); 268 } 269 /* 270 * Commit the change to s->timer_reload, so it can propagate. Otherwise 271 * the timer interrupt may not fire properly. The commit must happen 272 * before calling imx_epit_reload_compare_timer(), which reads 273 * s->timer_reload internally again. 274 */ 275 ptimer_transaction_commit(s->timer_reload); 276 imx_epit_reload_compare_timer(s); 277 ptimer_transaction_commit(s->timer_cmp); 278 } 279 280 static void imx_epit_write_cmp(IMXEPITState *s, uint32_t value) 281 { 282 s->cmp = value; 283 284 ptimer_transaction_begin(s->timer_cmp); 285 imx_epit_reload_compare_timer(s); 286 ptimer_transaction_commit(s->timer_cmp); 287 } 288 289 static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, 290 unsigned size) 291 { 292 IMXEPITState *s = IMX_EPIT(opaque); 293 294 DPRINTF("(%s, value = 0x%08x)\n", imx_epit_reg_name(offset >> 2), 295 (uint32_t)value); 296 297 switch (offset >> 2) { 298 case 0: /* CR */ 299 imx_epit_write_cr(s, (uint32_t)value); 300 break; 301 302 case 1: /* SR */ 303 imx_epit_write_sr(s, (uint32_t)value); 304 break; 305 306 case 2: /* LR */ 307 imx_epit_write_lr(s, (uint32_t)value); 308 break; 309 310 case 3: /* CMP */ 311 imx_epit_write_cmp(s, (uint32_t)value); 312 break; 313 314 default: 315 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 316 HWADDR_PRIx "\n", TYPE_IMX_EPIT, __func__, offset); 317 break; 318 } 319 } 320 321 static void imx_epit_cmp(void *opaque) 322 { 323 IMXEPITState *s = IMX_EPIT(opaque); 324 325 DPRINTF("sr was %d\n", s->sr); 326 /* Set interrupt status bit SR.OCIF and update the interrupt state */ 327 s->sr |= SR_OCIF; 328 imx_epit_update_int(s); 329 } 330 331 static void imx_epit_reload(void *opaque) 332 { 333 /* No action required on rollover of timer_reload */ 334 } 335 336 static const MemoryRegionOps imx_epit_ops = { 337 .read = imx_epit_read, 338 .write = imx_epit_write, 339 .endianness = DEVICE_NATIVE_ENDIAN, 340 }; 341 342 static const VMStateDescription vmstate_imx_timer_epit = { 343 .name = TYPE_IMX_EPIT, 344 .version_id = 3, 345 .minimum_version_id = 3, 346 .fields = (VMStateField[]) { 347 VMSTATE_UINT32(cr, IMXEPITState), 348 VMSTATE_UINT32(sr, IMXEPITState), 349 VMSTATE_UINT32(lr, IMXEPITState), 350 VMSTATE_UINT32(cmp, IMXEPITState), 351 VMSTATE_PTIMER(timer_reload, IMXEPITState), 352 VMSTATE_PTIMER(timer_cmp, IMXEPITState), 353 VMSTATE_END_OF_LIST() 354 } 355 }; 356 357 static void imx_epit_realize(DeviceState *dev, Error **errp) 358 { 359 IMXEPITState *s = IMX_EPIT(dev); 360 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 361 362 DPRINTF("\n"); 363 364 sysbus_init_irq(sbd, &s->irq); 365 memory_region_init_io(&s->iomem, OBJECT(s), &imx_epit_ops, s, TYPE_IMX_EPIT, 366 0x00001000); 367 sysbus_init_mmio(sbd, &s->iomem); 368 369 /* 370 * The reload timer keeps running when the peripheral is enabled. It is a 371 * kind of wall clock that does not generate any interrupts. The callback 372 * needs to be provided, but it does nothing as the ptimer already supports 373 * all necessary reloading functionality. 374 */ 375 s->timer_reload = ptimer_init(imx_epit_reload, s, PTIMER_POLICY_LEGACY); 376 377 /* 378 * The compare timer is running only when the peripheral configuration is 379 * in a state that will generate compare interrupts. 380 */ 381 s->timer_cmp = ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_LEGACY); 382 } 383 384 static void imx_epit_dev_reset(DeviceState *dev) 385 { 386 IMXEPITState *s = IMX_EPIT(dev); 387 imx_epit_reset(s, true); 388 } 389 390 static void imx_epit_class_init(ObjectClass *klass, void *data) 391 { 392 DeviceClass *dc = DEVICE_CLASS(klass); 393 394 dc->realize = imx_epit_realize; 395 dc->reset = imx_epit_dev_reset; 396 dc->vmsd = &vmstate_imx_timer_epit; 397 dc->desc = "i.MX periodic timer"; 398 } 399 400 static const TypeInfo imx_epit_info = { 401 .name = TYPE_IMX_EPIT, 402 .parent = TYPE_SYS_BUS_DEVICE, 403 .instance_size = sizeof(IMXEPITState), 404 .class_init = imx_epit_class_init, 405 }; 406 407 static void imx_epit_register_types(void) 408 { 409 type_register_static(&imx_epit_info); 410 } 411 412 type_init(imx_epit_register_types) 413