1 /* 2 * IMX EPIT Timer 3 * 4 * Copyright (c) 2008 OK Labs 5 * Copyright (c) 2011 NICTA Pty Ltd 6 * Originally written by Hans Jiang 7 * Updated by Peter Chubb 8 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> 9 * 10 * This code is licensed under GPL version 2 or later. See 11 * the COPYING file in the top-level directory. 12 * 13 */ 14 15 #include "qemu/osdep.h" 16 #include "hw/timer/imx_epit.h" 17 #include "migration/vmstate.h" 18 #include "hw/irq.h" 19 #include "hw/misc/imx_ccm.h" 20 #include "qemu/module.h" 21 #include "qemu/log.h" 22 23 #ifndef DEBUG_IMX_EPIT 24 #define DEBUG_IMX_EPIT 0 25 #endif 26 27 #define DPRINTF(fmt, args...) \ 28 do { \ 29 if (DEBUG_IMX_EPIT) { \ 30 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_EPIT, \ 31 __func__, ##args); \ 32 } \ 33 } while (0) 34 35 static const char *imx_epit_reg_name(uint32_t reg) 36 { 37 switch (reg) { 38 case 0: 39 return "CR"; 40 case 1: 41 return "SR"; 42 case 2: 43 return "LR"; 44 case 3: 45 return "CMP"; 46 case 4: 47 return "CNT"; 48 default: 49 return "[?]"; 50 } 51 } 52 53 /* 54 * Exact clock frequencies vary from board to board. 55 * These are typical. 56 */ 57 static const IMXClk imx_epit_clocks[] = { 58 CLK_NONE, /* 00 disabled */ 59 CLK_IPG, /* 01 ipg_clk, ~532MHz */ 60 CLK_IPG_HIGH, /* 10 ipg_clk_highfreq */ 61 CLK_32k, /* 11 ipg_clk_32k -- ~32kHz */ 62 }; 63 64 /* 65 * Update interrupt status 66 */ 67 static void imx_epit_update_int(IMXEPITState *s) 68 { 69 if (s->sr && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) { 70 qemu_irq_raise(s->irq); 71 } else { 72 qemu_irq_lower(s->irq); 73 } 74 } 75 76 /* 77 * Must be called from within a ptimer_transaction_begin/commit block 78 * for both s->timer_cmp and s->timer_reload. 79 */ 80 static void imx_epit_set_freq(IMXEPITState *s) 81 { 82 uint32_t clksrc; 83 uint32_t prescaler; 84 85 clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, 2); 86 prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, 12); 87 88 s->freq = imx_ccm_get_clock_frequency(s->ccm, 89 imx_epit_clocks[clksrc]) / prescaler; 90 91 DPRINTF("Setting ptimer frequency to %u\n", s->freq); 92 93 if (s->freq) { 94 ptimer_set_freq(s->timer_reload, s->freq); 95 ptimer_set_freq(s->timer_cmp, s->freq); 96 } 97 } 98 99 /* 100 * This is called both on hardware (device) reset and software reset. 101 */ 102 static void imx_epit_reset(DeviceState *dev) 103 { 104 IMXEPITState *s = IMX_EPIT(dev); 105 106 /* Soft reset doesn't touch some bits; hard reset clears them */ 107 s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN); 108 s->sr = 0; 109 s->lr = EPIT_TIMER_MAX; 110 s->cmp = 0; 111 s->cnt = 0; 112 ptimer_transaction_begin(s->timer_cmp); 113 ptimer_transaction_begin(s->timer_reload); 114 /* stop both timers */ 115 ptimer_stop(s->timer_cmp); 116 ptimer_stop(s->timer_reload); 117 /* compute new frequency */ 118 imx_epit_set_freq(s); 119 /* init both timers to EPIT_TIMER_MAX */ 120 ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1); 121 ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1); 122 if (s->freq && (s->cr & CR_EN)) { 123 /* if the timer is still enabled, restart it */ 124 ptimer_run(s->timer_reload, 0); 125 } 126 ptimer_transaction_commit(s->timer_cmp); 127 ptimer_transaction_commit(s->timer_reload); 128 } 129 130 static uint32_t imx_epit_update_count(IMXEPITState *s) 131 { 132 s->cnt = ptimer_get_count(s->timer_reload); 133 134 return s->cnt; 135 } 136 137 static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size) 138 { 139 IMXEPITState *s = IMX_EPIT(opaque); 140 uint32_t reg_value = 0; 141 142 switch (offset >> 2) { 143 case 0: /* Control Register */ 144 reg_value = s->cr; 145 break; 146 147 case 1: /* Status Register */ 148 reg_value = s->sr; 149 break; 150 151 case 2: /* LR - ticks*/ 152 reg_value = s->lr; 153 break; 154 155 case 3: /* CMP */ 156 reg_value = s->cmp; 157 break; 158 159 case 4: /* CNT */ 160 imx_epit_update_count(s); 161 reg_value = s->cnt; 162 break; 163 164 default: 165 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 166 HWADDR_PRIx "\n", TYPE_IMX_EPIT, __func__, offset); 167 break; 168 } 169 170 DPRINTF("(%s) = 0x%08x\n", imx_epit_reg_name(offset >> 2), reg_value); 171 172 return reg_value; 173 } 174 175 /* Must be called from ptimer_transaction_begin/commit block for s->timer_cmp */ 176 static void imx_epit_reload_compare_timer(IMXEPITState *s) 177 { 178 if ((s->cr & (CR_EN | CR_OCIEN)) == (CR_EN | CR_OCIEN)) { 179 /* if the compare feature is on and timers are running */ 180 uint32_t tmp = imx_epit_update_count(s); 181 uint64_t next; 182 if (tmp > s->cmp) { 183 /* It'll fire in this round of the timer */ 184 next = tmp - s->cmp; 185 } else { /* catch it next time around */ 186 next = tmp - s->cmp + ((s->cr & CR_RLD) ? EPIT_TIMER_MAX : s->lr); 187 } 188 ptimer_set_count(s->timer_cmp, next); 189 } 190 } 191 192 static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, 193 unsigned size) 194 { 195 IMXEPITState *s = IMX_EPIT(opaque); 196 uint64_t oldcr; 197 198 DPRINTF("(%s, value = 0x%08x)\n", imx_epit_reg_name(offset >> 2), 199 (uint32_t)value); 200 201 switch (offset >> 2) { 202 case 0: /* CR */ 203 204 oldcr = s->cr; 205 s->cr = value & 0x03ffffff; 206 if (s->cr & CR_SWR) { 207 /* handle the reset */ 208 imx_epit_reset(DEVICE(s)); 209 /* 210 * TODO: could we 'break' here? following operations appear 211 * to duplicate the work imx_epit_reset() already did. 212 */ 213 } 214 215 ptimer_transaction_begin(s->timer_cmp); 216 ptimer_transaction_begin(s->timer_reload); 217 218 /* Update the frequency. Has been done already in case of a reset. */ 219 if (!(s->cr & CR_SWR)) { 220 imx_epit_set_freq(s); 221 } 222 223 if (s->freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) { 224 if (s->cr & CR_ENMOD) { 225 if (s->cr & CR_RLD) { 226 ptimer_set_limit(s->timer_reload, s->lr, 1); 227 ptimer_set_limit(s->timer_cmp, s->lr, 1); 228 } else { 229 ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1); 230 ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1); 231 } 232 } 233 234 imx_epit_reload_compare_timer(s); 235 ptimer_run(s->timer_reload, 0); 236 if (s->cr & CR_OCIEN) { 237 ptimer_run(s->timer_cmp, 0); 238 } else { 239 ptimer_stop(s->timer_cmp); 240 } 241 } else if (!(s->cr & CR_EN)) { 242 /* stop both timers */ 243 ptimer_stop(s->timer_reload); 244 ptimer_stop(s->timer_cmp); 245 } else if (s->cr & CR_OCIEN) { 246 if (!(oldcr & CR_OCIEN)) { 247 imx_epit_reload_compare_timer(s); 248 ptimer_run(s->timer_cmp, 0); 249 } 250 } else { 251 ptimer_stop(s->timer_cmp); 252 } 253 254 ptimer_transaction_commit(s->timer_cmp); 255 ptimer_transaction_commit(s->timer_reload); 256 break; 257 258 case 1: /* SR - ACK*/ 259 /* writing 1 to OCIF clears the OCIF bit */ 260 if (value & 0x01) { 261 s->sr = 0; 262 imx_epit_update_int(s); 263 } 264 break; 265 266 case 2: /* LR - set ticks */ 267 s->lr = value; 268 269 ptimer_transaction_begin(s->timer_cmp); 270 ptimer_transaction_begin(s->timer_reload); 271 if (s->cr & CR_RLD) { 272 /* Also set the limit if the LRD bit is set */ 273 /* If IOVW bit is set then set the timer value */ 274 ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW); 275 ptimer_set_limit(s->timer_cmp, s->lr, 0); 276 } else if (s->cr & CR_IOVW) { 277 /* If IOVW bit is set then set the timer value */ 278 ptimer_set_count(s->timer_reload, s->lr); 279 } 280 /* 281 * Commit the change to s->timer_reload, so it can propagate. Otherwise 282 * the timer interrupt may not fire properly. The commit must happen 283 * before calling imx_epit_reload_compare_timer(), which reads 284 * s->timer_reload internally again. 285 */ 286 ptimer_transaction_commit(s->timer_reload); 287 imx_epit_reload_compare_timer(s); 288 ptimer_transaction_commit(s->timer_cmp); 289 break; 290 291 case 3: /* CMP */ 292 s->cmp = value; 293 294 ptimer_transaction_begin(s->timer_cmp); 295 imx_epit_reload_compare_timer(s); 296 ptimer_transaction_commit(s->timer_cmp); 297 298 break; 299 300 default: 301 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" 302 HWADDR_PRIx "\n", TYPE_IMX_EPIT, __func__, offset); 303 304 break; 305 } 306 } 307 static void imx_epit_cmp(void *opaque) 308 { 309 IMXEPITState *s = IMX_EPIT(opaque); 310 311 DPRINTF("sr was %d\n", s->sr); 312 313 s->sr = 1; 314 imx_epit_update_int(s); 315 } 316 317 static void imx_epit_reload(void *opaque) 318 { 319 /* No action required on rollover of timer_reload */ 320 } 321 322 static const MemoryRegionOps imx_epit_ops = { 323 .read = imx_epit_read, 324 .write = imx_epit_write, 325 .endianness = DEVICE_NATIVE_ENDIAN, 326 }; 327 328 static const VMStateDescription vmstate_imx_timer_epit = { 329 .name = TYPE_IMX_EPIT, 330 .version_id = 2, 331 .minimum_version_id = 2, 332 .fields = (VMStateField[]) { 333 VMSTATE_UINT32(cr, IMXEPITState), 334 VMSTATE_UINT32(sr, IMXEPITState), 335 VMSTATE_UINT32(lr, IMXEPITState), 336 VMSTATE_UINT32(cmp, IMXEPITState), 337 VMSTATE_UINT32(cnt, IMXEPITState), 338 VMSTATE_UINT32(freq, IMXEPITState), 339 VMSTATE_PTIMER(timer_reload, IMXEPITState), 340 VMSTATE_PTIMER(timer_cmp, IMXEPITState), 341 VMSTATE_END_OF_LIST() 342 } 343 }; 344 345 static void imx_epit_realize(DeviceState *dev, Error **errp) 346 { 347 IMXEPITState *s = IMX_EPIT(dev); 348 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 349 350 DPRINTF("\n"); 351 352 sysbus_init_irq(sbd, &s->irq); 353 memory_region_init_io(&s->iomem, OBJECT(s), &imx_epit_ops, s, TYPE_IMX_EPIT, 354 0x00001000); 355 sysbus_init_mmio(sbd, &s->iomem); 356 357 /* 358 * The reload timer keeps running when the peripheral is enabled. It is a 359 * kind of wall clock that does not generate any interrupts. The callback 360 * needs to be provided, but it does nothing as the ptimer already supports 361 * all necessary reloading functionality. 362 */ 363 s->timer_reload = ptimer_init(imx_epit_reload, s, PTIMER_POLICY_LEGACY); 364 365 /* 366 * The compare timer is running only when the peripheral configuration is 367 * in a state that will generate compare interrupts. 368 */ 369 s->timer_cmp = ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_LEGACY); 370 } 371 372 static void imx_epit_class_init(ObjectClass *klass, void *data) 373 { 374 DeviceClass *dc = DEVICE_CLASS(klass); 375 376 dc->realize = imx_epit_realize; 377 dc->reset = imx_epit_reset; 378 dc->vmsd = &vmstate_imx_timer_epit; 379 dc->desc = "i.MX periodic timer"; 380 } 381 382 static const TypeInfo imx_epit_info = { 383 .name = TYPE_IMX_EPIT, 384 .parent = TYPE_SYS_BUS_DEVICE, 385 .instance_size = sizeof(IMXEPITState), 386 .class_init = imx_epit_class_init, 387 }; 388 389 static void imx_epit_register_types(void) 390 { 391 type_register_static(&imx_epit_info); 392 } 393 394 type_init(imx_epit_register_types) 395