1 /* 2 * QEMU lowRISC Ibex Timer device 3 * 4 * Copyright (c) 2021 Western Digital 5 * 6 * For details check the documentation here: 7 * https://docs.opentitan.org/hw/ip/rv_timer/doc/ 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a copy 10 * of this software and associated documentation files (the "Software"), to deal 11 * in the Software without restriction, including without limitation the rights 12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 13 * copies of the Software, and to permit persons to whom the Software is 14 * furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in 17 * all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 25 * THE SOFTWARE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qemu/log.h" 30 #include "qemu/timer.h" 31 #include "hw/timer/ibex_timer.h" 32 #include "hw/irq.h" 33 #include "hw/qdev-properties.h" 34 #include "target/riscv/cpu.h" 35 #include "migration/vmstate.h" 36 37 REG32(CTRL, 0x00) 38 FIELD(CTRL, ACTIVE, 0, 1) 39 REG32(CFG0, 0x100) 40 FIELD(CFG0, PRESCALE, 0, 12) 41 FIELD(CFG0, STEP, 16, 8) 42 REG32(LOWER0, 0x104) 43 REG32(UPPER0, 0x108) 44 REG32(COMPARE_LOWER0, 0x10C) 45 REG32(COMPARE_UPPER0, 0x110) 46 REG32(INTR_ENABLE, 0x114) 47 FIELD(INTR_ENABLE, IE_0, 0, 1) 48 REG32(INTR_STATE, 0x118) 49 FIELD(INTR_STATE, IS_0, 0, 1) 50 REG32(INTR_TEST, 0x11C) 51 FIELD(INTR_TEST, T_0, 0, 1) 52 53 static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq) 54 { 55 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 56 timebase_freq, NANOSECONDS_PER_SECOND); 57 } 58 59 static void ibex_timer_update_irqs(IbexTimerState *s) 60 { 61 CPUState *cs = qemu_get_cpu(0); 62 RISCVCPU *cpu = RISCV_CPU(cs); 63 uint64_t value = s->timer_compare_lower0 | 64 ((uint64_t)s->timer_compare_upper0 << 32); 65 uint64_t next, diff; 66 uint64_t now = cpu_riscv_read_rtc(s->timebase_freq); 67 68 if (!(s->timer_ctrl & R_CTRL_ACTIVE_MASK)) { 69 /* Timer isn't active */ 70 return; 71 } 72 73 /* Update the CPUs mtimecmp */ 74 cpu->env.timecmp = value; 75 76 if (cpu->env.timecmp <= now) { 77 /* 78 * If the mtimecmp was in the past raise the interrupt now. 79 */ 80 qemu_irq_raise(s->m_timer_irq); 81 if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) { 82 s->timer_intr_state |= R_INTR_STATE_IS_0_MASK; 83 qemu_set_irq(s->irq, true); 84 } 85 return; 86 } 87 88 /* Setup a timer to trigger the interrupt in the future */ 89 qemu_irq_lower(s->m_timer_irq); 90 qemu_set_irq(s->irq, false); 91 92 diff = cpu->env.timecmp - now; 93 next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 94 muldiv64(diff, 95 NANOSECONDS_PER_SECOND, 96 s->timebase_freq); 97 98 if (next < qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) { 99 /* We overflowed the timer, just set it as large as we can */ 100 timer_mod(cpu->env.timer, 0x7FFFFFFFFFFFFFFF); 101 } else { 102 timer_mod(cpu->env.timer, next); 103 } 104 } 105 106 static void ibex_timer_cb(void *opaque) 107 { 108 IbexTimerState *s = opaque; 109 110 qemu_irq_raise(s->m_timer_irq); 111 if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) { 112 s->timer_intr_state |= R_INTR_STATE_IS_0_MASK; 113 qemu_set_irq(s->irq, true); 114 } 115 } 116 117 static void ibex_timer_reset(DeviceState *dev) 118 { 119 IbexTimerState *s = IBEX_TIMER(dev); 120 121 CPUState *cpu = qemu_get_cpu(0); 122 CPURISCVState *env = cpu->env_ptr; 123 env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 124 &ibex_timer_cb, s); 125 env->timecmp = 0; 126 127 s->timer_ctrl = 0x00000000; 128 s->timer_cfg0 = 0x00010000; 129 s->timer_compare_lower0 = 0xFFFFFFFF; 130 s->timer_compare_upper0 = 0xFFFFFFFF; 131 s->timer_intr_enable = 0x00000000; 132 s->timer_intr_state = 0x00000000; 133 134 ibex_timer_update_irqs(s); 135 } 136 137 static uint64_t ibex_timer_read(void *opaque, hwaddr addr, 138 unsigned int size) 139 { 140 IbexTimerState *s = opaque; 141 uint64_t now = cpu_riscv_read_rtc(s->timebase_freq); 142 uint64_t retvalue = 0; 143 144 switch (addr >> 2) { 145 case R_CTRL: 146 retvalue = s->timer_ctrl; 147 break; 148 case R_CFG0: 149 retvalue = s->timer_cfg0; 150 break; 151 case R_LOWER0: 152 retvalue = now; 153 break; 154 case R_UPPER0: 155 retvalue = now >> 32; 156 break; 157 case R_COMPARE_LOWER0: 158 retvalue = s->timer_compare_lower0; 159 break; 160 case R_COMPARE_UPPER0: 161 retvalue = s->timer_compare_upper0; 162 break; 163 case R_INTR_ENABLE: 164 retvalue = s->timer_intr_enable; 165 break; 166 case R_INTR_STATE: 167 retvalue = s->timer_intr_state; 168 break; 169 case R_INTR_TEST: 170 qemu_log_mask(LOG_GUEST_ERROR, 171 "Attempted to read INTR_TEST, a write only register"); 172 break; 173 default: 174 qemu_log_mask(LOG_GUEST_ERROR, 175 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 176 return 0; 177 } 178 179 return retvalue; 180 } 181 182 static void ibex_timer_write(void *opaque, hwaddr addr, 183 uint64_t val64, unsigned int size) 184 { 185 IbexTimerState *s = opaque; 186 uint32_t val = val64; 187 188 switch (addr >> 2) { 189 case R_CTRL: 190 s->timer_ctrl = val; 191 break; 192 case R_CFG0: 193 qemu_log_mask(LOG_UNIMP, "Changing prescale or step not supported"); 194 s->timer_cfg0 = val; 195 break; 196 case R_LOWER0: 197 qemu_log_mask(LOG_UNIMP, "Changing timer value is not supported"); 198 break; 199 case R_UPPER0: 200 qemu_log_mask(LOG_UNIMP, "Changing timer value is not supported"); 201 break; 202 case R_COMPARE_LOWER0: 203 s->timer_compare_lower0 = val; 204 ibex_timer_update_irqs(s); 205 break; 206 case R_COMPARE_UPPER0: 207 s->timer_compare_upper0 = val; 208 ibex_timer_update_irqs(s); 209 break; 210 case R_INTR_ENABLE: 211 s->timer_intr_enable = val; 212 break; 213 case R_INTR_STATE: 214 /* Write 1 to clear */ 215 s->timer_intr_state &= ~val; 216 break; 217 case R_INTR_TEST: 218 if (s->timer_intr_enable & val & R_INTR_ENABLE_IE_0_MASK) { 219 s->timer_intr_state |= R_INTR_STATE_IS_0_MASK; 220 qemu_set_irq(s->irq, true); 221 } 222 break; 223 default: 224 qemu_log_mask(LOG_GUEST_ERROR, 225 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 226 } 227 } 228 229 static const MemoryRegionOps ibex_timer_ops = { 230 .read = ibex_timer_read, 231 .write = ibex_timer_write, 232 .endianness = DEVICE_NATIVE_ENDIAN, 233 .impl.min_access_size = 4, 234 .impl.max_access_size = 4, 235 }; 236 237 static int ibex_timer_post_load(void *opaque, int version_id) 238 { 239 IbexTimerState *s = opaque; 240 241 ibex_timer_update_irqs(s); 242 return 0; 243 } 244 245 static const VMStateDescription vmstate_ibex_timer = { 246 .name = TYPE_IBEX_TIMER, 247 .version_id = 2, 248 .minimum_version_id = 2, 249 .post_load = ibex_timer_post_load, 250 .fields = (VMStateField[]) { 251 VMSTATE_UINT32(timer_ctrl, IbexTimerState), 252 VMSTATE_UINT32(timer_cfg0, IbexTimerState), 253 VMSTATE_UINT32(timer_compare_lower0, IbexTimerState), 254 VMSTATE_UINT32(timer_compare_upper0, IbexTimerState), 255 VMSTATE_UINT32(timer_intr_enable, IbexTimerState), 256 VMSTATE_UINT32(timer_intr_state, IbexTimerState), 257 VMSTATE_END_OF_LIST() 258 } 259 }; 260 261 static Property ibex_timer_properties[] = { 262 DEFINE_PROP_UINT32("timebase-freq", IbexTimerState, timebase_freq, 10000), 263 DEFINE_PROP_END_OF_LIST(), 264 }; 265 266 static void ibex_timer_init(Object *obj) 267 { 268 IbexTimerState *s = IBEX_TIMER(obj); 269 270 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 271 272 memory_region_init_io(&s->mmio, obj, &ibex_timer_ops, s, 273 TYPE_IBEX_TIMER, 0x400); 274 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 275 } 276 277 static void ibex_timer_realize(DeviceState *dev, Error **errp) 278 { 279 IbexTimerState *s = IBEX_TIMER(dev); 280 281 qdev_init_gpio_out(dev, &s->m_timer_irq, 1); 282 } 283 284 285 static void ibex_timer_class_init(ObjectClass *klass, void *data) 286 { 287 DeviceClass *dc = DEVICE_CLASS(klass); 288 289 dc->reset = ibex_timer_reset; 290 dc->vmsd = &vmstate_ibex_timer; 291 dc->realize = ibex_timer_realize; 292 device_class_set_props(dc, ibex_timer_properties); 293 } 294 295 static const TypeInfo ibex_timer_info = { 296 .name = TYPE_IBEX_TIMER, 297 .parent = TYPE_SYS_BUS_DEVICE, 298 .instance_size = sizeof(IbexTimerState), 299 .instance_init = ibex_timer_init, 300 .class_init = ibex_timer_class_init, 301 }; 302 303 static void ibex_timer_register_types(void) 304 { 305 type_register_static(&ibex_timer_info); 306 } 307 308 type_init(ibex_timer_register_types) 309