1df41cbd6SAlistair Francis /* 2df41cbd6SAlistair Francis * QEMU lowRISC Ibex Timer device 3df41cbd6SAlistair Francis * 4df41cbd6SAlistair Francis * Copyright (c) 2021 Western Digital 5df41cbd6SAlistair Francis * 6df41cbd6SAlistair Francis * For details check the documentation here: 7df41cbd6SAlistair Francis * https://docs.opentitan.org/hw/ip/rv_timer/doc/ 8df41cbd6SAlistair Francis * 9df41cbd6SAlistair Francis * Permission is hereby granted, free of charge, to any person obtaining a copy 10df41cbd6SAlistair Francis * of this software and associated documentation files (the "Software"), to deal 11df41cbd6SAlistair Francis * in the Software without restriction, including without limitation the rights 12df41cbd6SAlistair Francis * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 13df41cbd6SAlistair Francis * copies of the Software, and to permit persons to whom the Software is 14df41cbd6SAlistair Francis * furnished to do so, subject to the following conditions: 15df41cbd6SAlistair Francis * 16df41cbd6SAlistair Francis * The above copyright notice and this permission notice shall be included in 17df41cbd6SAlistair Francis * all copies or substantial portions of the Software. 18df41cbd6SAlistair Francis * 19df41cbd6SAlistair Francis * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20df41cbd6SAlistair Francis * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21df41cbd6SAlistair Francis * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22df41cbd6SAlistair Francis * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23df41cbd6SAlistair Francis * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24df41cbd6SAlistair Francis * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 25df41cbd6SAlistair Francis * THE SOFTWARE. 26df41cbd6SAlistair Francis */ 27df41cbd6SAlistair Francis 28df41cbd6SAlistair Francis #include "qemu/osdep.h" 29df41cbd6SAlistair Francis #include "qemu/log.h" 30df41cbd6SAlistair Francis #include "qemu/timer.h" 31df41cbd6SAlistair Francis #include "hw/timer/ibex_timer.h" 32df41cbd6SAlistair Francis #include "hw/irq.h" 33df41cbd6SAlistair Francis #include "hw/qdev-properties.h" 34df41cbd6SAlistair Francis #include "target/riscv/cpu.h" 35df41cbd6SAlistair Francis #include "migration/vmstate.h" 36df41cbd6SAlistair Francis 37df41cbd6SAlistair Francis REG32(CTRL, 0x00) 38df41cbd6SAlistair Francis FIELD(CTRL, ACTIVE, 0, 1) 39df41cbd6SAlistair Francis REG32(CFG0, 0x100) 40df41cbd6SAlistair Francis FIELD(CFG0, PRESCALE, 0, 12) 41df41cbd6SAlistair Francis FIELD(CFG0, STEP, 16, 8) 42df41cbd6SAlistair Francis REG32(LOWER0, 0x104) 43df41cbd6SAlistair Francis REG32(UPPER0, 0x108) 44df41cbd6SAlistair Francis REG32(COMPARE_LOWER0, 0x10C) 45df41cbd6SAlistair Francis REG32(COMPARE_UPPER0, 0x110) 46df41cbd6SAlistair Francis REG32(INTR_ENABLE, 0x114) 47df41cbd6SAlistair Francis FIELD(INTR_ENABLE, IE_0, 0, 1) 48df41cbd6SAlistair Francis REG32(INTR_STATE, 0x118) 49df41cbd6SAlistair Francis FIELD(INTR_STATE, IS_0, 0, 1) 50df41cbd6SAlistair Francis REG32(INTR_TEST, 0x11C) 51df41cbd6SAlistair Francis FIELD(INTR_TEST, T_0, 0, 1) 52df41cbd6SAlistair Francis 53df41cbd6SAlistair Francis static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq) 54df41cbd6SAlistair Francis { 55df41cbd6SAlistair Francis return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 56df41cbd6SAlistair Francis timebase_freq, NANOSECONDS_PER_SECOND); 57df41cbd6SAlistair Francis } 58df41cbd6SAlistair Francis 59df41cbd6SAlistair Francis static void ibex_timer_update_irqs(IbexTimerState *s) 60df41cbd6SAlistair Francis { 61df41cbd6SAlistair Francis CPUState *cs = qemu_get_cpu(0); 62df41cbd6SAlistair Francis RISCVCPU *cpu = RISCV_CPU(cs); 63df41cbd6SAlistair Francis uint64_t value = s->timer_compare_lower0 | 64df41cbd6SAlistair Francis ((uint64_t)s->timer_compare_upper0 << 32); 65df41cbd6SAlistair Francis uint64_t next, diff; 66df41cbd6SAlistair Francis uint64_t now = cpu_riscv_read_rtc(s->timebase_freq); 67df41cbd6SAlistair Francis 68df41cbd6SAlistair Francis if (!(s->timer_ctrl & R_CTRL_ACTIVE_MASK)) { 69df41cbd6SAlistair Francis /* Timer isn't active */ 70df41cbd6SAlistair Francis return; 71df41cbd6SAlistair Francis } 72df41cbd6SAlistair Francis 73df41cbd6SAlistair Francis /* Update the CPUs mtimecmp */ 74df41cbd6SAlistair Francis cpu->env.timecmp = value; 75df41cbd6SAlistair Francis 76df41cbd6SAlistair Francis if (cpu->env.timecmp <= now) { 77df41cbd6SAlistair Francis /* 78df41cbd6SAlistair Francis * If the mtimecmp was in the past raise the interrupt now. 79df41cbd6SAlistair Francis */ 80*57a3a622SAlistair Francis qemu_irq_raise(s->m_timer_irq); 81df41cbd6SAlistair Francis if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) { 82df41cbd6SAlistair Francis s->timer_intr_state |= R_INTR_STATE_IS_0_MASK; 83df41cbd6SAlistair Francis qemu_set_irq(s->irq, true); 84df41cbd6SAlistair Francis } 85df41cbd6SAlistair Francis return; 86df41cbd6SAlistair Francis } 87df41cbd6SAlistair Francis 88df41cbd6SAlistair Francis /* Setup a timer to trigger the interrupt in the future */ 89*57a3a622SAlistair Francis qemu_irq_lower(s->m_timer_irq); 90df41cbd6SAlistair Francis qemu_set_irq(s->irq, false); 91df41cbd6SAlistair Francis 92df41cbd6SAlistair Francis diff = cpu->env.timecmp - now; 93df41cbd6SAlistair Francis next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 94df41cbd6SAlistair Francis muldiv64(diff, 95df41cbd6SAlistair Francis NANOSECONDS_PER_SECOND, 96df41cbd6SAlistair Francis s->timebase_freq); 97df41cbd6SAlistair Francis 98df41cbd6SAlistair Francis if (next < qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) { 99df41cbd6SAlistair Francis /* We overflowed the timer, just set it as large as we can */ 100df41cbd6SAlistair Francis timer_mod(cpu->env.timer, 0x7FFFFFFFFFFFFFFF); 101df41cbd6SAlistair Francis } else { 102df41cbd6SAlistair Francis timer_mod(cpu->env.timer, next); 103df41cbd6SAlistair Francis } 104df41cbd6SAlistair Francis } 105df41cbd6SAlistair Francis 106df41cbd6SAlistair Francis static void ibex_timer_cb(void *opaque) 107df41cbd6SAlistair Francis { 108df41cbd6SAlistair Francis IbexTimerState *s = opaque; 109df41cbd6SAlistair Francis 110*57a3a622SAlistair Francis qemu_irq_raise(s->m_timer_irq); 111df41cbd6SAlistair Francis if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) { 112df41cbd6SAlistair Francis s->timer_intr_state |= R_INTR_STATE_IS_0_MASK; 113df41cbd6SAlistair Francis qemu_set_irq(s->irq, true); 114df41cbd6SAlistair Francis } 115df41cbd6SAlistair Francis } 116df41cbd6SAlistair Francis 117df41cbd6SAlistair Francis static void ibex_timer_reset(DeviceState *dev) 118df41cbd6SAlistair Francis { 119df41cbd6SAlistair Francis IbexTimerState *s = IBEX_TIMER(dev); 120df41cbd6SAlistair Francis 121df41cbd6SAlistair Francis CPUState *cpu = qemu_get_cpu(0); 122df41cbd6SAlistair Francis CPURISCVState *env = cpu->env_ptr; 123df41cbd6SAlistair Francis env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 124df41cbd6SAlistair Francis &ibex_timer_cb, s); 125df41cbd6SAlistair Francis env->timecmp = 0; 126df41cbd6SAlistair Francis 127df41cbd6SAlistair Francis s->timer_ctrl = 0x00000000; 128df41cbd6SAlistair Francis s->timer_cfg0 = 0x00010000; 129df41cbd6SAlistair Francis s->timer_compare_lower0 = 0xFFFFFFFF; 130df41cbd6SAlistair Francis s->timer_compare_upper0 = 0xFFFFFFFF; 131df41cbd6SAlistair Francis s->timer_intr_enable = 0x00000000; 132df41cbd6SAlistair Francis s->timer_intr_state = 0x00000000; 133df41cbd6SAlistair Francis s->timer_intr_test = 0x00000000; 134df41cbd6SAlistair Francis 135df41cbd6SAlistair Francis ibex_timer_update_irqs(s); 136df41cbd6SAlistair Francis } 137df41cbd6SAlistair Francis 138df41cbd6SAlistair Francis static uint64_t ibex_timer_read(void *opaque, hwaddr addr, 139df41cbd6SAlistair Francis unsigned int size) 140df41cbd6SAlistair Francis { 141df41cbd6SAlistair Francis IbexTimerState *s = opaque; 142df41cbd6SAlistair Francis uint64_t now = cpu_riscv_read_rtc(s->timebase_freq); 143df41cbd6SAlistair Francis uint64_t retvalue = 0; 144df41cbd6SAlistair Francis 145df41cbd6SAlistair Francis switch (addr >> 2) { 146df41cbd6SAlistair Francis case R_CTRL: 147df41cbd6SAlistair Francis retvalue = s->timer_ctrl; 148df41cbd6SAlistair Francis break; 149df41cbd6SAlistair Francis case R_CFG0: 150df41cbd6SAlistair Francis retvalue = s->timer_cfg0; 151df41cbd6SAlistair Francis break; 152df41cbd6SAlistair Francis case R_LOWER0: 153df41cbd6SAlistair Francis retvalue = now; 154df41cbd6SAlistair Francis break; 155df41cbd6SAlistair Francis case R_UPPER0: 156df41cbd6SAlistair Francis retvalue = now >> 32; 157df41cbd6SAlistair Francis break; 158df41cbd6SAlistair Francis case R_COMPARE_LOWER0: 159df41cbd6SAlistair Francis retvalue = s->timer_compare_lower0; 160df41cbd6SAlistair Francis break; 161df41cbd6SAlistair Francis case R_COMPARE_UPPER0: 162df41cbd6SAlistair Francis retvalue = s->timer_compare_upper0; 163df41cbd6SAlistair Francis break; 164df41cbd6SAlistair Francis case R_INTR_ENABLE: 165df41cbd6SAlistair Francis retvalue = s->timer_intr_enable; 166df41cbd6SAlistair Francis break; 167df41cbd6SAlistair Francis case R_INTR_STATE: 168df41cbd6SAlistair Francis retvalue = s->timer_intr_state; 169df41cbd6SAlistair Francis break; 170df41cbd6SAlistair Francis case R_INTR_TEST: 171df41cbd6SAlistair Francis retvalue = s->timer_intr_test; 172df41cbd6SAlistair Francis break; 173df41cbd6SAlistair Francis default: 174df41cbd6SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, 175df41cbd6SAlistair Francis "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 176df41cbd6SAlistair Francis return 0; 177df41cbd6SAlistair Francis } 178df41cbd6SAlistair Francis 179df41cbd6SAlistair Francis return retvalue; 180df41cbd6SAlistair Francis } 181df41cbd6SAlistair Francis 182df41cbd6SAlistair Francis static void ibex_timer_write(void *opaque, hwaddr addr, 183df41cbd6SAlistair Francis uint64_t val64, unsigned int size) 184df41cbd6SAlistair Francis { 185df41cbd6SAlistair Francis IbexTimerState *s = opaque; 186df41cbd6SAlistair Francis uint32_t val = val64; 187df41cbd6SAlistair Francis 188df41cbd6SAlistair Francis switch (addr >> 2) { 189df41cbd6SAlistair Francis case R_CTRL: 190df41cbd6SAlistair Francis s->timer_ctrl = val; 191df41cbd6SAlistair Francis break; 192df41cbd6SAlistair Francis case R_CFG0: 193df41cbd6SAlistair Francis qemu_log_mask(LOG_UNIMP, "Changing prescale or step not supported"); 194df41cbd6SAlistair Francis s->timer_cfg0 = val; 195df41cbd6SAlistair Francis break; 196df41cbd6SAlistair Francis case R_LOWER0: 197df41cbd6SAlistair Francis qemu_log_mask(LOG_UNIMP, "Changing timer value is not supported"); 198df41cbd6SAlistair Francis break; 199df41cbd6SAlistair Francis case R_UPPER0: 200df41cbd6SAlistair Francis qemu_log_mask(LOG_UNIMP, "Changing timer value is not supported"); 201df41cbd6SAlistair Francis break; 202df41cbd6SAlistair Francis case R_COMPARE_LOWER0: 203df41cbd6SAlistair Francis s->timer_compare_lower0 = val; 204df41cbd6SAlistair Francis ibex_timer_update_irqs(s); 205df41cbd6SAlistair Francis break; 206df41cbd6SAlistair Francis case R_COMPARE_UPPER0: 207df41cbd6SAlistair Francis s->timer_compare_upper0 = val; 208df41cbd6SAlistair Francis ibex_timer_update_irqs(s); 209df41cbd6SAlistair Francis break; 210df41cbd6SAlistair Francis case R_INTR_ENABLE: 211df41cbd6SAlistair Francis s->timer_intr_enable = val; 212df41cbd6SAlistair Francis break; 213df41cbd6SAlistair Francis case R_INTR_STATE: 214df41cbd6SAlistair Francis /* Write 1 to clear */ 215df41cbd6SAlistair Francis s->timer_intr_state &= ~val; 216df41cbd6SAlistair Francis break; 217df41cbd6SAlistair Francis case R_INTR_TEST: 218df41cbd6SAlistair Francis s->timer_intr_test = val; 219df41cbd6SAlistair Francis if (s->timer_intr_enable & 220df41cbd6SAlistair Francis s->timer_intr_test & 221df41cbd6SAlistair Francis R_INTR_ENABLE_IE_0_MASK) { 222df41cbd6SAlistair Francis s->timer_intr_state |= R_INTR_STATE_IS_0_MASK; 223df41cbd6SAlistair Francis qemu_set_irq(s->irq, true); 224df41cbd6SAlistair Francis } 225df41cbd6SAlistair Francis break; 226df41cbd6SAlistair Francis default: 227df41cbd6SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, 228df41cbd6SAlistair Francis "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 229df41cbd6SAlistair Francis } 230df41cbd6SAlistair Francis } 231df41cbd6SAlistair Francis 232df41cbd6SAlistair Francis static const MemoryRegionOps ibex_timer_ops = { 233df41cbd6SAlistair Francis .read = ibex_timer_read, 234df41cbd6SAlistair Francis .write = ibex_timer_write, 235df41cbd6SAlistair Francis .endianness = DEVICE_NATIVE_ENDIAN, 236df41cbd6SAlistair Francis .impl.min_access_size = 4, 237df41cbd6SAlistair Francis .impl.max_access_size = 4, 238df41cbd6SAlistair Francis }; 239df41cbd6SAlistair Francis 240df41cbd6SAlistair Francis static int ibex_timer_post_load(void *opaque, int version_id) 241df41cbd6SAlistair Francis { 242df41cbd6SAlistair Francis IbexTimerState *s = opaque; 243df41cbd6SAlistair Francis 244df41cbd6SAlistair Francis ibex_timer_update_irqs(s); 245df41cbd6SAlistair Francis return 0; 246df41cbd6SAlistair Francis } 247df41cbd6SAlistair Francis 248df41cbd6SAlistair Francis static const VMStateDescription vmstate_ibex_timer = { 249df41cbd6SAlistair Francis .name = TYPE_IBEX_TIMER, 250df41cbd6SAlistair Francis .version_id = 1, 251df41cbd6SAlistair Francis .minimum_version_id = 1, 252df41cbd6SAlistair Francis .post_load = ibex_timer_post_load, 253df41cbd6SAlistair Francis .fields = (VMStateField[]) { 254df41cbd6SAlistair Francis VMSTATE_UINT32(timer_ctrl, IbexTimerState), 255df41cbd6SAlistair Francis VMSTATE_UINT32(timer_cfg0, IbexTimerState), 256df41cbd6SAlistair Francis VMSTATE_UINT32(timer_compare_lower0, IbexTimerState), 257df41cbd6SAlistair Francis VMSTATE_UINT32(timer_compare_upper0, IbexTimerState), 258df41cbd6SAlistair Francis VMSTATE_UINT32(timer_intr_enable, IbexTimerState), 259df41cbd6SAlistair Francis VMSTATE_UINT32(timer_intr_state, IbexTimerState), 260df41cbd6SAlistair Francis VMSTATE_UINT32(timer_intr_test, IbexTimerState), 261df41cbd6SAlistair Francis VMSTATE_END_OF_LIST() 262df41cbd6SAlistair Francis } 263df41cbd6SAlistair Francis }; 264df41cbd6SAlistair Francis 265df41cbd6SAlistair Francis static Property ibex_timer_properties[] = { 266df41cbd6SAlistair Francis DEFINE_PROP_UINT32("timebase-freq", IbexTimerState, timebase_freq, 10000), 267df41cbd6SAlistair Francis DEFINE_PROP_END_OF_LIST(), 268df41cbd6SAlistair Francis }; 269df41cbd6SAlistair Francis 270df41cbd6SAlistair Francis static void ibex_timer_init(Object *obj) 271df41cbd6SAlistair Francis { 272df41cbd6SAlistair Francis IbexTimerState *s = IBEX_TIMER(obj); 273df41cbd6SAlistair Francis 274df41cbd6SAlistair Francis sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 275df41cbd6SAlistair Francis 276df41cbd6SAlistair Francis memory_region_init_io(&s->mmio, obj, &ibex_timer_ops, s, 277df41cbd6SAlistair Francis TYPE_IBEX_TIMER, 0x400); 278df41cbd6SAlistair Francis sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 279df41cbd6SAlistair Francis } 280df41cbd6SAlistair Francis 281*57a3a622SAlistair Francis static void ibex_timer_realize(DeviceState *dev, Error **errp) 282*57a3a622SAlistair Francis { 283*57a3a622SAlistair Francis IbexTimerState *s = IBEX_TIMER(dev); 284*57a3a622SAlistair Francis 285*57a3a622SAlistair Francis qdev_init_gpio_out(dev, &s->m_timer_irq, 1); 286*57a3a622SAlistair Francis } 287*57a3a622SAlistair Francis 288*57a3a622SAlistair Francis 289df41cbd6SAlistair Francis static void ibex_timer_class_init(ObjectClass *klass, void *data) 290df41cbd6SAlistair Francis { 291df41cbd6SAlistair Francis DeviceClass *dc = DEVICE_CLASS(klass); 292df41cbd6SAlistair Francis 293df41cbd6SAlistair Francis dc->reset = ibex_timer_reset; 294df41cbd6SAlistair Francis dc->vmsd = &vmstate_ibex_timer; 295*57a3a622SAlistair Francis dc->realize = ibex_timer_realize; 296df41cbd6SAlistair Francis device_class_set_props(dc, ibex_timer_properties); 297df41cbd6SAlistair Francis } 298df41cbd6SAlistair Francis 299df41cbd6SAlistair Francis static const TypeInfo ibex_timer_info = { 300df41cbd6SAlistair Francis .name = TYPE_IBEX_TIMER, 301df41cbd6SAlistair Francis .parent = TYPE_SYS_BUS_DEVICE, 302df41cbd6SAlistair Francis .instance_size = sizeof(IbexTimerState), 303df41cbd6SAlistair Francis .instance_init = ibex_timer_init, 304df41cbd6SAlistair Francis .class_init = ibex_timer_class_init, 305df41cbd6SAlistair Francis }; 306df41cbd6SAlistair Francis 307df41cbd6SAlistair Francis static void ibex_timer_register_types(void) 308df41cbd6SAlistair Francis { 309df41cbd6SAlistair Francis type_register_static(&ibex_timer_info); 310df41cbd6SAlistair Francis } 311df41cbd6SAlistair Francis 312df41cbd6SAlistair Francis type_init(ibex_timer_register_types) 313