1 /* 2 * QEMU 8253/8254 - common bits of emulated and KVM kernel model 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2012 Jan Kiszka, Siemens AG 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/hw.h" 28 #include "hw/isa/isa.h" 29 #include "qemu/module.h" 30 #include "qemu/timer.h" 31 #include "hw/timer/i8254.h" 32 #include "hw/timer/i8254_internal.h" 33 #include "migration/qemu-file-types.h" 34 #include "migration/vmstate.h" 35 36 /* val must be 0 or 1 */ 37 void pit_set_gate(ISADevice *dev, int channel, int val) 38 { 39 PITCommonState *pit = PIT_COMMON(dev); 40 PITChannelState *s = &pit->channels[channel]; 41 PITCommonClass *c = PIT_COMMON_GET_CLASS(pit); 42 43 c->set_channel_gate(pit, s, val); 44 } 45 46 /* get pit output bit */ 47 int pit_get_out(PITChannelState *s, int64_t current_time) 48 { 49 uint64_t d; 50 int out; 51 52 d = muldiv64(current_time - s->count_load_time, PIT_FREQ, 53 NANOSECONDS_PER_SECOND); 54 switch (s->mode) { 55 default: 56 case 0: 57 out = (d >= s->count); 58 break; 59 case 1: 60 out = (d < s->count); 61 break; 62 case 2: 63 if ((d % s->count) == 0 && d != 0) { 64 out = 1; 65 } else { 66 out = 0; 67 } 68 break; 69 case 3: 70 out = (d % s->count) < ((s->count + 1) >> 1); 71 break; 72 case 4: 73 case 5: 74 out = (d == s->count); 75 break; 76 } 77 return out; 78 } 79 80 /* return -1 if no transition will occur. */ 81 int64_t pit_get_next_transition_time(PITChannelState *s, int64_t current_time) 82 { 83 uint64_t d, next_time, base; 84 int period2; 85 86 d = muldiv64(current_time - s->count_load_time, PIT_FREQ, 87 NANOSECONDS_PER_SECOND); 88 switch (s->mode) { 89 default: 90 case 0: 91 case 1: 92 if (d < s->count) { 93 next_time = s->count; 94 } else { 95 return -1; 96 } 97 break; 98 case 2: 99 base = QEMU_ALIGN_DOWN(d, s->count); 100 if ((d - base) == 0 && d != 0) { 101 next_time = base + s->count; 102 } else { 103 next_time = base + s->count + 1; 104 } 105 break; 106 case 3: 107 base = QEMU_ALIGN_DOWN(d, s->count); 108 period2 = ((s->count + 1) >> 1); 109 if ((d - base) < period2) { 110 next_time = base + period2; 111 } else { 112 next_time = base + s->count; 113 } 114 break; 115 case 4: 116 case 5: 117 if (d < s->count) { 118 next_time = s->count; 119 } else if (d == s->count) { 120 next_time = s->count + 1; 121 } else { 122 return -1; 123 } 124 break; 125 } 126 /* convert to timer units */ 127 next_time = s->count_load_time + muldiv64(next_time, NANOSECONDS_PER_SECOND, 128 PIT_FREQ); 129 /* fix potential rounding problems */ 130 /* XXX: better solution: use a clock at PIT_FREQ Hz */ 131 if (next_time <= current_time) { 132 next_time = current_time + 1; 133 } 134 return next_time; 135 } 136 137 void pit_get_channel_info_common(PITCommonState *s, PITChannelState *sc, 138 PITChannelInfo *info) 139 { 140 info->gate = sc->gate; 141 info->mode = sc->mode; 142 info->initial_count = sc->count; 143 info->out = pit_get_out(sc, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 144 } 145 146 void pit_get_channel_info(ISADevice *dev, int channel, PITChannelInfo *info) 147 { 148 PITCommonState *pit = PIT_COMMON(dev); 149 PITChannelState *s = &pit->channels[channel]; 150 PITCommonClass *c = PIT_COMMON_GET_CLASS(pit); 151 152 c->get_channel_info(pit, s, info); 153 } 154 155 void pit_reset_common(PITCommonState *pit) 156 { 157 PITChannelState *s; 158 int i; 159 160 for (i = 0; i < 3; i++) { 161 s = &pit->channels[i]; 162 s->mode = 3; 163 s->gate = (i != 2); 164 s->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 165 s->count = 0x10000; 166 if (i == 0 && !s->irq_disabled) { 167 s->next_transition_time = 168 pit_get_next_transition_time(s, s->count_load_time); 169 } 170 } 171 } 172 173 static void pit_common_realize(DeviceState *dev, Error **errp) 174 { 175 ISADevice *isadev = ISA_DEVICE(dev); 176 PITCommonState *pit = PIT_COMMON(dev); 177 178 isa_register_ioport(isadev, &pit->ioports, pit->iobase); 179 180 qdev_set_legacy_instance_id(dev, pit->iobase, 2); 181 } 182 183 static const VMStateDescription vmstate_pit_channel = { 184 .name = "pit channel", 185 .version_id = 2, 186 .minimum_version_id = 2, 187 .fields = (VMStateField[]) { 188 VMSTATE_INT32(count, PITChannelState), 189 VMSTATE_UINT16(latched_count, PITChannelState), 190 VMSTATE_UINT8(count_latched, PITChannelState), 191 VMSTATE_UINT8(status_latched, PITChannelState), 192 VMSTATE_UINT8(status, PITChannelState), 193 VMSTATE_UINT8(read_state, PITChannelState), 194 VMSTATE_UINT8(write_state, PITChannelState), 195 VMSTATE_UINT8(write_latch, PITChannelState), 196 VMSTATE_UINT8(rw_mode, PITChannelState), 197 VMSTATE_UINT8(mode, PITChannelState), 198 VMSTATE_UINT8(bcd, PITChannelState), 199 VMSTATE_UINT8(gate, PITChannelState), 200 VMSTATE_INT64(count_load_time, PITChannelState), 201 VMSTATE_INT64(next_transition_time, PITChannelState), 202 VMSTATE_END_OF_LIST() 203 } 204 }; 205 206 static int pit_load_old(QEMUFile *f, void *opaque, int version_id) 207 { 208 PITCommonState *pit = opaque; 209 PITCommonClass *c = PIT_COMMON_GET_CLASS(pit); 210 PITChannelState *s; 211 int i; 212 213 if (version_id != 1) { 214 return -EINVAL; 215 } 216 217 for (i = 0; i < 3; i++) { 218 s = &pit->channels[i]; 219 s->count = qemu_get_be32(f); 220 qemu_get_be16s(f, &s->latched_count); 221 qemu_get_8s(f, &s->count_latched); 222 qemu_get_8s(f, &s->status_latched); 223 qemu_get_8s(f, &s->status); 224 qemu_get_8s(f, &s->read_state); 225 qemu_get_8s(f, &s->write_state); 226 qemu_get_8s(f, &s->write_latch); 227 qemu_get_8s(f, &s->rw_mode); 228 qemu_get_8s(f, &s->mode); 229 qemu_get_8s(f, &s->bcd); 230 qemu_get_8s(f, &s->gate); 231 s->count_load_time = qemu_get_be64(f); 232 s->irq_disabled = 0; 233 if (i == 0) { 234 s->next_transition_time = qemu_get_be64(f); 235 } 236 } 237 if (c->post_load) { 238 c->post_load(pit); 239 } 240 return 0; 241 } 242 243 static int pit_dispatch_pre_save(void *opaque) 244 { 245 PITCommonState *s = opaque; 246 PITCommonClass *c = PIT_COMMON_GET_CLASS(s); 247 248 if (c->pre_save) { 249 c->pre_save(s); 250 } 251 252 return 0; 253 } 254 255 static int pit_dispatch_post_load(void *opaque, int version_id) 256 { 257 PITCommonState *s = opaque; 258 PITCommonClass *c = PIT_COMMON_GET_CLASS(s); 259 260 if (c->post_load) { 261 c->post_load(s); 262 } 263 return 0; 264 } 265 266 static const VMStateDescription vmstate_pit_common = { 267 .name = "i8254", 268 .version_id = 3, 269 .minimum_version_id = 2, 270 .minimum_version_id_old = 1, 271 .load_state_old = pit_load_old, 272 .pre_save = pit_dispatch_pre_save, 273 .post_load = pit_dispatch_post_load, 274 .fields = (VMStateField[]) { 275 VMSTATE_UINT32_V(channels[0].irq_disabled, PITCommonState, 3), 276 VMSTATE_STRUCT_ARRAY(channels, PITCommonState, 3, 2, 277 vmstate_pit_channel, PITChannelState), 278 VMSTATE_INT64(channels[0].next_transition_time, 279 PITCommonState), /* formerly irq_timer */ 280 VMSTATE_END_OF_LIST() 281 } 282 }; 283 284 static void pit_common_class_init(ObjectClass *klass, void *data) 285 { 286 DeviceClass *dc = DEVICE_CLASS(klass); 287 288 dc->realize = pit_common_realize; 289 dc->vmsd = &vmstate_pit_common; 290 /* 291 * Reason: unlike ordinary ISA devices, the PIT may need to be 292 * wired to the HPET, and because of that, some wiring is always 293 * done by board code. 294 */ 295 dc->user_creatable = false; 296 } 297 298 static const TypeInfo pit_common_type = { 299 .name = TYPE_PIT_COMMON, 300 .parent = TYPE_ISA_DEVICE, 301 .instance_size = sizeof(PITCommonState), 302 .class_size = sizeof(PITCommonClass), 303 .class_init = pit_common_class_init, 304 .abstract = true, 305 }; 306 307 static void register_devices(void) 308 { 309 type_register_static(&pit_common_type); 310 } 311 312 type_init(register_devices); 313