1 /* 2 * ASPEED AST2400 Timer 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright (C) 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "hw/irq.h" 15 #include "hw/sysbus.h" 16 #include "hw/timer/aspeed_timer.h" 17 #include "migration/vmstate.h" 18 #include "qemu/bitops.h" 19 #include "qemu/timer.h" 20 #include "qemu/log.h" 21 #include "qemu/module.h" 22 #include "hw/qdev-properties.h" 23 #include "trace.h" 24 25 #define TIMER_NR_REGS 4 26 27 #define TIMER_CTRL_BITS 4 28 #define TIMER_CTRL_MASK ((1 << TIMER_CTRL_BITS) - 1) 29 30 #define TIMER_CLOCK_USE_EXT true 31 #define TIMER_CLOCK_EXT_HZ 1000000 32 #define TIMER_CLOCK_USE_APB false 33 34 #define TIMER_REG_STATUS 0 35 #define TIMER_REG_RELOAD 1 36 #define TIMER_REG_MATCH_FIRST 2 37 #define TIMER_REG_MATCH_SECOND 3 38 39 #define TIMER_FIRST_CAP_PULSE 4 40 41 enum timer_ctrl_op { 42 op_enable = 0, 43 op_external_clock, 44 op_overflow_interrupt, 45 op_pulse_enable 46 }; 47 48 /* 49 * Minimum value of the reload register to filter out short period 50 * timers which have a noticeable impact in emulation. 5us should be 51 * enough, use 20us for "safety". 52 */ 53 #define TIMER_MIN_NS (20 * SCALE_US) 54 55 /** 56 * Avoid mutual references between AspeedTimerCtrlState and AspeedTimer 57 * structs, as it's a waste of memory. The ptimer BH callback needs to know 58 * whether a specific AspeedTimer is enabled, but this information is held in 59 * AspeedTimerCtrlState. So, provide a helper to hoist ourselves from an 60 * arbitrary AspeedTimer to AspeedTimerCtrlState. 61 */ 62 static inline AspeedTimerCtrlState *timer_to_ctrl(AspeedTimer *t) 63 { 64 const AspeedTimer (*timers)[] = (void *)t - (t->id * sizeof(*t)); 65 return container_of(timers, AspeedTimerCtrlState, timers); 66 } 67 68 static inline bool timer_ctrl_status(AspeedTimer *t, enum timer_ctrl_op op) 69 { 70 return !!(timer_to_ctrl(t)->ctrl & BIT(t->id * TIMER_CTRL_BITS + op)); 71 } 72 73 static inline bool timer_enabled(AspeedTimer *t) 74 { 75 return timer_ctrl_status(t, op_enable); 76 } 77 78 static inline bool timer_overflow_interrupt(AspeedTimer *t) 79 { 80 return timer_ctrl_status(t, op_overflow_interrupt); 81 } 82 83 static inline bool timer_can_pulse(AspeedTimer *t) 84 { 85 return t->id >= TIMER_FIRST_CAP_PULSE; 86 } 87 88 static inline bool timer_external_clock(AspeedTimer *t) 89 { 90 return timer_ctrl_status(t, op_external_clock); 91 } 92 93 static inline uint32_t calculate_rate(struct AspeedTimer *t) 94 { 95 AspeedTimerCtrlState *s = timer_to_ctrl(t); 96 97 return timer_external_clock(t) ? TIMER_CLOCK_EXT_HZ : 98 aspeed_scu_get_apb_freq(s->scu); 99 } 100 101 static inline uint32_t calculate_ticks(struct AspeedTimer *t, uint64_t now_ns) 102 { 103 uint64_t delta_ns = now_ns - MIN(now_ns, t->start); 104 uint32_t rate = calculate_rate(t); 105 uint64_t ticks = muldiv64(delta_ns, rate, NANOSECONDS_PER_SECOND); 106 107 return t->reload - MIN(t->reload, ticks); 108 } 109 110 static uint32_t calculate_min_ticks(AspeedTimer *t, uint32_t value) 111 { 112 uint32_t rate = calculate_rate(t); 113 uint32_t min_ticks = muldiv64(TIMER_MIN_NS, rate, NANOSECONDS_PER_SECOND); 114 115 return value < min_ticks ? min_ticks : value; 116 } 117 118 static inline uint64_t calculate_time(struct AspeedTimer *t, uint32_t ticks) 119 { 120 uint64_t delta_ns; 121 uint64_t delta_ticks; 122 123 delta_ticks = t->reload - MIN(t->reload, ticks); 124 delta_ns = muldiv64(delta_ticks, NANOSECONDS_PER_SECOND, calculate_rate(t)); 125 126 return t->start + delta_ns; 127 } 128 129 static inline uint32_t calculate_match(struct AspeedTimer *t, int i) 130 { 131 return t->match[i] < t->reload ? t->match[i] : 0; 132 } 133 134 static uint64_t calculate_next(struct AspeedTimer *t) 135 { 136 uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 137 uint64_t next; 138 139 /* 140 * We don't know the relationship between the values in the match 141 * registers, so sort using MAX/MIN/zero. We sort in that order as 142 * the timer counts down to zero. 143 */ 144 145 next = calculate_time(t, MAX(calculate_match(t, 0), calculate_match(t, 1))); 146 if (now < next) { 147 return next; 148 } 149 150 next = calculate_time(t, MIN(calculate_match(t, 0), calculate_match(t, 1))); 151 if (now < next) { 152 return next; 153 } 154 155 next = calculate_time(t, 0); 156 if (now < next) { 157 return next; 158 } 159 160 /* We've missed all deadlines, fire interrupt and try again */ 161 timer_del(&t->timer); 162 163 if (timer_overflow_interrupt(t)) { 164 AspeedTimerCtrlState *s = timer_to_ctrl(t); 165 t->level = !t->level; 166 s->irq_sts |= BIT(t->id); 167 qemu_set_irq(t->irq, t->level); 168 } 169 170 next = MAX(calculate_match(t, 0), calculate_match(t, 1)); 171 t->start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 172 173 return calculate_time(t, next); 174 } 175 176 static void aspeed_timer_mod(AspeedTimer *t) 177 { 178 uint64_t next = calculate_next(t); 179 if (next) { 180 timer_mod(&t->timer, next); 181 } 182 } 183 184 static void aspeed_timer_expire(void *opaque) 185 { 186 AspeedTimer *t = opaque; 187 bool interrupt = false; 188 uint32_t ticks; 189 190 if (!timer_enabled(t)) { 191 return; 192 } 193 194 ticks = calculate_ticks(t, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 195 196 if (!ticks) { 197 interrupt = timer_overflow_interrupt(t) || !t->match[0] || !t->match[1]; 198 } else if (ticks <= MIN(t->match[0], t->match[1])) { 199 interrupt = true; 200 } else if (ticks <= MAX(t->match[0], t->match[1])) { 201 interrupt = true; 202 } 203 204 if (interrupt) { 205 AspeedTimerCtrlState *s = timer_to_ctrl(t); 206 t->level = !t->level; 207 s->irq_sts |= BIT(t->id); 208 qemu_set_irq(t->irq, t->level); 209 } 210 211 aspeed_timer_mod(t); 212 } 213 214 static uint64_t aspeed_timer_get_value(AspeedTimer *t, int reg) 215 { 216 uint64_t value; 217 218 switch (reg) { 219 case TIMER_REG_STATUS: 220 if (timer_enabled(t)) { 221 value = calculate_ticks(t, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 222 } else { 223 value = t->reload; 224 } 225 break; 226 case TIMER_REG_RELOAD: 227 value = t->reload; 228 break; 229 case TIMER_REG_MATCH_FIRST: 230 case TIMER_REG_MATCH_SECOND: 231 value = t->match[reg - 2]; 232 break; 233 default: 234 qemu_log_mask(LOG_UNIMP, "%s: Programming error: unexpected reg: %d\n", 235 __func__, reg); 236 value = 0; 237 break; 238 } 239 return value; 240 } 241 242 static uint64_t aspeed_timer_read_common(AspeedTimerCtrlState *s, hwaddr offset) 243 { 244 const int reg = (offset & 0xf) / 4; 245 uint64_t value; 246 247 switch (offset) { 248 case 0x30: /* Control Register */ 249 value = s->ctrl; 250 break; 251 case 0x00 ... 0x2c: /* Timers 1 - 4 */ 252 value = aspeed_timer_get_value(&s->timers[(offset >> 4)], reg); 253 break; 254 case 0x40 ... 0x8c: /* Timers 5 - 8 */ 255 value = aspeed_timer_get_value(&s->timers[(offset >> 4) - 1], reg); 256 break; 257 default: 258 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 259 __func__, offset); 260 value = 0; 261 break; 262 } 263 return value; 264 } 265 266 static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg, 267 uint32_t value) 268 { 269 AspeedTimer *t; 270 uint32_t old_reload; 271 272 trace_aspeed_timer_set_value(timer, reg, value); 273 t = &s->timers[timer]; 274 switch (reg) { 275 case TIMER_REG_RELOAD: 276 old_reload = t->reload; 277 t->reload = calculate_min_ticks(t, value); 278 279 /* 280 * If the reload value was not previously set, or zero, and 281 * the current value is valid, try to start the timer if it is 282 * enabled. 283 */ 284 if (old_reload || !t->reload) { 285 break; 286 } 287 /* fall through to re-enable */ 288 case TIMER_REG_STATUS: 289 if (timer_enabled(t)) { 290 uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 291 int64_t delta = (int64_t) value - (int64_t) calculate_ticks(t, now); 292 uint32_t rate = calculate_rate(t); 293 294 if (delta >= 0) { 295 t->start += muldiv64(delta, NANOSECONDS_PER_SECOND, rate); 296 } else { 297 t->start -= muldiv64(-delta, NANOSECONDS_PER_SECOND, rate); 298 } 299 aspeed_timer_mod(t); 300 } 301 break; 302 case TIMER_REG_MATCH_FIRST: 303 case TIMER_REG_MATCH_SECOND: 304 t->match[reg - 2] = value; 305 if (timer_enabled(t)) { 306 aspeed_timer_mod(t); 307 } 308 break; 309 default: 310 qemu_log_mask(LOG_UNIMP, "%s: Programming error: unexpected reg: %d\n", 311 __func__, reg); 312 break; 313 } 314 } 315 316 /* 317 * Control register operations are broken out into helpers that can be 318 * explicitly called on aspeed_timer_reset(), but also from 319 * aspeed_timer_ctrl_op(). 320 */ 321 322 static void aspeed_timer_ctrl_enable(AspeedTimer *t, bool enable) 323 { 324 trace_aspeed_timer_ctrl_enable(t->id, enable); 325 if (enable) { 326 t->start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 327 aspeed_timer_mod(t); 328 } else { 329 timer_del(&t->timer); 330 } 331 } 332 333 static void aspeed_timer_ctrl_external_clock(AspeedTimer *t, bool enable) 334 { 335 trace_aspeed_timer_ctrl_external_clock(t->id, enable); 336 } 337 338 static void aspeed_timer_ctrl_overflow_interrupt(AspeedTimer *t, bool enable) 339 { 340 trace_aspeed_timer_ctrl_overflow_interrupt(t->id, enable); 341 } 342 343 static void aspeed_timer_ctrl_pulse_enable(AspeedTimer *t, bool enable) 344 { 345 if (timer_can_pulse(t)) { 346 trace_aspeed_timer_ctrl_pulse_enable(t->id, enable); 347 } else { 348 qemu_log_mask(LOG_GUEST_ERROR, 349 "%s: Timer does not support pulse mode\n", __func__); 350 } 351 } 352 353 /** 354 * Given the actions are fixed in number and completely described in helper 355 * functions, dispatch with a lookup table rather than manage control flow with 356 * a switch statement. 357 */ 358 static void (*const ctrl_ops[])(AspeedTimer *, bool) = { 359 [op_enable] = aspeed_timer_ctrl_enable, 360 [op_external_clock] = aspeed_timer_ctrl_external_clock, 361 [op_overflow_interrupt] = aspeed_timer_ctrl_overflow_interrupt, 362 [op_pulse_enable] = aspeed_timer_ctrl_pulse_enable, 363 }; 364 365 /** 366 * Conditionally affect changes chosen by a timer's control bit. 367 * 368 * The aspeed_timer_ctrl_op() interface is convenient for the 369 * aspeed_timer_set_ctrl() function as the "no change" early exit can be 370 * calculated for all operations, which cleans up the caller code. However the 371 * interface isn't convenient for the reset function where we want to enter a 372 * specific state without artificially constructing old and new values that 373 * will fall through the change guard (and motivates extracting the actions 374 * out to helper functions). 375 * 376 * @t: The timer to manipulate 377 * @op: The type of operation to be performed 378 * @old: The old state of the timer's control bits 379 * @new: The incoming state for the timer's control bits 380 */ 381 static void aspeed_timer_ctrl_op(AspeedTimer *t, enum timer_ctrl_op op, 382 uint8_t old, uint8_t new) 383 { 384 const uint8_t mask = BIT(op); 385 const bool enable = !!(new & mask); 386 const bool changed = ((old ^ new) & mask); 387 if (!changed) { 388 return; 389 } 390 ctrl_ops[op](t, enable); 391 } 392 393 static void aspeed_timer_set_ctrl(AspeedTimerCtrlState *s, uint32_t reg) 394 { 395 int i; 396 int shift; 397 uint8_t t_old, t_new; 398 AspeedTimer *t; 399 const uint8_t enable_mask = BIT(op_enable); 400 401 /* 402 * Handle a dependency between the 'enable' and remaining three 403 * configuration bits - i.e. if more than one bit in the control set has 404 * changed, including the 'enable' bit, then we want either disable the 405 * timer and perform configuration, or perform configuration and then 406 * enable the timer 407 */ 408 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 409 t = &s->timers[i]; 410 shift = (i * TIMER_CTRL_BITS); 411 t_old = (s->ctrl >> shift) & TIMER_CTRL_MASK; 412 t_new = (reg >> shift) & TIMER_CTRL_MASK; 413 414 /* If we are disabling, do so first */ 415 if ((t_old & enable_mask) && !(t_new & enable_mask)) { 416 aspeed_timer_ctrl_enable(t, false); 417 } 418 aspeed_timer_ctrl_op(t, op_external_clock, t_old, t_new); 419 aspeed_timer_ctrl_op(t, op_overflow_interrupt, t_old, t_new); 420 aspeed_timer_ctrl_op(t, op_pulse_enable, t_old, t_new); 421 /* If we are enabling, do so last */ 422 if (!(t_old & enable_mask) && (t_new & enable_mask)) { 423 aspeed_timer_ctrl_enable(t, true); 424 } 425 } 426 s->ctrl = reg; 427 } 428 429 static void aspeed_timer_set_ctrl2(AspeedTimerCtrlState *s, uint32_t value) 430 { 431 trace_aspeed_timer_set_ctrl2(value); 432 } 433 434 static void aspeed_timer_write_common(AspeedTimerCtrlState *s, hwaddr offset, 435 uint64_t value) 436 { 437 const uint32_t tv = (uint32_t)(value & 0xFFFFFFFF); 438 const int reg = (offset & 0xf) / 4; 439 440 switch (offset) { 441 /* Control Registers */ 442 case 0x30: 443 aspeed_timer_set_ctrl(s, tv); 444 break; 445 /* Timer Registers */ 446 case 0x00 ... 0x2c: 447 aspeed_timer_set_value(s, (offset >> TIMER_NR_REGS), reg, tv); 448 break; 449 case 0x40 ... 0x8c: 450 aspeed_timer_set_value(s, (offset >> TIMER_NR_REGS) - 1, reg, tv); 451 break; 452 default: 453 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 454 __func__, offset); 455 break; 456 } 457 } 458 459 static uint64_t aspeed_timer_read(void *opaque, hwaddr offset, unsigned size) 460 { 461 AspeedTimerCtrlState *s = ASPEED_TIMER(opaque); 462 return ASPEED_TIMER_GET_CLASS(s)->read(s, offset); 463 } 464 465 static void aspeed_timer_write(void *opaque, hwaddr offset, uint64_t value, 466 unsigned size) 467 { 468 AspeedTimerCtrlState *s = ASPEED_TIMER(opaque); 469 ASPEED_TIMER_GET_CLASS(s)->write(s, offset, value); 470 } 471 472 static const MemoryRegionOps aspeed_timer_ops = { 473 .read = aspeed_timer_read, 474 .write = aspeed_timer_write, 475 .endianness = DEVICE_LITTLE_ENDIAN, 476 .valid.min_access_size = 4, 477 .valid.max_access_size = 4, 478 .valid.unaligned = false, 479 }; 480 481 static uint64_t aspeed_2400_timer_read(AspeedTimerCtrlState *s, hwaddr offset) 482 { 483 uint64_t value; 484 485 switch (offset) { 486 case 0x34: 487 value = s->ctrl2; 488 break; 489 case 0x38: 490 case 0x3C: 491 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 492 __func__, offset); 493 value = 0; 494 break; 495 default: 496 value = aspeed_timer_read_common(s, offset); 497 break; 498 } 499 trace_aspeed_timer_read(offset, value); 500 return value; 501 } 502 503 static void aspeed_2400_timer_write(AspeedTimerCtrlState *s, hwaddr offset, 504 uint64_t value) 505 { 506 const uint32_t tv = (uint32_t)(value & 0xFFFFFFFF); 507 508 switch (offset) { 509 case 0x34: 510 aspeed_timer_set_ctrl2(s, tv); 511 break; 512 case 0x38: 513 case 0x3C: 514 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 515 __func__, offset); 516 break; 517 default: 518 aspeed_timer_write_common(s, offset, value); 519 break; 520 } 521 } 522 523 static uint64_t aspeed_2500_timer_read(AspeedTimerCtrlState *s, hwaddr offset) 524 { 525 uint64_t value; 526 527 switch (offset) { 528 case 0x34: 529 value = s->ctrl2; 530 break; 531 case 0x38: 532 value = s->ctrl3 & BIT(0); 533 break; 534 case 0x3C: 535 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 536 __func__, offset); 537 value = 0; 538 break; 539 default: 540 value = aspeed_timer_read_common(s, offset); 541 break; 542 } 543 trace_aspeed_timer_read(offset, value); 544 return value; 545 } 546 547 static void aspeed_2500_timer_write(AspeedTimerCtrlState *s, hwaddr offset, 548 uint64_t value) 549 { 550 const uint32_t tv = (uint32_t)(value & 0xFFFFFFFF); 551 uint8_t command; 552 553 switch (offset) { 554 case 0x34: 555 aspeed_timer_set_ctrl2(s, tv); 556 break; 557 case 0x38: 558 command = (value >> 1) & 0xFF; 559 if (command == 0xAE) { 560 s->ctrl3 = 0x1; 561 } else if (command == 0xEA) { 562 s->ctrl3 = 0x0; 563 } 564 break; 565 case 0x3C: 566 if (s->ctrl3 & BIT(0)) { 567 aspeed_timer_set_ctrl(s, s->ctrl & ~tv); 568 } 569 break; 570 571 default: 572 aspeed_timer_write_common(s, offset, value); 573 break; 574 } 575 } 576 577 static uint64_t aspeed_2600_timer_read(AspeedTimerCtrlState *s, hwaddr offset) 578 { 579 uint64_t value; 580 581 switch (offset) { 582 case 0x34: 583 value = s->irq_sts; 584 break; 585 case 0x38: 586 case 0x3C: 587 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 588 __func__, offset); 589 value = 0; 590 break; 591 default: 592 value = aspeed_timer_read_common(s, offset); 593 break; 594 } 595 trace_aspeed_timer_read(offset, value); 596 return value; 597 } 598 599 static void aspeed_2600_timer_write(AspeedTimerCtrlState *s, hwaddr offset, 600 uint64_t value) 601 { 602 const uint32_t tv = (uint32_t)(value & 0xFFFFFFFF); 603 604 switch (offset) { 605 case 0x34: 606 s->irq_sts &= ~tv; 607 break; 608 case 0x3C: 609 aspeed_timer_set_ctrl(s, s->ctrl & ~tv); 610 break; 611 case 0x38: 612 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 613 __func__, offset); 614 break; 615 default: 616 aspeed_timer_write_common(s, offset, value); 617 break; 618 } 619 } 620 621 static void aspeed_2700_timer_set_ctrl(AspeedTimerCtrlState *s, int index, 622 uint32_t reg) 623 { 624 const uint8_t overflow_interrupt_mask = BIT(op_overflow_interrupt); 625 const uint8_t external_clock_mask = BIT(op_external_clock); 626 const uint8_t pulse_enable_mask = BIT(op_pulse_enable); 627 const uint8_t enable_mask = BIT(op_enable); 628 AspeedTimer *t; 629 uint8_t t_old; 630 uint8_t t_new; 631 int shift; 632 633 /* 634 * Only 1 will set the specific bits to 1 635 * Handle a dependency between the 'enable' and remaining three 636 * configuration bits - i.e. if more than one bit in the control set has 637 * set, including the 'enable' bit, perform configuration and then 638 * enable the timer. 639 * Interrupt Status bit should not be set. 640 */ 641 642 t = &s->timers[index]; 643 shift = index * TIMER_CTRL_BITS; 644 645 t_old = (s->ctrl >> shift) & TIMER_CTRL_MASK; 646 t_new = reg & TIMER_CTRL_MASK; 647 648 if (!(t_old & external_clock_mask) && 649 (t_new & external_clock_mask)) { 650 aspeed_timer_ctrl_external_clock(t, true); 651 s->ctrl = deposit32(s->ctrl, shift + op_external_clock, 1, 1); 652 } 653 654 if (!(t_old & overflow_interrupt_mask) && 655 (t_new & overflow_interrupt_mask)) { 656 aspeed_timer_ctrl_overflow_interrupt(t, true); 657 s->ctrl = deposit32(s->ctrl, shift + op_overflow_interrupt, 1, 1); 658 } 659 660 661 if (!(t_old & pulse_enable_mask) && 662 (t_new & pulse_enable_mask)) { 663 aspeed_timer_ctrl_pulse_enable(t, true); 664 s->ctrl = deposit32(s->ctrl, shift + op_pulse_enable, 1, 1); 665 } 666 667 /* If we are enabling, do so last */ 668 if (!(t_old & enable_mask) && 669 (t_new & enable_mask)) { 670 aspeed_timer_ctrl_enable(t, true); 671 s->ctrl = deposit32(s->ctrl, shift + op_enable, 1, 1); 672 } 673 } 674 675 static void aspeed_2700_timer_clear_ctrl(AspeedTimerCtrlState *s, int index, 676 uint32_t reg) 677 { 678 const uint8_t overflow_interrupt_mask = BIT(op_overflow_interrupt); 679 const uint8_t external_clock_mask = BIT(op_external_clock); 680 const uint8_t pulse_enable_mask = BIT(op_pulse_enable); 681 const uint8_t enable_mask = BIT(op_enable); 682 AspeedTimer *t; 683 uint8_t t_old; 684 uint8_t t_new; 685 int shift; 686 687 /* 688 * Only 1 will clear the specific bits to 0 689 * Handle a dependency between the 'enable' and remaining three 690 * configuration bits - i.e. if more than one bit in the control set has 691 * clear, including the 'enable' bit, then disable the timer and perform 692 * configuration 693 */ 694 695 t = &s->timers[index]; 696 shift = index * TIMER_CTRL_BITS; 697 698 t_old = (s->ctrl >> shift) & TIMER_CTRL_MASK; 699 t_new = reg & TIMER_CTRL_MASK; 700 701 /* If we are disabling, do so first */ 702 if ((t_old & enable_mask) && 703 (t_new & enable_mask)) { 704 aspeed_timer_ctrl_enable(t, false); 705 s->ctrl = deposit32(s->ctrl, shift + op_enable, 1, 0); 706 } 707 708 if ((t_old & external_clock_mask) && 709 (t_new & external_clock_mask)) { 710 aspeed_timer_ctrl_external_clock(t, false); 711 s->ctrl = deposit32(s->ctrl, shift + op_external_clock, 1, 0); 712 } 713 714 if ((t_old & overflow_interrupt_mask) && 715 (t_new & overflow_interrupt_mask)) { 716 aspeed_timer_ctrl_overflow_interrupt(t, false); 717 s->ctrl = deposit32(s->ctrl, shift + op_overflow_interrupt, 1, 0); 718 } 719 720 if ((t_old & pulse_enable_mask) && 721 (t_new & pulse_enable_mask)) { 722 aspeed_timer_ctrl_pulse_enable(t, false); 723 s->ctrl = deposit32(s->ctrl, shift + op_pulse_enable, 1, 0); 724 } 725 726 /* Clear interrupt status */ 727 if (reg & 0x10000) { 728 s->irq_sts = deposit32(s->irq_sts, index, 1, 0); 729 } 730 } 731 732 static uint64_t aspeed_2700_timer_read(AspeedTimerCtrlState *s, hwaddr offset) 733 { 734 uint32_t timer_offset = offset & 0x3f; 735 int timer_index = offset >> 6; 736 uint64_t value = 0; 737 738 if (timer_index >= ASPEED_TIMER_NR_TIMERS) { 739 qemu_log_mask(LOG_GUEST_ERROR, 740 "%s: offset 0x%" PRIx64 " out of bounds\n", 741 __func__, offset); 742 return 0; 743 } 744 745 switch (timer_offset) { 746 /* 747 * Counter Status 748 * Counter Reload 749 * Counter First Matching 750 * Counter Second Matching 751 */ 752 case 0x00 ... 0x0C: 753 value = aspeed_timer_get_value(&s->timers[timer_index], 754 timer_offset >> 2); 755 break; 756 /* Counter Control and Interrupt Status */ 757 case 0x10: 758 value = deposit64(value, 0, 4, 759 extract32(s->ctrl, timer_index * 4, 4)); 760 value = deposit64(value, 16, 1, 761 extract32(s->irq_sts, timer_index, 1)); 762 break; 763 default: 764 qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" 765 PRIx64"\n", __func__, offset); 766 value = 0; 767 break; 768 } 769 trace_aspeed_timer_read(offset, value); 770 return value; 771 } 772 773 static void aspeed_2700_timer_write(AspeedTimerCtrlState *s, hwaddr offset, 774 uint64_t value) 775 { 776 const uint32_t timer_value = (uint32_t)(value & 0xFFFFFFFF); 777 uint32_t timer_offset = offset & 0x3f; 778 int timer_index = offset >> 6; 779 780 if (timer_index >= ASPEED_TIMER_NR_TIMERS) { 781 qemu_log_mask(LOG_GUEST_ERROR, 782 "%s: offset 0x%" PRIx64 " out of bounds\n", 783 __func__, offset); 784 } 785 786 switch (timer_offset) { 787 /* 788 * Counter Status 789 * Counter Reload 790 * Counter First Matching 791 * Counter Second Matching 792 */ 793 case 0x00 ... 0x0C: 794 aspeed_timer_set_value(s, timer_index, timer_offset >> 2, 795 timer_value); 796 break; 797 /* Counter Control Set and Interrupt Status */ 798 case 0x10: 799 aspeed_2700_timer_set_ctrl(s, timer_index, timer_value); 800 break; 801 /* Counter Control Clear and Interrupr Status */ 802 case 0x14: 803 aspeed_2700_timer_clear_ctrl(s, timer_index, timer_value); 804 break; 805 default: 806 qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" 807 PRIx64"\n", __func__, offset); 808 break; 809 } 810 } 811 812 static void aspeed_init_one_timer(AspeedTimerCtrlState *s, uint8_t id) 813 { 814 AspeedTimer *t = &s->timers[id]; 815 816 t->id = id; 817 timer_init_ns(&t->timer, QEMU_CLOCK_VIRTUAL, aspeed_timer_expire, t); 818 } 819 820 static void aspeed_timer_realize(DeviceState *dev, Error **errp) 821 { 822 int i; 823 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 824 AspeedTimerCtrlState *s = ASPEED_TIMER(dev); 825 826 assert(s->scu); 827 828 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 829 aspeed_init_one_timer(s, i); 830 sysbus_init_irq(sbd, &s->timers[i].irq); 831 } 832 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_timer_ops, s, 833 TYPE_ASPEED_TIMER, 0x1000); 834 sysbus_init_mmio(sbd, &s->iomem); 835 } 836 837 static void aspeed_timer_reset(DeviceState *dev) 838 { 839 int i; 840 AspeedTimerCtrlState *s = ASPEED_TIMER(dev); 841 842 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { 843 AspeedTimer *t = &s->timers[i]; 844 /* 845 * Explicitly call helpers to avoid any conditional behaviour through 846 * aspeed_timer_set_ctrl(). 847 */ 848 aspeed_timer_ctrl_enable(t, false); 849 aspeed_timer_ctrl_external_clock(t, TIMER_CLOCK_USE_APB); 850 aspeed_timer_ctrl_overflow_interrupt(t, false); 851 aspeed_timer_ctrl_pulse_enable(t, false); 852 t->level = 0; 853 t->reload = 0; 854 t->match[0] = 0; 855 t->match[1] = 0; 856 } 857 s->ctrl = 0; 858 s->ctrl2 = 0; 859 s->ctrl3 = 0; 860 s->irq_sts = 0; 861 } 862 863 static const VMStateDescription vmstate_aspeed_timer = { 864 .name = "aspeed.timer", 865 .version_id = 2, 866 .minimum_version_id = 2, 867 .fields = (const VMStateField[]) { 868 VMSTATE_UINT8(id, AspeedTimer), 869 VMSTATE_INT32(level, AspeedTimer), 870 VMSTATE_TIMER(timer, AspeedTimer), 871 VMSTATE_UINT32(reload, AspeedTimer), 872 VMSTATE_UINT32_ARRAY(match, AspeedTimer, 2), 873 VMSTATE_END_OF_LIST() 874 } 875 }; 876 877 static const VMStateDescription vmstate_aspeed_timer_state = { 878 .name = "aspeed.timerctrl", 879 .version_id = 2, 880 .minimum_version_id = 2, 881 .fields = (const VMStateField[]) { 882 VMSTATE_UINT32(ctrl, AspeedTimerCtrlState), 883 VMSTATE_UINT32(ctrl2, AspeedTimerCtrlState), 884 VMSTATE_UINT32(ctrl3, AspeedTimerCtrlState), 885 VMSTATE_UINT32(irq_sts, AspeedTimerCtrlState), 886 VMSTATE_STRUCT_ARRAY(timers, AspeedTimerCtrlState, 887 ASPEED_TIMER_NR_TIMERS, 1, vmstate_aspeed_timer, 888 AspeedTimer), 889 VMSTATE_END_OF_LIST() 890 } 891 }; 892 893 static const Property aspeed_timer_properties[] = { 894 DEFINE_PROP_LINK("scu", AspeedTimerCtrlState, scu, TYPE_ASPEED_SCU, 895 AspeedSCUState *), 896 }; 897 898 static void timer_class_init(ObjectClass *klass, void *data) 899 { 900 DeviceClass *dc = DEVICE_CLASS(klass); 901 902 dc->realize = aspeed_timer_realize; 903 device_class_set_legacy_reset(dc, aspeed_timer_reset); 904 dc->desc = "ASPEED Timer"; 905 dc->vmsd = &vmstate_aspeed_timer_state; 906 device_class_set_props(dc, aspeed_timer_properties); 907 } 908 909 static const TypeInfo aspeed_timer_info = { 910 .name = TYPE_ASPEED_TIMER, 911 .parent = TYPE_SYS_BUS_DEVICE, 912 .instance_size = sizeof(AspeedTimerCtrlState), 913 .class_init = timer_class_init, 914 .class_size = sizeof(AspeedTimerClass), 915 .abstract = true, 916 }; 917 918 static void aspeed_2400_timer_class_init(ObjectClass *klass, void *data) 919 { 920 DeviceClass *dc = DEVICE_CLASS(klass); 921 AspeedTimerClass *awc = ASPEED_TIMER_CLASS(klass); 922 923 dc->desc = "ASPEED 2400 Timer"; 924 awc->read = aspeed_2400_timer_read; 925 awc->write = aspeed_2400_timer_write; 926 } 927 928 static const TypeInfo aspeed_2400_timer_info = { 929 .name = TYPE_ASPEED_2400_TIMER, 930 .parent = TYPE_ASPEED_TIMER, 931 .class_init = aspeed_2400_timer_class_init, 932 }; 933 934 static void aspeed_2500_timer_class_init(ObjectClass *klass, void *data) 935 { 936 DeviceClass *dc = DEVICE_CLASS(klass); 937 AspeedTimerClass *awc = ASPEED_TIMER_CLASS(klass); 938 939 dc->desc = "ASPEED 2500 Timer"; 940 awc->read = aspeed_2500_timer_read; 941 awc->write = aspeed_2500_timer_write; 942 } 943 944 static const TypeInfo aspeed_2500_timer_info = { 945 .name = TYPE_ASPEED_2500_TIMER, 946 .parent = TYPE_ASPEED_TIMER, 947 .class_init = aspeed_2500_timer_class_init, 948 }; 949 950 static void aspeed_2600_timer_class_init(ObjectClass *klass, void *data) 951 { 952 DeviceClass *dc = DEVICE_CLASS(klass); 953 AspeedTimerClass *awc = ASPEED_TIMER_CLASS(klass); 954 955 dc->desc = "ASPEED 2600 Timer"; 956 awc->read = aspeed_2600_timer_read; 957 awc->write = aspeed_2600_timer_write; 958 } 959 960 static const TypeInfo aspeed_2600_timer_info = { 961 .name = TYPE_ASPEED_2600_TIMER, 962 .parent = TYPE_ASPEED_TIMER, 963 .class_init = aspeed_2600_timer_class_init, 964 }; 965 966 static void aspeed_1030_timer_class_init(ObjectClass *klass, void *data) 967 { 968 DeviceClass *dc = DEVICE_CLASS(klass); 969 AspeedTimerClass *awc = ASPEED_TIMER_CLASS(klass); 970 971 dc->desc = "ASPEED 1030 Timer"; 972 awc->read = aspeed_2600_timer_read; 973 awc->write = aspeed_2600_timer_write; 974 } 975 976 static const TypeInfo aspeed_1030_timer_info = { 977 .name = TYPE_ASPEED_1030_TIMER, 978 .parent = TYPE_ASPEED_TIMER, 979 .class_init = aspeed_1030_timer_class_init, 980 }; 981 982 static void aspeed_2700_timer_class_init(ObjectClass *klass, void *data) 983 { 984 DeviceClass *dc = DEVICE_CLASS(klass); 985 AspeedTimerClass *awc = ASPEED_TIMER_CLASS(klass); 986 987 dc->desc = "ASPEED 2700 Timer"; 988 awc->read = aspeed_2700_timer_read; 989 awc->write = aspeed_2700_timer_write; 990 } 991 992 static const TypeInfo aspeed_2700_timer_info = { 993 .name = TYPE_ASPEED_2700_TIMER, 994 .parent = TYPE_ASPEED_TIMER, 995 .class_init = aspeed_2700_timer_class_init, 996 }; 997 998 static void aspeed_timer_register_types(void) 999 { 1000 type_register_static(&aspeed_timer_info); 1001 type_register_static(&aspeed_2400_timer_info); 1002 type_register_static(&aspeed_2500_timer_info); 1003 type_register_static(&aspeed_2600_timer_info); 1004 type_register_static(&aspeed_1030_timer_info); 1005 type_register_static(&aspeed_2700_timer_info); 1006 } 1007 1008 type_init(aspeed_timer_register_types) 1009