1 /* 2 * Allwinner A10 timer device emulation 3 * 4 * Copyright (C) 2013 Li Guang 5 * Written by Li Guang <lig.fnst@cn.fujitsu.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "hw/irq.h" 20 #include "hw/qdev-properties.h" 21 #include "hw/sysbus.h" 22 #include "sysemu/sysemu.h" 23 #include "hw/timer/allwinner-a10-pit.h" 24 #include "migration/vmstate.h" 25 #include "qemu/log.h" 26 #include "qemu/main-loop.h" 27 #include "qemu/module.h" 28 29 static void a10_pit_update_irq(AwA10PITState *s) 30 { 31 int i; 32 33 for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { 34 qemu_set_irq(s->irq[i], !!(s->irq_status & s->irq_enable & (1 << i))); 35 } 36 } 37 38 static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) 39 { 40 AwA10PITState *s = AW_A10_PIT(opaque); 41 uint8_t index; 42 43 switch (offset) { 44 case AW_A10_PIT_TIMER_IRQ_EN: 45 return s->irq_enable; 46 case AW_A10_PIT_TIMER_IRQ_ST: 47 return s->irq_status; 48 case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END: 49 index = offset & 0xf0; 50 index >>= 4; 51 index -= 1; 52 switch (offset & 0x0f) { 53 case AW_A10_PIT_TIMER_CONTROL: 54 return s->control[index]; 55 case AW_A10_PIT_TIMER_INTERVAL: 56 return s->interval[index]; 57 case AW_A10_PIT_TIMER_COUNT: 58 s->count[index] = ptimer_get_count(s->timer[index]); 59 return s->count[index]; 60 default: 61 qemu_log_mask(LOG_GUEST_ERROR, 62 "%s: Bad offset 0x%x\n", __func__, (int)offset); 63 break; 64 } 65 case AW_A10_PIT_WDOG_CONTROL: 66 break; 67 case AW_A10_PIT_WDOG_MODE: 68 break; 69 case AW_A10_PIT_COUNT_LO: 70 return s->count_lo; 71 case AW_A10_PIT_COUNT_HI: 72 return s->count_hi; 73 case AW_A10_PIT_COUNT_CTL: 74 return s->count_ctl; 75 default: 76 qemu_log_mask(LOG_GUEST_ERROR, 77 "%s: Bad offset 0x%x\n", __func__, (int)offset); 78 break; 79 } 80 81 return 0; 82 } 83 84 static void a10_pit_set_freq(AwA10PITState *s, int index) 85 { 86 uint32_t prescaler, source, source_freq; 87 88 prescaler = 1 << extract32(s->control[index], 4, 3); 89 source = extract32(s->control[index], 2, 2); 90 source_freq = s->clk_freq[source]; 91 92 if (source_freq) { 93 ptimer_set_freq(s->timer[index], source_freq / prescaler); 94 } else { 95 qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid clock source %u\n", 96 __func__, source); 97 } 98 } 99 100 static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, 101 unsigned size) 102 { 103 AwA10PITState *s = AW_A10_PIT(opaque); 104 uint8_t index; 105 106 switch (offset) { 107 case AW_A10_PIT_TIMER_IRQ_EN: 108 s->irq_enable = value; 109 a10_pit_update_irq(s); 110 break; 111 case AW_A10_PIT_TIMER_IRQ_ST: 112 s->irq_status &= ~value; 113 a10_pit_update_irq(s); 114 break; 115 case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END: 116 index = offset & 0xf0; 117 index >>= 4; 118 index -= 1; 119 switch (offset & 0x0f) { 120 case AW_A10_PIT_TIMER_CONTROL: 121 s->control[index] = value; 122 a10_pit_set_freq(s, index); 123 if (s->control[index] & AW_A10_PIT_TIMER_RELOAD) { 124 ptimer_set_count(s->timer[index], s->interval[index]); 125 } 126 if (s->control[index] & AW_A10_PIT_TIMER_EN) { 127 int oneshot = 0; 128 if (s->control[index] & AW_A10_PIT_TIMER_MODE) { 129 oneshot = 1; 130 } 131 ptimer_run(s->timer[index], oneshot); 132 } else { 133 ptimer_stop(s->timer[index]); 134 } 135 break; 136 case AW_A10_PIT_TIMER_INTERVAL: 137 s->interval[index] = value; 138 ptimer_set_limit(s->timer[index], s->interval[index], 1); 139 break; 140 case AW_A10_PIT_TIMER_COUNT: 141 s->count[index] = value; 142 break; 143 default: 144 qemu_log_mask(LOG_GUEST_ERROR, 145 "%s: Bad offset 0x%x\n", __func__, (int)offset); 146 } 147 break; 148 case AW_A10_PIT_WDOG_CONTROL: 149 s->watch_dog_control = value; 150 break; 151 case AW_A10_PIT_WDOG_MODE: 152 s->watch_dog_mode = value; 153 break; 154 case AW_A10_PIT_COUNT_LO: 155 s->count_lo = value; 156 break; 157 case AW_A10_PIT_COUNT_HI: 158 s->count_hi = value; 159 break; 160 case AW_A10_PIT_COUNT_CTL: 161 s->count_ctl = value; 162 if (s->count_ctl & AW_A10_PIT_COUNT_RL_EN) { 163 uint64_t tmp_count = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 164 165 s->count_lo = tmp_count; 166 s->count_hi = tmp_count >> 32; 167 s->count_ctl &= ~AW_A10_PIT_COUNT_RL_EN; 168 } 169 if (s->count_ctl & AW_A10_PIT_COUNT_CLR_EN) { 170 s->count_lo = 0; 171 s->count_hi = 0; 172 s->count_ctl &= ~AW_A10_PIT_COUNT_CLR_EN; 173 } 174 break; 175 default: 176 qemu_log_mask(LOG_GUEST_ERROR, 177 "%s: Bad offset 0x%x\n", __func__, (int)offset); 178 break; 179 } 180 } 181 182 static const MemoryRegionOps a10_pit_ops = { 183 .read = a10_pit_read, 184 .write = a10_pit_write, 185 .endianness = DEVICE_NATIVE_ENDIAN, 186 }; 187 188 static Property a10_pit_properties[] = { 189 DEFINE_PROP_UINT32("clk0-freq", AwA10PITState, clk_freq[0], 0), 190 DEFINE_PROP_UINT32("clk1-freq", AwA10PITState, clk_freq[1], 0), 191 DEFINE_PROP_UINT32("clk2-freq", AwA10PITState, clk_freq[2], 0), 192 DEFINE_PROP_UINT32("clk3-freq", AwA10PITState, clk_freq[3], 0), 193 DEFINE_PROP_END_OF_LIST(), 194 }; 195 196 static const VMStateDescription vmstate_a10_pit = { 197 .name = "a10.pit", 198 .version_id = 1, 199 .minimum_version_id = 1, 200 .fields = (VMStateField[]) { 201 VMSTATE_UINT32(irq_enable, AwA10PITState), 202 VMSTATE_UINT32(irq_status, AwA10PITState), 203 VMSTATE_UINT32_ARRAY(control, AwA10PITState, AW_A10_PIT_TIMER_NR), 204 VMSTATE_UINT32_ARRAY(interval, AwA10PITState, AW_A10_PIT_TIMER_NR), 205 VMSTATE_UINT32_ARRAY(count, AwA10PITState, AW_A10_PIT_TIMER_NR), 206 VMSTATE_UINT32(watch_dog_mode, AwA10PITState), 207 VMSTATE_UINT32(watch_dog_control, AwA10PITState), 208 VMSTATE_UINT32(count_lo, AwA10PITState), 209 VMSTATE_UINT32(count_hi, AwA10PITState), 210 VMSTATE_UINT32(count_ctl, AwA10PITState), 211 VMSTATE_PTIMER_ARRAY(timer, AwA10PITState, AW_A10_PIT_TIMER_NR), 212 VMSTATE_END_OF_LIST() 213 } 214 }; 215 216 static void a10_pit_reset(DeviceState *dev) 217 { 218 AwA10PITState *s = AW_A10_PIT(dev); 219 uint8_t i; 220 221 s->irq_enable = 0; 222 s->irq_status = 0; 223 a10_pit_update_irq(s); 224 225 for (i = 0; i < 6; i++) { 226 s->control[i] = AW_A10_PIT_DEFAULT_CLOCK; 227 s->interval[i] = 0; 228 s->count[i] = 0; 229 ptimer_stop(s->timer[i]); 230 a10_pit_set_freq(s, i); 231 } 232 s->watch_dog_mode = 0; 233 s->watch_dog_control = 0; 234 s->count_lo = 0; 235 s->count_hi = 0; 236 s->count_ctl = 0; 237 } 238 239 static void a10_pit_timer_cb(void *opaque) 240 { 241 AwA10TimerContext *tc = opaque; 242 AwA10PITState *s = tc->container; 243 uint8_t i = tc->index; 244 245 if (s->control[i] & AW_A10_PIT_TIMER_EN) { 246 s->irq_status |= 1 << i; 247 if (s->control[i] & AW_A10_PIT_TIMER_MODE) { 248 ptimer_stop(s->timer[i]); 249 s->control[i] &= ~AW_A10_PIT_TIMER_EN; 250 } 251 a10_pit_update_irq(s); 252 } 253 } 254 255 static void a10_pit_init(Object *obj) 256 { 257 AwA10PITState *s = AW_A10_PIT(obj); 258 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 259 QEMUBH * bh[AW_A10_PIT_TIMER_NR]; 260 uint8_t i; 261 262 for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { 263 sysbus_init_irq(sbd, &s->irq[i]); 264 } 265 memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s, 266 TYPE_AW_A10_PIT, 0x400); 267 sysbus_init_mmio(sbd, &s->iomem); 268 269 for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { 270 AwA10TimerContext *tc = &s->timer_context[i]; 271 272 tc->container = s; 273 tc->index = i; 274 bh[i] = qemu_bh_new(a10_pit_timer_cb, tc); 275 s->timer[i] = ptimer_init(bh[i], PTIMER_POLICY_DEFAULT); 276 } 277 } 278 279 static void a10_pit_class_init(ObjectClass *klass, void *data) 280 { 281 DeviceClass *dc = DEVICE_CLASS(klass); 282 283 dc->reset = a10_pit_reset; 284 dc->props = a10_pit_properties; 285 dc->desc = "allwinner a10 timer"; 286 dc->vmsd = &vmstate_a10_pit; 287 } 288 289 static const TypeInfo a10_pit_info = { 290 .name = TYPE_AW_A10_PIT, 291 .parent = TYPE_SYS_BUS_DEVICE, 292 .instance_size = sizeof(AwA10PITState), 293 .instance_init = a10_pit_init, 294 .class_init = a10_pit_class_init, 295 }; 296 297 static void a10_register_types(void) 298 { 299 type_register_static(&a10_pit_info); 300 } 301 302 type_init(a10_register_types); 303