1 /* 2 * QEMU model of the Xilinx Zynq SPI controller 3 * 4 * Copyright (c) 2012 Peter A. G. Crosthwaite 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/sysbus.h" 27 #include "sysemu/sysemu.h" 28 #include "hw/ptimer.h" 29 #include "qemu/log.h" 30 #include "qemu/bitops.h" 31 #include "hw/ssi/xilinx_spips.h" 32 #include "qapi/error.h" 33 #include "hw/register.h" 34 #include "migration/blocker.h" 35 36 #ifndef XILINX_SPIPS_ERR_DEBUG 37 #define XILINX_SPIPS_ERR_DEBUG 0 38 #endif 39 40 #define DB_PRINT_L(level, ...) do { \ 41 if (XILINX_SPIPS_ERR_DEBUG > (level)) { \ 42 fprintf(stderr, ": %s: ", __func__); \ 43 fprintf(stderr, ## __VA_ARGS__); \ 44 } \ 45 } while (0); 46 47 /* config register */ 48 #define R_CONFIG (0x00 / 4) 49 #define IFMODE (1U << 31) 50 #define R_CONFIG_ENDIAN (1 << 26) 51 #define MODEFAIL_GEN_EN (1 << 17) 52 #define MAN_START_COM (1 << 16) 53 #define MAN_START_EN (1 << 15) 54 #define MANUAL_CS (1 << 14) 55 #define CS (0xF << 10) 56 #define CS_SHIFT (10) 57 #define PERI_SEL (1 << 9) 58 #define REF_CLK (1 << 8) 59 #define FIFO_WIDTH (3 << 6) 60 #define BAUD_RATE_DIV (7 << 3) 61 #define CLK_PH (1 << 2) 62 #define CLK_POL (1 << 1) 63 #define MODE_SEL (1 << 0) 64 #define R_CONFIG_RSVD (0x7bf40000) 65 66 /* interrupt mechanism */ 67 #define R_INTR_STATUS (0x04 / 4) 68 #define R_INTR_EN (0x08 / 4) 69 #define R_INTR_DIS (0x0C / 4) 70 #define R_INTR_MASK (0x10 / 4) 71 #define IXR_TX_FIFO_UNDERFLOW (1 << 6) 72 #define IXR_RX_FIFO_FULL (1 << 5) 73 #define IXR_RX_FIFO_NOT_EMPTY (1 << 4) 74 #define IXR_TX_FIFO_FULL (1 << 3) 75 #define IXR_TX_FIFO_NOT_FULL (1 << 2) 76 #define IXR_TX_FIFO_MODE_FAIL (1 << 1) 77 #define IXR_RX_FIFO_OVERFLOW (1 << 0) 78 #define IXR_ALL ((IXR_TX_FIFO_UNDERFLOW<<1)-1) 79 80 #define R_EN (0x14 / 4) 81 #define R_DELAY (0x18 / 4) 82 #define R_TX_DATA (0x1C / 4) 83 #define R_RX_DATA (0x20 / 4) 84 #define R_SLAVE_IDLE_COUNT (0x24 / 4) 85 #define R_TX_THRES (0x28 / 4) 86 #define R_RX_THRES (0x2C / 4) 87 #define R_TXD1 (0x80 / 4) 88 #define R_TXD2 (0x84 / 4) 89 #define R_TXD3 (0x88 / 4) 90 91 #define R_LQSPI_CFG (0xa0 / 4) 92 #define R_LQSPI_CFG_RESET 0x03A002EB 93 #define LQSPI_CFG_LQ_MODE (1U << 31) 94 #define LQSPI_CFG_TWO_MEM (1 << 30) 95 #define LQSPI_CFG_SEP_BUS (1 << 29) 96 #define LQSPI_CFG_U_PAGE (1 << 28) 97 #define LQSPI_CFG_ADDR4 (1 << 27) 98 #define LQSPI_CFG_MODE_EN (1 << 25) 99 #define LQSPI_CFG_MODE_WIDTH 8 100 #define LQSPI_CFG_MODE_SHIFT 16 101 #define LQSPI_CFG_DUMMY_WIDTH 3 102 #define LQSPI_CFG_DUMMY_SHIFT 8 103 #define LQSPI_CFG_INST_CODE 0xFF 104 105 #define R_CMND (0xc0 / 4) 106 #define R_CMND_RXFIFO_DRAIN (1 << 19) 107 FIELD(CMND, PARTIAL_BYTE_LEN, 16, 3) 108 #define R_CMND_EXT_ADD (1 << 15) 109 FIELD(CMND, RX_DISCARD, 8, 7) 110 FIELD(CMND, DUMMY_CYCLES, 2, 6) 111 #define R_CMND_DMA_EN (1 << 1) 112 #define R_CMND_PUSH_WAIT (1 << 0) 113 #define R_TRANSFER_SIZE (0xc4 / 4) 114 #define R_LQSPI_STS (0xA4 / 4) 115 #define LQSPI_STS_WR_RECVD (1 << 1) 116 117 #define R_MOD_ID (0xFC / 4) 118 119 /* size of TXRX FIFOs */ 120 #define RXFF_A 32 121 #define TXFF_A 32 122 123 #define RXFF_A_Q (64 * 4) 124 #define TXFF_A_Q (64 * 4) 125 126 /* 16MB per linear region */ 127 #define LQSPI_ADDRESS_BITS 24 128 129 #define SNOOP_CHECKING 0xFF 130 #define SNOOP_ADDR 0xF0 131 #define SNOOP_NONE 0xEE 132 #define SNOOP_STRIPING 0 133 134 static inline int num_effective_busses(XilinxSPIPS *s) 135 { 136 return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && 137 s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1; 138 } 139 140 static inline bool xilinx_spips_cs_is_set(XilinxSPIPS *s, int i, int field) 141 { 142 return ~field & (1 << i) && (s->regs[R_CONFIG] & MANUAL_CS 143 || !fifo8_is_empty(&s->tx_fifo)); 144 } 145 146 static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) 147 { 148 int i, j; 149 bool found = false; 150 int field = s->regs[R_CONFIG] >> CS_SHIFT; 151 152 for (i = 0; i < s->num_cs; i++) { 153 for (j = 0; j < num_effective_busses(s); j++) { 154 int upage = !!(s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE); 155 int cs_to_set = (j * s->num_cs + i + upage) % 156 (s->num_cs * s->num_busses); 157 158 if (xilinx_spips_cs_is_set(s, i, field) && !found) { 159 DB_PRINT_L(0, "selecting slave %d\n", i); 160 qemu_set_irq(s->cs_lines[cs_to_set], 0); 161 if (s->cs_lines_state[cs_to_set]) { 162 s->cs_lines_state[cs_to_set] = false; 163 s->rx_discard = ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD); 164 } 165 } else { 166 DB_PRINT_L(0, "deselecting slave %d\n", i); 167 qemu_set_irq(s->cs_lines[cs_to_set], 1); 168 s->cs_lines_state[cs_to_set] = true; 169 } 170 } 171 if (xilinx_spips_cs_is_set(s, i, field)) { 172 found = true; 173 } 174 } 175 if (!found) { 176 s->snoop_state = SNOOP_CHECKING; 177 s->cmd_dummies = 0; 178 s->link_state = 1; 179 s->link_state_next = 1; 180 s->link_state_next_when = 0; 181 DB_PRINT_L(1, "moving to snoop check state\n"); 182 } 183 } 184 185 static void xilinx_spips_update_ixr(XilinxSPIPS *s) 186 { 187 if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE) { 188 return; 189 } 190 /* These are set/cleared as they occur */ 191 s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW | 192 IXR_TX_FIFO_MODE_FAIL); 193 /* these are pure functions of fifo state, set them here */ 194 s->regs[R_INTR_STATUS] |= 195 (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) | 196 (s->rx_fifo.num >= s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY : 0) | 197 (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | 198 (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0); 199 /* drive external interrupt pin */ 200 int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] & 201 IXR_ALL); 202 if (new_irqline != s->irqline) { 203 s->irqline = new_irqline; 204 qemu_set_irq(s->irq, s->irqline); 205 } 206 } 207 208 static void xilinx_spips_reset(DeviceState *d) 209 { 210 XilinxSPIPS *s = XILINX_SPIPS(d); 211 212 int i; 213 for (i = 0; i < XLNX_SPIPS_R_MAX; i++) { 214 s->regs[i] = 0; 215 } 216 217 fifo8_reset(&s->rx_fifo); 218 fifo8_reset(&s->rx_fifo); 219 /* non zero resets */ 220 s->regs[R_CONFIG] |= MODEFAIL_GEN_EN; 221 s->regs[R_SLAVE_IDLE_COUNT] = 0xFF; 222 s->regs[R_TX_THRES] = 1; 223 s->regs[R_RX_THRES] = 1; 224 /* FIXME: move magic number definition somewhere sensible */ 225 s->regs[R_MOD_ID] = 0x01090106; 226 s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET; 227 s->link_state = 1; 228 s->link_state_next = 1; 229 s->link_state_next_when = 0; 230 s->snoop_state = SNOOP_CHECKING; 231 s->cmd_dummies = 0; 232 s->man_start_com = false; 233 xilinx_spips_update_ixr(s); 234 xilinx_spips_update_cs_lines(s); 235 } 236 237 /* N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) 238 * column wise (from element 0 to N-1). num is the length of x, and dir 239 * reverses the direction of the transform. Best illustrated by example: 240 * Each digit in the below array is a single bit (num == 3): 241 * 242 * {{ 76543210, } ----- stripe (dir == false) -----> {{ 741gdaFC, } 243 * { hgfedcba, } { 630fcHEB, } 244 * { HGFEDCBA, }} <---- upstripe (dir == true) ----- { 52hebGDA, }} 245 */ 246 247 static inline void stripe8(uint8_t *x, int num, bool dir) 248 { 249 uint8_t r[num]; 250 memset(r, 0, sizeof(uint8_t) * num); 251 int idx[2] = {0, 0}; 252 int bit[2] = {0, 7}; 253 int d = dir; 254 255 for (idx[0] = 0; idx[0] < num; ++idx[0]) { 256 for (bit[0] = 7; bit[0] >= 0; bit[0]--) { 257 r[idx[!d]] |= x[idx[d]] & 1 << bit[d] ? 1 << bit[!d] : 0; 258 idx[1] = (idx[1] + 1) % num; 259 if (!idx[1]) { 260 bit[1]--; 261 } 262 } 263 } 264 memcpy(x, r, sizeof(uint8_t) * num); 265 } 266 267 static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command) 268 { 269 if (!qs) { 270 /* The SPI device is not a QSPI device */ 271 return -1; 272 } 273 274 switch (command) { /* check for dummies */ 275 case READ: /* no dummy bytes/cycles */ 276 case PP: 277 case DPP: 278 case QPP: 279 case READ_4: 280 case PP_4: 281 case QPP_4: 282 return 0; 283 case FAST_READ: 284 case DOR: 285 case QOR: 286 case DOR_4: 287 case QOR_4: 288 return 1; 289 case DIOR: 290 case FAST_READ_4: 291 case DIOR_4: 292 return 2; 293 case QIOR: 294 case QIOR_4: 295 return 5; 296 default: 297 return -1; 298 } 299 } 300 301 static inline uint8_t get_addr_length(XilinxSPIPS *s, uint8_t cmd) 302 { 303 switch (cmd) { 304 case PP_4: 305 case QPP_4: 306 case READ_4: 307 case QIOR_4: 308 case FAST_READ_4: 309 case DOR_4: 310 case QOR_4: 311 case DIOR_4: 312 return 4; 313 default: 314 return (s->regs[R_CMND] & R_CMND_EXT_ADD) ? 4 : 3; 315 } 316 } 317 318 static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) 319 { 320 int debug_level = 0; 321 XilinxQSPIPS *q = (XilinxQSPIPS *) object_dynamic_cast(OBJECT(s), 322 TYPE_XILINX_QSPIPS); 323 324 for (;;) { 325 int i; 326 uint8_t tx = 0; 327 uint8_t tx_rx[num_effective_busses(s)]; 328 uint8_t dummy_cycles = 0; 329 uint8_t addr_length; 330 331 if (fifo8_is_empty(&s->tx_fifo)) { 332 if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { 333 s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW; 334 } 335 xilinx_spips_update_ixr(s); 336 return; 337 } else if (s->snoop_state == SNOOP_STRIPING) { 338 for (i = 0; i < num_effective_busses(s); ++i) { 339 tx_rx[i] = fifo8_pop(&s->tx_fifo); 340 } 341 stripe8(tx_rx, num_effective_busses(s), false); 342 } else if (s->snoop_state >= SNOOP_ADDR) { 343 tx = fifo8_pop(&s->tx_fifo); 344 for (i = 0; i < num_effective_busses(s); ++i) { 345 tx_rx[i] = tx; 346 } 347 } else { 348 /* Extract a dummy byte and generate dummy cycles according to the 349 * link state */ 350 tx = fifo8_pop(&s->tx_fifo); 351 dummy_cycles = 8 / s->link_state; 352 } 353 354 for (i = 0; i < num_effective_busses(s); ++i) { 355 int bus = num_effective_busses(s) - 1 - i; 356 if (dummy_cycles) { 357 int d; 358 for (d = 0; d < dummy_cycles; ++d) { 359 tx_rx[0] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[0]); 360 } 361 } else { 362 DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]); 363 tx_rx[i] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]); 364 DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]); 365 } 366 } 367 368 if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { 369 DB_PRINT_L(debug_level, "dircarding drained rx byte\n"); 370 /* Do nothing */ 371 } else if (s->rx_discard) { 372 DB_PRINT_L(debug_level, "dircarding discarded rx byte\n"); 373 s->rx_discard -= 8 / s->link_state; 374 } else if (fifo8_is_full(&s->rx_fifo)) { 375 s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW; 376 DB_PRINT_L(0, "rx FIFO overflow"); 377 } else if (s->snoop_state == SNOOP_STRIPING) { 378 stripe8(tx_rx, num_effective_busses(s), true); 379 for (i = 0; i < num_effective_busses(s); ++i) { 380 fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]); 381 DB_PRINT_L(debug_level, "pushing striped rx byte\n"); 382 } 383 } else { 384 DB_PRINT_L(debug_level, "pushing unstriped rx byte\n"); 385 fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]); 386 } 387 388 if (s->link_state_next_when) { 389 s->link_state_next_when--; 390 if (!s->link_state_next_when) { 391 s->link_state = s->link_state_next; 392 } 393 } 394 395 DB_PRINT_L(debug_level, "initial snoop state: %x\n", 396 (unsigned)s->snoop_state); 397 switch (s->snoop_state) { 398 case (SNOOP_CHECKING): 399 /* Store the count of dummy bytes in the txfifo */ 400 s->cmd_dummies = xilinx_spips_num_dummies(q, tx); 401 addr_length = get_addr_length(s, tx); 402 if (s->cmd_dummies < 0) { 403 s->snoop_state = SNOOP_NONE; 404 } else { 405 s->snoop_state = SNOOP_ADDR + addr_length - 1; 406 } 407 switch (tx) { 408 case DPP: 409 case DOR: 410 case DOR_4: 411 s->link_state_next = 2; 412 s->link_state_next_when = addr_length + s->cmd_dummies; 413 break; 414 case QPP: 415 case QPP_4: 416 case QOR: 417 case QOR_4: 418 s->link_state_next = 4; 419 s->link_state_next_when = addr_length + s->cmd_dummies; 420 break; 421 case DIOR: 422 case DIOR_4: 423 s->link_state = 2; 424 break; 425 case QIOR: 426 case QIOR_4: 427 s->link_state = 4; 428 break; 429 } 430 break; 431 case (SNOOP_ADDR): 432 /* Address has been transmitted, transmit dummy cycles now if 433 * needed */ 434 if (s->cmd_dummies < 0) { 435 s->snoop_state = SNOOP_NONE; 436 } else { 437 s->snoop_state = s->cmd_dummies; 438 } 439 break; 440 case (SNOOP_STRIPING): 441 case (SNOOP_NONE): 442 /* Once we hit the boring stuff - squelch debug noise */ 443 if (!debug_level) { 444 DB_PRINT_L(0, "squelching debug info ....\n"); 445 debug_level = 1; 446 } 447 break; 448 default: 449 s->snoop_state--; 450 } 451 DB_PRINT_L(debug_level, "final snoop state: %x\n", 452 (unsigned)s->snoop_state); 453 } 454 } 455 456 static inline void tx_data_bytes(Fifo8 *fifo, uint32_t value, int num, bool be) 457 { 458 int i; 459 for (i = 0; i < num && !fifo8_is_full(fifo); ++i) { 460 if (be) { 461 fifo8_push(fifo, (uint8_t)(value >> 24)); 462 value <<= 8; 463 } else { 464 fifo8_push(fifo, (uint8_t)value); 465 value >>= 8; 466 } 467 } 468 } 469 470 static void xilinx_spips_check_zero_pump(XilinxSPIPS *s) 471 { 472 if (!s->regs[R_TRANSFER_SIZE]) { 473 return; 474 } 475 if (!fifo8_is_empty(&s->tx_fifo) && s->regs[R_CMND] & R_CMND_PUSH_WAIT) { 476 return; 477 } 478 /* 479 * The zero pump must never fill tx fifo such that rx overflow is 480 * possible 481 */ 482 while (s->regs[R_TRANSFER_SIZE] && 483 s->rx_fifo.num + s->tx_fifo.num < RXFF_A_Q - 3) { 484 /* endianess just doesn't matter when zero pumping */ 485 tx_data_bytes(&s->tx_fifo, 0, 4, false); 486 s->regs[R_TRANSFER_SIZE] &= ~0x03ull; 487 s->regs[R_TRANSFER_SIZE] -= 4; 488 } 489 } 490 491 static void xilinx_spips_check_flush(XilinxSPIPS *s) 492 { 493 if (s->man_start_com || 494 (!fifo8_is_empty(&s->tx_fifo) && 495 !(s->regs[R_CONFIG] & MAN_START_EN))) { 496 xilinx_spips_check_zero_pump(s); 497 xilinx_spips_flush_txfifo(s); 498 } 499 if (fifo8_is_empty(&s->tx_fifo) && !s->regs[R_TRANSFER_SIZE]) { 500 s->man_start_com = false; 501 } 502 xilinx_spips_update_ixr(s); 503 } 504 505 static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max) 506 { 507 int i; 508 509 for (i = 0; i < max && !fifo8_is_empty(fifo); ++i) { 510 value[i] = fifo8_pop(fifo); 511 } 512 return max - i; 513 } 514 515 static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, 516 unsigned size) 517 { 518 XilinxSPIPS *s = opaque; 519 uint32_t mask = ~0; 520 uint32_t ret; 521 uint8_t rx_buf[4]; 522 int shortfall; 523 524 addr >>= 2; 525 switch (addr) { 526 case R_CONFIG: 527 mask = ~(R_CONFIG_RSVD | MAN_START_COM); 528 break; 529 case R_INTR_STATUS: 530 ret = s->regs[addr] & IXR_ALL; 531 s->regs[addr] = 0; 532 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 533 return ret; 534 case R_INTR_MASK: 535 mask = IXR_ALL; 536 break; 537 case R_EN: 538 mask = 0x1; 539 break; 540 case R_SLAVE_IDLE_COUNT: 541 mask = 0xFF; 542 break; 543 case R_MOD_ID: 544 mask = 0x01FFFFFF; 545 break; 546 case R_INTR_EN: 547 case R_INTR_DIS: 548 case R_TX_DATA: 549 mask = 0; 550 break; 551 case R_RX_DATA: 552 memset(rx_buf, 0, sizeof(rx_buf)); 553 shortfall = rx_data_bytes(&s->rx_fifo, rx_buf, s->num_txrx_bytes); 554 ret = s->regs[R_CONFIG] & R_CONFIG_ENDIAN ? 555 cpu_to_be32(*(uint32_t *)rx_buf) : 556 cpu_to_le32(*(uint32_t *)rx_buf); 557 if (!(s->regs[R_CONFIG] & R_CONFIG_ENDIAN)) { 558 ret <<= 8 * shortfall; 559 } 560 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 561 xilinx_spips_update_ixr(s); 562 return ret; 563 } 564 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, 565 s->regs[addr] & mask); 566 return s->regs[addr] & mask; 567 568 } 569 570 static void xilinx_spips_write(void *opaque, hwaddr addr, 571 uint64_t value, unsigned size) 572 { 573 int mask = ~0; 574 XilinxSPIPS *s = opaque; 575 576 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value); 577 addr >>= 2; 578 switch (addr) { 579 case R_CONFIG: 580 mask = ~(R_CONFIG_RSVD | MAN_START_COM); 581 if ((value & MAN_START_COM) && (s->regs[R_CONFIG] & MAN_START_EN)) { 582 s->man_start_com = true; 583 } 584 break; 585 case R_INTR_STATUS: 586 mask = IXR_ALL; 587 s->regs[R_INTR_STATUS] &= ~(mask & value); 588 goto no_reg_update; 589 case R_INTR_DIS: 590 mask = IXR_ALL; 591 s->regs[R_INTR_MASK] &= ~(mask & value); 592 goto no_reg_update; 593 case R_INTR_EN: 594 mask = IXR_ALL; 595 s->regs[R_INTR_MASK] |= mask & value; 596 goto no_reg_update; 597 case R_EN: 598 mask = 0x1; 599 break; 600 case R_SLAVE_IDLE_COUNT: 601 mask = 0xFF; 602 break; 603 case R_RX_DATA: 604 case R_INTR_MASK: 605 case R_MOD_ID: 606 mask = 0; 607 break; 608 case R_TX_DATA: 609 tx_data_bytes(&s->tx_fifo, (uint32_t)value, s->num_txrx_bytes, 610 s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 611 goto no_reg_update; 612 case R_TXD1: 613 tx_data_bytes(&s->tx_fifo, (uint32_t)value, 1, 614 s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 615 goto no_reg_update; 616 case R_TXD2: 617 tx_data_bytes(&s->tx_fifo, (uint32_t)value, 2, 618 s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 619 goto no_reg_update; 620 case R_TXD3: 621 tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3, 622 s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 623 goto no_reg_update; 624 } 625 s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); 626 no_reg_update: 627 xilinx_spips_update_cs_lines(s); 628 xilinx_spips_check_flush(s); 629 xilinx_spips_update_cs_lines(s); 630 xilinx_spips_update_ixr(s); 631 } 632 633 static const MemoryRegionOps spips_ops = { 634 .read = xilinx_spips_read, 635 .write = xilinx_spips_write, 636 .endianness = DEVICE_LITTLE_ENDIAN, 637 }; 638 639 static void xilinx_qspips_invalidate_mmio_ptr(XilinxQSPIPS *q) 640 { 641 XilinxSPIPS *s = &q->parent_obj; 642 643 if ((q->mmio_execution_enabled) && (q->lqspi_cached_addr != ~0ULL)) { 644 /* Invalidate the current mapped mmio */ 645 memory_region_invalidate_mmio_ptr(&s->mmlqspi, q->lqspi_cached_addr, 646 LQSPI_CACHE_SIZE); 647 } 648 649 q->lqspi_cached_addr = ~0ULL; 650 } 651 652 static void xilinx_qspips_write(void *opaque, hwaddr addr, 653 uint64_t value, unsigned size) 654 { 655 XilinxQSPIPS *q = XILINX_QSPIPS(opaque); 656 XilinxSPIPS *s = XILINX_SPIPS(opaque); 657 658 xilinx_spips_write(opaque, addr, value, size); 659 addr >>= 2; 660 661 if (addr == R_LQSPI_CFG) { 662 xilinx_qspips_invalidate_mmio_ptr(q); 663 } 664 if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { 665 fifo8_reset(&s->rx_fifo); 666 } 667 } 668 669 static const MemoryRegionOps qspips_ops = { 670 .read = xilinx_spips_read, 671 .write = xilinx_qspips_write, 672 .endianness = DEVICE_LITTLE_ENDIAN, 673 }; 674 675 #define LQSPI_CACHE_SIZE 1024 676 677 static void lqspi_load_cache(void *opaque, hwaddr addr) 678 { 679 XilinxQSPIPS *q = opaque; 680 XilinxSPIPS *s = opaque; 681 int i; 682 int flash_addr = ((addr & ~(LQSPI_CACHE_SIZE - 1)) 683 / num_effective_busses(s)); 684 int slave = flash_addr >> LQSPI_ADDRESS_BITS; 685 int cache_entry = 0; 686 uint32_t u_page_save = s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE; 687 688 if (addr < q->lqspi_cached_addr || 689 addr > q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { 690 xilinx_qspips_invalidate_mmio_ptr(q); 691 s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 692 s->regs[R_LQSPI_STS] |= slave ? LQSPI_CFG_U_PAGE : 0; 693 694 DB_PRINT_L(0, "config reg status: %08x\n", s->regs[R_LQSPI_CFG]); 695 696 fifo8_reset(&s->tx_fifo); 697 fifo8_reset(&s->rx_fifo); 698 699 /* instruction */ 700 DB_PRINT_L(0, "pushing read instruction: %02x\n", 701 (unsigned)(uint8_t)(s->regs[R_LQSPI_CFG] & 702 LQSPI_CFG_INST_CODE)); 703 fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE); 704 /* read address */ 705 DB_PRINT_L(0, "pushing read address %06x\n", flash_addr); 706 if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_ADDR4) { 707 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 24)); 708 } 709 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16)); 710 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8)); 711 fifo8_push(&s->tx_fifo, (uint8_t)flash_addr); 712 /* mode bits */ 713 if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) { 714 fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG], 715 LQSPI_CFG_MODE_SHIFT, 716 LQSPI_CFG_MODE_WIDTH)); 717 } 718 /* dummy bytes */ 719 for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT, 720 LQSPI_CFG_DUMMY_WIDTH)); ++i) { 721 DB_PRINT_L(0, "pushing dummy byte\n"); 722 fifo8_push(&s->tx_fifo, 0); 723 } 724 xilinx_spips_update_cs_lines(s); 725 xilinx_spips_flush_txfifo(s); 726 fifo8_reset(&s->rx_fifo); 727 728 DB_PRINT_L(0, "starting QSPI data read\n"); 729 730 while (cache_entry < LQSPI_CACHE_SIZE) { 731 for (i = 0; i < 64; ++i) { 732 tx_data_bytes(&s->tx_fifo, 0, 1, false); 733 } 734 xilinx_spips_flush_txfifo(s); 735 for (i = 0; i < 64; ++i) { 736 rx_data_bytes(&s->rx_fifo, &q->lqspi_buf[cache_entry++], 1); 737 } 738 } 739 740 s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 741 s->regs[R_LQSPI_STS] |= u_page_save; 742 xilinx_spips_update_cs_lines(s); 743 744 q->lqspi_cached_addr = flash_addr * num_effective_busses(s); 745 } 746 } 747 748 static void *lqspi_request_mmio_ptr(void *opaque, hwaddr addr, unsigned *size, 749 unsigned *offset) 750 { 751 XilinxQSPIPS *q = opaque; 752 hwaddr offset_within_the_region; 753 754 if (!q->mmio_execution_enabled) { 755 return NULL; 756 } 757 758 offset_within_the_region = addr & ~(LQSPI_CACHE_SIZE - 1); 759 lqspi_load_cache(opaque, offset_within_the_region); 760 *size = LQSPI_CACHE_SIZE; 761 *offset = offset_within_the_region; 762 return q->lqspi_buf; 763 } 764 765 static uint64_t 766 lqspi_read(void *opaque, hwaddr addr, unsigned int size) 767 { 768 XilinxQSPIPS *q = opaque; 769 uint32_t ret; 770 771 if (addr >= q->lqspi_cached_addr && 772 addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { 773 uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr]; 774 ret = cpu_to_le32(*(uint32_t *)retp); 775 DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr, 776 (unsigned)ret); 777 return ret; 778 } else { 779 lqspi_load_cache(opaque, addr); 780 return lqspi_read(opaque, addr, size); 781 } 782 } 783 784 static const MemoryRegionOps lqspi_ops = { 785 .read = lqspi_read, 786 .request_ptr = lqspi_request_mmio_ptr, 787 .endianness = DEVICE_NATIVE_ENDIAN, 788 .valid = { 789 .min_access_size = 1, 790 .max_access_size = 4 791 } 792 }; 793 794 static void xilinx_spips_realize(DeviceState *dev, Error **errp) 795 { 796 XilinxSPIPS *s = XILINX_SPIPS(dev); 797 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 798 XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s); 799 qemu_irq *cs; 800 int i; 801 802 DB_PRINT_L(0, "realized spips\n"); 803 804 s->spi = g_new(SSIBus *, s->num_busses); 805 for (i = 0; i < s->num_busses; ++i) { 806 char bus_name[16]; 807 snprintf(bus_name, 16, "spi%d", i); 808 s->spi[i] = ssi_create_bus(dev, bus_name); 809 } 810 811 s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses); 812 s->cs_lines_state = g_new0(bool, s->num_cs * s->num_busses); 813 for (i = 0, cs = s->cs_lines; i < s->num_busses; ++i, cs += s->num_cs) { 814 ssi_auto_connect_slaves(DEVICE(s), cs, s->spi[i]); 815 } 816 817 sysbus_init_irq(sbd, &s->irq); 818 for (i = 0; i < s->num_cs * s->num_busses; ++i) { 819 sysbus_init_irq(sbd, &s->cs_lines[i]); 820 } 821 822 memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s, 823 "spi", XLNX_SPIPS_R_MAX * 4); 824 sysbus_init_mmio(sbd, &s->iomem); 825 826 s->irqline = -1; 827 828 fifo8_create(&s->rx_fifo, xsc->rx_fifo_size); 829 fifo8_create(&s->tx_fifo, xsc->tx_fifo_size); 830 } 831 832 static void xilinx_qspips_realize(DeviceState *dev, Error **errp) 833 { 834 XilinxSPIPS *s = XILINX_SPIPS(dev); 835 XilinxQSPIPS *q = XILINX_QSPIPS(dev); 836 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 837 838 DB_PRINT_L(0, "realized qspips\n"); 839 840 s->num_busses = 2; 841 s->num_cs = 2; 842 s->num_txrx_bytes = 4; 843 844 xilinx_spips_realize(dev, errp); 845 memory_region_init_io(&s->mmlqspi, OBJECT(s), &lqspi_ops, s, "lqspi", 846 (1 << LQSPI_ADDRESS_BITS) * 2); 847 sysbus_init_mmio(sbd, &s->mmlqspi); 848 849 q->lqspi_cached_addr = ~0ULL; 850 851 /* mmio_execution breaks migration better aborting than having strange 852 * bugs. 853 */ 854 if (q->mmio_execution_enabled) { 855 error_setg(&q->migration_blocker, 856 "enabling mmio_execution breaks migration"); 857 migrate_add_blocker(q->migration_blocker, &error_fatal); 858 } 859 } 860 861 static int xilinx_spips_post_load(void *opaque, int version_id) 862 { 863 xilinx_spips_update_ixr((XilinxSPIPS *)opaque); 864 xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque); 865 return 0; 866 } 867 868 static const VMStateDescription vmstate_xilinx_spips = { 869 .name = "xilinx_spips", 870 .version_id = 2, 871 .minimum_version_id = 2, 872 .post_load = xilinx_spips_post_load, 873 .fields = (VMStateField[]) { 874 VMSTATE_FIFO8(tx_fifo, XilinxSPIPS), 875 VMSTATE_FIFO8(rx_fifo, XilinxSPIPS), 876 VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, XLNX_SPIPS_R_MAX), 877 VMSTATE_UINT8(snoop_state, XilinxSPIPS), 878 VMSTATE_END_OF_LIST() 879 } 880 }; 881 882 static Property xilinx_qspips_properties[] = { 883 /* We had to turn this off for 2.10 as it is not compatible with migration. 884 * It can be enabled but will prevent the device to be migrated. 885 * This will go aways when a fix will be released. 886 */ 887 DEFINE_PROP_BOOL("x-mmio-exec", XilinxQSPIPS, mmio_execution_enabled, 888 false), 889 DEFINE_PROP_END_OF_LIST(), 890 }; 891 892 static Property xilinx_spips_properties[] = { 893 DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1), 894 DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4), 895 DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1), 896 DEFINE_PROP_END_OF_LIST(), 897 }; 898 899 static void xilinx_qspips_class_init(ObjectClass *klass, void * data) 900 { 901 DeviceClass *dc = DEVICE_CLASS(klass); 902 XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 903 904 dc->realize = xilinx_qspips_realize; 905 dc->props = xilinx_qspips_properties; 906 xsc->reg_ops = &qspips_ops; 907 xsc->rx_fifo_size = RXFF_A_Q; 908 xsc->tx_fifo_size = TXFF_A_Q; 909 } 910 911 static void xilinx_spips_class_init(ObjectClass *klass, void *data) 912 { 913 DeviceClass *dc = DEVICE_CLASS(klass); 914 XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 915 916 dc->realize = xilinx_spips_realize; 917 dc->reset = xilinx_spips_reset; 918 dc->props = xilinx_spips_properties; 919 dc->vmsd = &vmstate_xilinx_spips; 920 921 xsc->reg_ops = &spips_ops; 922 xsc->rx_fifo_size = RXFF_A; 923 xsc->tx_fifo_size = TXFF_A; 924 } 925 926 static const TypeInfo xilinx_spips_info = { 927 .name = TYPE_XILINX_SPIPS, 928 .parent = TYPE_SYS_BUS_DEVICE, 929 .instance_size = sizeof(XilinxSPIPS), 930 .class_init = xilinx_spips_class_init, 931 .class_size = sizeof(XilinxSPIPSClass), 932 }; 933 934 static const TypeInfo xilinx_qspips_info = { 935 .name = TYPE_XILINX_QSPIPS, 936 .parent = TYPE_XILINX_SPIPS, 937 .instance_size = sizeof(XilinxQSPIPS), 938 .class_init = xilinx_qspips_class_init, 939 }; 940 941 static void xilinx_spips_register_types(void) 942 { 943 type_register_static(&xilinx_spips_info); 944 type_register_static(&xilinx_qspips_info); 945 } 946 947 type_init(xilinx_spips_register_types) 948