1 /* 2 * QEMU model of the Xilinx Zynq SPI controller 3 * 4 * Copyright (c) 2012 Peter A. G. Crosthwaite 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/sysbus.h" 27 #include "sysemu/sysemu.h" 28 #include "hw/ptimer.h" 29 #include "qemu/log.h" 30 #include "qemu/bitops.h" 31 #include "hw/ssi/xilinx_spips.h" 32 #include "qapi/error.h" 33 #include "hw/register.h" 34 #include "sysemu/dma.h" 35 #include "migration/blocker.h" 36 37 #ifndef XILINX_SPIPS_ERR_DEBUG 38 #define XILINX_SPIPS_ERR_DEBUG 0 39 #endif 40 41 #define DB_PRINT_L(level, ...) do { \ 42 if (XILINX_SPIPS_ERR_DEBUG > (level)) { \ 43 fprintf(stderr, ": %s: ", __func__); \ 44 fprintf(stderr, ## __VA_ARGS__); \ 45 } \ 46 } while (0); 47 48 /* config register */ 49 #define R_CONFIG (0x00 / 4) 50 #define IFMODE (1U << 31) 51 #define R_CONFIG_ENDIAN (1 << 26) 52 #define MODEFAIL_GEN_EN (1 << 17) 53 #define MAN_START_COM (1 << 16) 54 #define MAN_START_EN (1 << 15) 55 #define MANUAL_CS (1 << 14) 56 #define CS (0xF << 10) 57 #define CS_SHIFT (10) 58 #define PERI_SEL (1 << 9) 59 #define REF_CLK (1 << 8) 60 #define FIFO_WIDTH (3 << 6) 61 #define BAUD_RATE_DIV (7 << 3) 62 #define CLK_PH (1 << 2) 63 #define CLK_POL (1 << 1) 64 #define MODE_SEL (1 << 0) 65 #define R_CONFIG_RSVD (0x7bf40000) 66 67 /* interrupt mechanism */ 68 #define R_INTR_STATUS (0x04 / 4) 69 #define R_INTR_EN (0x08 / 4) 70 #define R_INTR_DIS (0x0C / 4) 71 #define R_INTR_MASK (0x10 / 4) 72 #define IXR_TX_FIFO_UNDERFLOW (1 << 6) 73 /* Poll timeout not implemented */ 74 #define IXR_RX_FIFO_EMPTY (1 << 11) 75 #define IXR_GENERIC_FIFO_FULL (1 << 10) 76 #define IXR_GENERIC_FIFO_NOT_FULL (1 << 9) 77 #define IXR_TX_FIFO_EMPTY (1 << 8) 78 #define IXR_GENERIC_FIFO_EMPTY (1 << 7) 79 #define IXR_RX_FIFO_FULL (1 << 5) 80 #define IXR_RX_FIFO_NOT_EMPTY (1 << 4) 81 #define IXR_TX_FIFO_FULL (1 << 3) 82 #define IXR_TX_FIFO_NOT_FULL (1 << 2) 83 #define IXR_TX_FIFO_MODE_FAIL (1 << 1) 84 #define IXR_RX_FIFO_OVERFLOW (1 << 0) 85 #define IXR_ALL ((1 << 13) - 1) 86 #define GQSPI_IXR_MASK 0xFBE 87 #define IXR_SELF_CLEAR \ 88 (IXR_GENERIC_FIFO_EMPTY \ 89 | IXR_GENERIC_FIFO_FULL \ 90 | IXR_GENERIC_FIFO_NOT_FULL \ 91 | IXR_TX_FIFO_EMPTY \ 92 | IXR_TX_FIFO_FULL \ 93 | IXR_TX_FIFO_NOT_FULL \ 94 | IXR_RX_FIFO_EMPTY \ 95 | IXR_RX_FIFO_FULL \ 96 | IXR_RX_FIFO_NOT_EMPTY) 97 98 #define R_EN (0x14 / 4) 99 #define R_DELAY (0x18 / 4) 100 #define R_TX_DATA (0x1C / 4) 101 #define R_RX_DATA (0x20 / 4) 102 #define R_SLAVE_IDLE_COUNT (0x24 / 4) 103 #define R_TX_THRES (0x28 / 4) 104 #define R_RX_THRES (0x2C / 4) 105 #define R_TXD1 (0x80 / 4) 106 #define R_TXD2 (0x84 / 4) 107 #define R_TXD3 (0x88 / 4) 108 109 #define R_LQSPI_CFG (0xa0 / 4) 110 #define R_LQSPI_CFG_RESET 0x03A002EB 111 #define LQSPI_CFG_LQ_MODE (1U << 31) 112 #define LQSPI_CFG_TWO_MEM (1 << 30) 113 #define LQSPI_CFG_SEP_BUS (1 << 29) 114 #define LQSPI_CFG_U_PAGE (1 << 28) 115 #define LQSPI_CFG_ADDR4 (1 << 27) 116 #define LQSPI_CFG_MODE_EN (1 << 25) 117 #define LQSPI_CFG_MODE_WIDTH 8 118 #define LQSPI_CFG_MODE_SHIFT 16 119 #define LQSPI_CFG_DUMMY_WIDTH 3 120 #define LQSPI_CFG_DUMMY_SHIFT 8 121 #define LQSPI_CFG_INST_CODE 0xFF 122 123 #define R_CMND (0xc0 / 4) 124 #define R_CMND_RXFIFO_DRAIN (1 << 19) 125 FIELD(CMND, PARTIAL_BYTE_LEN, 16, 3) 126 #define R_CMND_EXT_ADD (1 << 15) 127 FIELD(CMND, RX_DISCARD, 8, 7) 128 FIELD(CMND, DUMMY_CYCLES, 2, 6) 129 #define R_CMND_DMA_EN (1 << 1) 130 #define R_CMND_PUSH_WAIT (1 << 0) 131 #define R_TRANSFER_SIZE (0xc4 / 4) 132 #define R_LQSPI_STS (0xA4 / 4) 133 #define LQSPI_STS_WR_RECVD (1 << 1) 134 135 #define R_MOD_ID (0xFC / 4) 136 137 #define R_GQSPI_SELECT (0x144 / 4) 138 FIELD(GQSPI_SELECT, GENERIC_QSPI_EN, 0, 1) 139 #define R_GQSPI_ISR (0x104 / 4) 140 #define R_GQSPI_IER (0x108 / 4) 141 #define R_GQSPI_IDR (0x10c / 4) 142 #define R_GQSPI_IMR (0x110 / 4) 143 #define R_GQSPI_TX_THRESH (0x128 / 4) 144 #define R_GQSPI_RX_THRESH (0x12c / 4) 145 #define R_GQSPI_CNFG (0x100 / 4) 146 FIELD(GQSPI_CNFG, MODE_EN, 30, 2) 147 FIELD(GQSPI_CNFG, GEN_FIFO_START_MODE, 29, 1) 148 FIELD(GQSPI_CNFG, GEN_FIFO_START, 28, 1) 149 FIELD(GQSPI_CNFG, ENDIAN, 26, 1) 150 /* Poll timeout not implemented */ 151 FIELD(GQSPI_CNFG, EN_POLL_TIMEOUT, 20, 1) 152 /* QEMU doesnt care about any of these last three */ 153 FIELD(GQSPI_CNFG, BR, 3, 3) 154 FIELD(GQSPI_CNFG, CPH, 2, 1) 155 FIELD(GQSPI_CNFG, CPL, 1, 1) 156 #define R_GQSPI_GEN_FIFO (0x140 / 4) 157 #define R_GQSPI_TXD (0x11c / 4) 158 #define R_GQSPI_RXD (0x120 / 4) 159 #define R_GQSPI_FIFO_CTRL (0x14c / 4) 160 FIELD(GQSPI_FIFO_CTRL, RX_FIFO_RESET, 2, 1) 161 FIELD(GQSPI_FIFO_CTRL, TX_FIFO_RESET, 1, 1) 162 FIELD(GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET, 0, 1) 163 #define R_GQSPI_GFIFO_THRESH (0x150 / 4) 164 #define R_GQSPI_DATA_STS (0x15c / 4) 165 /* We use the snapshot register to hold the core state for the currently 166 * or most recently executed command. So the generic fifo format is defined 167 * for the snapshot register 168 */ 169 #define R_GQSPI_GF_SNAPSHOT (0x160 / 4) 170 FIELD(GQSPI_GF_SNAPSHOT, POLL, 19, 1) 171 FIELD(GQSPI_GF_SNAPSHOT, STRIPE, 18, 1) 172 FIELD(GQSPI_GF_SNAPSHOT, RECIEVE, 17, 1) 173 FIELD(GQSPI_GF_SNAPSHOT, TRANSMIT, 16, 1) 174 FIELD(GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT, 14, 2) 175 FIELD(GQSPI_GF_SNAPSHOT, CHIP_SELECT, 12, 2) 176 FIELD(GQSPI_GF_SNAPSHOT, SPI_MODE, 10, 2) 177 FIELD(GQSPI_GF_SNAPSHOT, EXPONENT, 9, 1) 178 FIELD(GQSPI_GF_SNAPSHOT, DATA_XFER, 8, 1) 179 FIELD(GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA, 0, 8) 180 #define R_GQSPI_MOD_ID (0x168 / 4) 181 #define R_GQSPI_MOD_ID_VALUE 0x010A0000 182 /* size of TXRX FIFOs */ 183 #define RXFF_A (128) 184 #define TXFF_A (128) 185 186 #define RXFF_A_Q (64 * 4) 187 #define TXFF_A_Q (64 * 4) 188 189 /* 16MB per linear region */ 190 #define LQSPI_ADDRESS_BITS 24 191 192 #define SNOOP_CHECKING 0xFF 193 #define SNOOP_ADDR 0xF0 194 #define SNOOP_NONE 0xEE 195 #define SNOOP_STRIPING 0 196 197 static inline int num_effective_busses(XilinxSPIPS *s) 198 { 199 return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && 200 s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1; 201 } 202 203 static void xilinx_spips_update_cs(XilinxSPIPS *s, int field) 204 { 205 int i; 206 207 for (i = 0; i < s->num_cs; i++) { 208 bool old_state = s->cs_lines_state[i]; 209 bool new_state = field & (1 << i); 210 211 if (old_state != new_state) { 212 s->cs_lines_state[i] = new_state; 213 s->rx_discard = ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD); 214 DB_PRINT_L(1, "%sselecting slave %d\n", new_state ? "" : "de", i); 215 } 216 qemu_set_irq(s->cs_lines[i], !new_state); 217 } 218 if (!(field & ((1 << s->num_cs) - 1))) { 219 s->snoop_state = SNOOP_CHECKING; 220 s->cmd_dummies = 0; 221 s->link_state = 1; 222 s->link_state_next = 1; 223 s->link_state_next_when = 0; 224 DB_PRINT_L(1, "moving to snoop check state\n"); 225 } 226 } 227 228 static void xlnx_zynqmp_qspips_update_cs_lines(XlnxZynqMPQSPIPS *s) 229 { 230 if (s->regs[R_GQSPI_GF_SNAPSHOT]) { 231 int field = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, CHIP_SELECT); 232 xilinx_spips_update_cs(XILINX_SPIPS(s), field); 233 } 234 } 235 236 static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) 237 { 238 int field = ~((s->regs[R_CONFIG] & CS) >> CS_SHIFT); 239 240 /* In dual parallel, mirror low CS to both */ 241 if (num_effective_busses(s) == 2) { 242 /* Single bit chip-select for qspi */ 243 field &= 0x1; 244 field |= field << 1; 245 /* Dual stack U-Page */ 246 } else if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM && 247 s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE) { 248 /* Single bit chip-select for qspi */ 249 field &= 0x1; 250 /* change from CS0 to CS1 */ 251 field <<= 1; 252 } 253 /* Auto CS */ 254 if (!(s->regs[R_CONFIG] & MANUAL_CS) && 255 fifo8_is_empty(&s->tx_fifo)) { 256 field = 0; 257 } 258 xilinx_spips_update_cs(s, field); 259 } 260 261 static void xilinx_spips_update_ixr(XilinxSPIPS *s) 262 { 263 if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { 264 s->regs[R_INTR_STATUS] &= ~IXR_SELF_CLEAR; 265 s->regs[R_INTR_STATUS] |= 266 (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) | 267 (s->rx_fifo.num >= s->regs[R_RX_THRES] ? 268 IXR_RX_FIFO_NOT_EMPTY : 0) | 269 (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | 270 (fifo8_is_empty(&s->tx_fifo) ? IXR_TX_FIFO_EMPTY : 0) | 271 (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0); 272 } 273 int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] & 274 IXR_ALL); 275 if (new_irqline != s->irqline) { 276 s->irqline = new_irqline; 277 qemu_set_irq(s->irq, s->irqline); 278 } 279 } 280 281 static void xlnx_zynqmp_qspips_update_ixr(XlnxZynqMPQSPIPS *s) 282 { 283 uint32_t gqspi_int; 284 int new_irqline; 285 286 s->regs[R_GQSPI_ISR] &= ~IXR_SELF_CLEAR; 287 s->regs[R_GQSPI_ISR] |= 288 (fifo32_is_empty(&s->fifo_g) ? IXR_GENERIC_FIFO_EMPTY : 0) | 289 (fifo32_is_full(&s->fifo_g) ? IXR_GENERIC_FIFO_FULL : 0) | 290 (s->fifo_g.fifo.num < s->regs[R_GQSPI_GFIFO_THRESH] ? 291 IXR_GENERIC_FIFO_NOT_FULL : 0) | 292 (fifo8_is_empty(&s->rx_fifo_g) ? IXR_RX_FIFO_EMPTY : 0) | 293 (fifo8_is_full(&s->rx_fifo_g) ? IXR_RX_FIFO_FULL : 0) | 294 (s->rx_fifo_g.num >= s->regs[R_GQSPI_RX_THRESH] ? 295 IXR_RX_FIFO_NOT_EMPTY : 0) | 296 (fifo8_is_empty(&s->tx_fifo_g) ? IXR_TX_FIFO_EMPTY : 0) | 297 (fifo8_is_full(&s->tx_fifo_g) ? IXR_TX_FIFO_FULL : 0) | 298 (s->tx_fifo_g.num < s->regs[R_GQSPI_TX_THRESH] ? 299 IXR_TX_FIFO_NOT_FULL : 0); 300 301 /* GQSPI Interrupt Trigger Status */ 302 gqspi_int = (~s->regs[R_GQSPI_IMR]) & s->regs[R_GQSPI_ISR] & GQSPI_IXR_MASK; 303 new_irqline = !!(gqspi_int & IXR_ALL); 304 305 /* drive external interrupt pin */ 306 if (new_irqline != s->gqspi_irqline) { 307 s->gqspi_irqline = new_irqline; 308 qemu_set_irq(XILINX_SPIPS(s)->irq, s->gqspi_irqline); 309 } 310 } 311 312 static void xilinx_spips_reset(DeviceState *d) 313 { 314 XilinxSPIPS *s = XILINX_SPIPS(d); 315 316 int i; 317 for (i = 0; i < XLNX_SPIPS_R_MAX; i++) { 318 s->regs[i] = 0; 319 } 320 321 fifo8_reset(&s->rx_fifo); 322 fifo8_reset(&s->rx_fifo); 323 /* non zero resets */ 324 s->regs[R_CONFIG] |= MODEFAIL_GEN_EN; 325 s->regs[R_SLAVE_IDLE_COUNT] = 0xFF; 326 s->regs[R_TX_THRES] = 1; 327 s->regs[R_RX_THRES] = 1; 328 /* FIXME: move magic number definition somewhere sensible */ 329 s->regs[R_MOD_ID] = 0x01090106; 330 s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET; 331 s->link_state = 1; 332 s->link_state_next = 1; 333 s->link_state_next_when = 0; 334 s->snoop_state = SNOOP_CHECKING; 335 s->cmd_dummies = 0; 336 s->man_start_com = false; 337 xilinx_spips_update_ixr(s); 338 xilinx_spips_update_cs_lines(s); 339 } 340 341 static void xlnx_zynqmp_qspips_reset(DeviceState *d) 342 { 343 XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(d); 344 int i; 345 346 xilinx_spips_reset(d); 347 348 for (i = 0; i < XLNX_ZYNQMP_SPIPS_R_MAX; i++) { 349 s->regs[i] = 0; 350 } 351 fifo8_reset(&s->rx_fifo_g); 352 fifo8_reset(&s->rx_fifo_g); 353 fifo32_reset(&s->fifo_g); 354 s->regs[R_GQSPI_TX_THRESH] = 1; 355 s->regs[R_GQSPI_RX_THRESH] = 1; 356 s->regs[R_GQSPI_GFIFO_THRESH] = 1; 357 s->regs[R_GQSPI_IMR] = GQSPI_IXR_MASK; 358 s->man_start_com_g = false; 359 s->gqspi_irqline = 0; 360 xlnx_zynqmp_qspips_update_ixr(s); 361 } 362 363 /* N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) 364 * column wise (from element 0 to N-1). num is the length of x, and dir 365 * reverses the direction of the transform. Best illustrated by example: 366 * Each digit in the below array is a single bit (num == 3): 367 * 368 * {{ 76543210, } ----- stripe (dir == false) -----> {{ 741gdaFC, } 369 * { hgfedcba, } { 630fcHEB, } 370 * { HGFEDCBA, }} <---- upstripe (dir == true) ----- { 52hebGDA, }} 371 */ 372 373 static inline void stripe8(uint8_t *x, int num, bool dir) 374 { 375 uint8_t r[num]; 376 memset(r, 0, sizeof(uint8_t) * num); 377 int idx[2] = {0, 0}; 378 int bit[2] = {0, 7}; 379 int d = dir; 380 381 for (idx[0] = 0; idx[0] < num; ++idx[0]) { 382 for (bit[0] = 7; bit[0] >= 0; bit[0]--) { 383 r[idx[!d]] |= x[idx[d]] & 1 << bit[d] ? 1 << bit[!d] : 0; 384 idx[1] = (idx[1] + 1) % num; 385 if (!idx[1]) { 386 bit[1]--; 387 } 388 } 389 } 390 memcpy(x, r, sizeof(uint8_t) * num); 391 } 392 393 static void xlnx_zynqmp_qspips_flush_fifo_g(XlnxZynqMPQSPIPS *s) 394 { 395 while (s->regs[R_GQSPI_DATA_STS] || !fifo32_is_empty(&s->fifo_g)) { 396 uint8_t tx_rx[2] = { 0 }; 397 int num_stripes = 1; 398 uint8_t busses; 399 int i; 400 401 if (!s->regs[R_GQSPI_DATA_STS]) { 402 uint8_t imm; 403 404 s->regs[R_GQSPI_GF_SNAPSHOT] = fifo32_pop(&s->fifo_g); 405 DB_PRINT_L(0, "GQSPI command: %x\n", s->regs[R_GQSPI_GF_SNAPSHOT]); 406 if (!s->regs[R_GQSPI_GF_SNAPSHOT]) { 407 DB_PRINT_L(0, "Dummy GQSPI Delay Command Entry, Do nothing"); 408 continue; 409 } 410 xlnx_zynqmp_qspips_update_cs_lines(s); 411 412 imm = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA); 413 if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) { 414 /* immedate transfer */ 415 if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) || 416 ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) { 417 s->regs[R_GQSPI_DATA_STS] = 1; 418 /* CS setup/hold - do nothing */ 419 } else { 420 s->regs[R_GQSPI_DATA_STS] = 0; 421 } 422 } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, EXPONENT)) { 423 if (imm > 31) { 424 qemu_log_mask(LOG_UNIMP, "QSPI exponential transfer too" 425 " long - 2 ^ %" PRId8 " requested\n", imm); 426 } 427 s->regs[R_GQSPI_DATA_STS] = 1ul << imm; 428 } else { 429 s->regs[R_GQSPI_DATA_STS] = imm; 430 } 431 } 432 /* Zero length transfer check */ 433 if (!s->regs[R_GQSPI_DATA_STS]) { 434 continue; 435 } 436 if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE) && 437 fifo8_is_full(&s->rx_fifo_g)) { 438 /* No space in RX fifo for transfer - try again later */ 439 return; 440 } 441 if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, STRIPE) && 442 (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) || 443 ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE))) { 444 num_stripes = 2; 445 } 446 if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) { 447 tx_rx[0] = ARRAY_FIELD_EX32(s->regs, 448 GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA); 449 } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT)) { 450 for (i = 0; i < num_stripes; ++i) { 451 if (!fifo8_is_empty(&s->tx_fifo_g)) { 452 tx_rx[i] = fifo8_pop(&s->tx_fifo_g); 453 s->tx_fifo_g_align++; 454 } else { 455 return; 456 } 457 } 458 } 459 if (num_stripes == 1) { 460 /* mirror */ 461 tx_rx[1] = tx_rx[0]; 462 } 463 busses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT); 464 for (i = 0; i < 2; ++i) { 465 DB_PRINT_L(1, "bus %d tx = %02x\n", i, tx_rx[i]); 466 tx_rx[i] = ssi_transfer(XILINX_SPIPS(s)->spi[i], tx_rx[i]); 467 DB_PRINT_L(1, "bus %d rx = %02x\n", i, tx_rx[i]); 468 } 469 if (s->regs[R_GQSPI_DATA_STS] > 1 && 470 busses == 0x3 && num_stripes == 2) { 471 s->regs[R_GQSPI_DATA_STS] -= 2; 472 } else if (s->regs[R_GQSPI_DATA_STS] > 0) { 473 s->regs[R_GQSPI_DATA_STS]--; 474 } 475 if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) { 476 for (i = 0; i < 2; ++i) { 477 if (busses & (1 << i)) { 478 DB_PRINT_L(1, "bus %d push_byte = %02x\n", i, tx_rx[i]); 479 fifo8_push(&s->rx_fifo_g, tx_rx[i]); 480 s->rx_fifo_g_align++; 481 } 482 } 483 } 484 if (!s->regs[R_GQSPI_DATA_STS]) { 485 for (; s->tx_fifo_g_align % 4; s->tx_fifo_g_align++) { 486 fifo8_pop(&s->tx_fifo_g); 487 } 488 for (; s->rx_fifo_g_align % 4; s->rx_fifo_g_align++) { 489 fifo8_push(&s->rx_fifo_g, 0); 490 } 491 } 492 } 493 } 494 495 static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command) 496 { 497 if (!qs) { 498 /* The SPI device is not a QSPI device */ 499 return -1; 500 } 501 502 switch (command) { /* check for dummies */ 503 case READ: /* no dummy bytes/cycles */ 504 case PP: 505 case DPP: 506 case QPP: 507 case READ_4: 508 case PP_4: 509 case QPP_4: 510 return 0; 511 case FAST_READ: 512 case DOR: 513 case QOR: 514 case DOR_4: 515 case QOR_4: 516 return 1; 517 case DIOR: 518 case FAST_READ_4: 519 case DIOR_4: 520 return 2; 521 case QIOR: 522 case QIOR_4: 523 return 5; 524 default: 525 return -1; 526 } 527 } 528 529 static inline uint8_t get_addr_length(XilinxSPIPS *s, uint8_t cmd) 530 { 531 switch (cmd) { 532 case PP_4: 533 case QPP_4: 534 case READ_4: 535 case QIOR_4: 536 case FAST_READ_4: 537 case DOR_4: 538 case QOR_4: 539 case DIOR_4: 540 return 4; 541 default: 542 return (s->regs[R_CMND] & R_CMND_EXT_ADD) ? 4 : 3; 543 } 544 } 545 546 static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) 547 { 548 int debug_level = 0; 549 XilinxQSPIPS *q = (XilinxQSPIPS *) object_dynamic_cast(OBJECT(s), 550 TYPE_XILINX_QSPIPS); 551 552 for (;;) { 553 int i; 554 uint8_t tx = 0; 555 uint8_t tx_rx[num_effective_busses(s)]; 556 uint8_t dummy_cycles = 0; 557 uint8_t addr_length; 558 559 if (fifo8_is_empty(&s->tx_fifo)) { 560 xilinx_spips_update_ixr(s); 561 return; 562 } else if (s->snoop_state == SNOOP_STRIPING) { 563 for (i = 0; i < num_effective_busses(s); ++i) { 564 tx_rx[i] = fifo8_pop(&s->tx_fifo); 565 } 566 stripe8(tx_rx, num_effective_busses(s), false); 567 } else if (s->snoop_state >= SNOOP_ADDR) { 568 tx = fifo8_pop(&s->tx_fifo); 569 for (i = 0; i < num_effective_busses(s); ++i) { 570 tx_rx[i] = tx; 571 } 572 } else { 573 /* Extract a dummy byte and generate dummy cycles according to the 574 * link state */ 575 tx = fifo8_pop(&s->tx_fifo); 576 dummy_cycles = 8 / s->link_state; 577 } 578 579 for (i = 0; i < num_effective_busses(s); ++i) { 580 int bus = num_effective_busses(s) - 1 - i; 581 if (dummy_cycles) { 582 int d; 583 for (d = 0; d < dummy_cycles; ++d) { 584 tx_rx[0] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[0]); 585 } 586 } else { 587 DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]); 588 tx_rx[i] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]); 589 DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]); 590 } 591 } 592 593 if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { 594 DB_PRINT_L(debug_level, "dircarding drained rx byte\n"); 595 /* Do nothing */ 596 } else if (s->rx_discard) { 597 DB_PRINT_L(debug_level, "dircarding discarded rx byte\n"); 598 s->rx_discard -= 8 / s->link_state; 599 } else if (fifo8_is_full(&s->rx_fifo)) { 600 s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW; 601 DB_PRINT_L(0, "rx FIFO overflow"); 602 } else if (s->snoop_state == SNOOP_STRIPING) { 603 stripe8(tx_rx, num_effective_busses(s), true); 604 for (i = 0; i < num_effective_busses(s); ++i) { 605 fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]); 606 DB_PRINT_L(debug_level, "pushing striped rx byte\n"); 607 } 608 } else { 609 DB_PRINT_L(debug_level, "pushing unstriped rx byte\n"); 610 fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]); 611 } 612 613 if (s->link_state_next_when) { 614 s->link_state_next_when--; 615 if (!s->link_state_next_when) { 616 s->link_state = s->link_state_next; 617 } 618 } 619 620 DB_PRINT_L(debug_level, "initial snoop state: %x\n", 621 (unsigned)s->snoop_state); 622 switch (s->snoop_state) { 623 case (SNOOP_CHECKING): 624 /* Store the count of dummy bytes in the txfifo */ 625 s->cmd_dummies = xilinx_spips_num_dummies(q, tx); 626 addr_length = get_addr_length(s, tx); 627 if (s->cmd_dummies < 0) { 628 s->snoop_state = SNOOP_NONE; 629 } else { 630 s->snoop_state = SNOOP_ADDR + addr_length - 1; 631 } 632 switch (tx) { 633 case DPP: 634 case DOR: 635 case DOR_4: 636 s->link_state_next = 2; 637 s->link_state_next_when = addr_length + s->cmd_dummies; 638 break; 639 case QPP: 640 case QPP_4: 641 case QOR: 642 case QOR_4: 643 s->link_state_next = 4; 644 s->link_state_next_when = addr_length + s->cmd_dummies; 645 break; 646 case DIOR: 647 case DIOR_4: 648 s->link_state = 2; 649 break; 650 case QIOR: 651 case QIOR_4: 652 s->link_state = 4; 653 break; 654 } 655 break; 656 case (SNOOP_ADDR): 657 /* Address has been transmitted, transmit dummy cycles now if 658 * needed */ 659 if (s->cmd_dummies < 0) { 660 s->snoop_state = SNOOP_NONE; 661 } else { 662 s->snoop_state = s->cmd_dummies; 663 } 664 break; 665 case (SNOOP_STRIPING): 666 case (SNOOP_NONE): 667 /* Once we hit the boring stuff - squelch debug noise */ 668 if (!debug_level) { 669 DB_PRINT_L(0, "squelching debug info ....\n"); 670 debug_level = 1; 671 } 672 break; 673 default: 674 s->snoop_state--; 675 } 676 DB_PRINT_L(debug_level, "final snoop state: %x\n", 677 (unsigned)s->snoop_state); 678 } 679 } 680 681 static inline void tx_data_bytes(Fifo8 *fifo, uint32_t value, int num, bool be) 682 { 683 int i; 684 for (i = 0; i < num && !fifo8_is_full(fifo); ++i) { 685 if (be) { 686 fifo8_push(fifo, (uint8_t)(value >> 24)); 687 value <<= 8; 688 } else { 689 fifo8_push(fifo, (uint8_t)value); 690 value >>= 8; 691 } 692 } 693 } 694 695 static void xilinx_spips_check_zero_pump(XilinxSPIPS *s) 696 { 697 if (!s->regs[R_TRANSFER_SIZE]) { 698 return; 699 } 700 if (!fifo8_is_empty(&s->tx_fifo) && s->regs[R_CMND] & R_CMND_PUSH_WAIT) { 701 return; 702 } 703 /* 704 * The zero pump must never fill tx fifo such that rx overflow is 705 * possible 706 */ 707 while (s->regs[R_TRANSFER_SIZE] && 708 s->rx_fifo.num + s->tx_fifo.num < RXFF_A_Q - 3) { 709 /* endianess just doesn't matter when zero pumping */ 710 tx_data_bytes(&s->tx_fifo, 0, 4, false); 711 s->regs[R_TRANSFER_SIZE] &= ~0x03ull; 712 s->regs[R_TRANSFER_SIZE] -= 4; 713 } 714 } 715 716 static void xilinx_spips_check_flush(XilinxSPIPS *s) 717 { 718 if (s->man_start_com || 719 (!fifo8_is_empty(&s->tx_fifo) && 720 !(s->regs[R_CONFIG] & MAN_START_EN))) { 721 xilinx_spips_check_zero_pump(s); 722 xilinx_spips_flush_txfifo(s); 723 } 724 if (fifo8_is_empty(&s->tx_fifo) && !s->regs[R_TRANSFER_SIZE]) { 725 s->man_start_com = false; 726 } 727 xilinx_spips_update_ixr(s); 728 } 729 730 static void xlnx_zynqmp_qspips_check_flush(XlnxZynqMPQSPIPS *s) 731 { 732 bool gqspi_has_work = s->regs[R_GQSPI_DATA_STS] || 733 !fifo32_is_empty(&s->fifo_g); 734 735 if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) { 736 if (s->man_start_com_g || (gqspi_has_work && 737 !ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE))) { 738 xlnx_zynqmp_qspips_flush_fifo_g(s); 739 } 740 } else { 741 xilinx_spips_check_flush(XILINX_SPIPS(s)); 742 } 743 if (!gqspi_has_work) { 744 s->man_start_com_g = false; 745 } 746 xlnx_zynqmp_qspips_update_ixr(s); 747 } 748 749 static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max) 750 { 751 int i; 752 753 for (i = 0; i < max && !fifo8_is_empty(fifo); ++i) { 754 value[i] = fifo8_pop(fifo); 755 } 756 return max - i; 757 } 758 759 static const void *pop_buf(Fifo8 *fifo, uint32_t max, uint32_t *num) 760 { 761 void *ret; 762 763 if (max == 0 || max > fifo->num) { 764 abort(); 765 } 766 *num = MIN(fifo->capacity - fifo->head, max); 767 ret = &fifo->data[fifo->head]; 768 fifo->head += *num; 769 fifo->head %= fifo->capacity; 770 fifo->num -= *num; 771 return ret; 772 } 773 774 static void xlnx_zynqmp_qspips_notify(void *opaque) 775 { 776 XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(opaque); 777 XilinxSPIPS *s = XILINX_SPIPS(rq); 778 Fifo8 *recv_fifo; 779 780 if (ARRAY_FIELD_EX32(rq->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) { 781 if (!(ARRAY_FIELD_EX32(rq->regs, GQSPI_CNFG, MODE_EN) == 2)) { 782 return; 783 } 784 recv_fifo = &rq->rx_fifo_g; 785 } else { 786 if (!(s->regs[R_CMND] & R_CMND_DMA_EN)) { 787 return; 788 } 789 recv_fifo = &s->rx_fifo; 790 } 791 while (recv_fifo->num >= 4 792 && stream_can_push(rq->dma, xlnx_zynqmp_qspips_notify, rq)) 793 { 794 size_t ret; 795 uint32_t num; 796 const void *rxd = pop_buf(recv_fifo, 4, &num); 797 798 memcpy(rq->dma_buf, rxd, num); 799 800 ret = stream_push(rq->dma, rq->dma_buf, 4); 801 assert(ret == 4); 802 xlnx_zynqmp_qspips_check_flush(rq); 803 } 804 } 805 806 static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, 807 unsigned size) 808 { 809 XilinxSPIPS *s = opaque; 810 uint32_t mask = ~0; 811 uint32_t ret; 812 uint8_t rx_buf[4]; 813 int shortfall; 814 815 addr >>= 2; 816 switch (addr) { 817 case R_CONFIG: 818 mask = ~(R_CONFIG_RSVD | MAN_START_COM); 819 break; 820 case R_INTR_STATUS: 821 ret = s->regs[addr] & IXR_ALL; 822 s->regs[addr] = 0; 823 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 824 xilinx_spips_update_ixr(s); 825 return ret; 826 case R_INTR_MASK: 827 mask = IXR_ALL; 828 break; 829 case R_EN: 830 mask = 0x1; 831 break; 832 case R_SLAVE_IDLE_COUNT: 833 mask = 0xFF; 834 break; 835 case R_MOD_ID: 836 mask = 0x01FFFFFF; 837 break; 838 case R_INTR_EN: 839 case R_INTR_DIS: 840 case R_TX_DATA: 841 mask = 0; 842 break; 843 case R_RX_DATA: 844 memset(rx_buf, 0, sizeof(rx_buf)); 845 shortfall = rx_data_bytes(&s->rx_fifo, rx_buf, s->num_txrx_bytes); 846 ret = s->regs[R_CONFIG] & R_CONFIG_ENDIAN ? 847 cpu_to_be32(*(uint32_t *)rx_buf) : 848 cpu_to_le32(*(uint32_t *)rx_buf); 849 if (!(s->regs[R_CONFIG] & R_CONFIG_ENDIAN)) { 850 ret <<= 8 * shortfall; 851 } 852 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 853 xilinx_spips_check_flush(s); 854 xilinx_spips_update_ixr(s); 855 return ret; 856 } 857 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, 858 s->regs[addr] & mask); 859 return s->regs[addr] & mask; 860 861 } 862 863 static uint64_t xlnx_zynqmp_qspips_read(void *opaque, 864 hwaddr addr, unsigned size) 865 { 866 XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(opaque); 867 uint32_t reg = addr / 4; 868 uint32_t ret; 869 uint8_t rx_buf[4]; 870 int shortfall; 871 872 if (reg <= R_MOD_ID) { 873 return xilinx_spips_read(opaque, addr, size); 874 } else { 875 switch (reg) { 876 case R_GQSPI_RXD: 877 if (fifo8_is_empty(&s->rx_fifo_g)) { 878 qemu_log_mask(LOG_GUEST_ERROR, 879 "Read from empty GQSPI RX FIFO\n"); 880 return 0; 881 } 882 memset(rx_buf, 0, sizeof(rx_buf)); 883 shortfall = rx_data_bytes(&s->rx_fifo_g, rx_buf, 884 XILINX_SPIPS(s)->num_txrx_bytes); 885 ret = ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN) ? 886 cpu_to_be32(*(uint32_t *)rx_buf) : 887 cpu_to_le32(*(uint32_t *)rx_buf); 888 if (!ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN)) { 889 ret <<= 8 * shortfall; 890 } 891 xlnx_zynqmp_qspips_check_flush(s); 892 xlnx_zynqmp_qspips_update_ixr(s); 893 return ret; 894 default: 895 return s->regs[reg]; 896 } 897 } 898 } 899 900 static void xilinx_spips_write(void *opaque, hwaddr addr, 901 uint64_t value, unsigned size) 902 { 903 int mask = ~0; 904 XilinxSPIPS *s = opaque; 905 906 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value); 907 addr >>= 2; 908 switch (addr) { 909 case R_CONFIG: 910 mask = ~(R_CONFIG_RSVD | MAN_START_COM); 911 if ((value & MAN_START_COM) && (s->regs[R_CONFIG] & MAN_START_EN)) { 912 s->man_start_com = true; 913 } 914 break; 915 case R_INTR_STATUS: 916 mask = IXR_ALL; 917 s->regs[R_INTR_STATUS] &= ~(mask & value); 918 goto no_reg_update; 919 case R_INTR_DIS: 920 mask = IXR_ALL; 921 s->regs[R_INTR_MASK] &= ~(mask & value); 922 goto no_reg_update; 923 case R_INTR_EN: 924 mask = IXR_ALL; 925 s->regs[R_INTR_MASK] |= mask & value; 926 goto no_reg_update; 927 case R_EN: 928 mask = 0x1; 929 break; 930 case R_SLAVE_IDLE_COUNT: 931 mask = 0xFF; 932 break; 933 case R_RX_DATA: 934 case R_INTR_MASK: 935 case R_MOD_ID: 936 mask = 0; 937 break; 938 case R_TX_DATA: 939 tx_data_bytes(&s->tx_fifo, (uint32_t)value, s->num_txrx_bytes, 940 s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 941 goto no_reg_update; 942 case R_TXD1: 943 tx_data_bytes(&s->tx_fifo, (uint32_t)value, 1, 944 s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 945 goto no_reg_update; 946 case R_TXD2: 947 tx_data_bytes(&s->tx_fifo, (uint32_t)value, 2, 948 s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 949 goto no_reg_update; 950 case R_TXD3: 951 tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3, 952 s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 953 goto no_reg_update; 954 } 955 s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); 956 no_reg_update: 957 xilinx_spips_update_cs_lines(s); 958 xilinx_spips_check_flush(s); 959 xilinx_spips_update_cs_lines(s); 960 xilinx_spips_update_ixr(s); 961 } 962 963 static const MemoryRegionOps spips_ops = { 964 .read = xilinx_spips_read, 965 .write = xilinx_spips_write, 966 .endianness = DEVICE_LITTLE_ENDIAN, 967 }; 968 969 static void xilinx_qspips_invalidate_mmio_ptr(XilinxQSPIPS *q) 970 { 971 XilinxSPIPS *s = &q->parent_obj; 972 973 if ((q->mmio_execution_enabled) && (q->lqspi_cached_addr != ~0ULL)) { 974 /* Invalidate the current mapped mmio */ 975 memory_region_invalidate_mmio_ptr(&s->mmlqspi, q->lqspi_cached_addr, 976 LQSPI_CACHE_SIZE); 977 } 978 979 q->lqspi_cached_addr = ~0ULL; 980 } 981 982 static void xilinx_qspips_write(void *opaque, hwaddr addr, 983 uint64_t value, unsigned size) 984 { 985 XilinxQSPIPS *q = XILINX_QSPIPS(opaque); 986 XilinxSPIPS *s = XILINX_SPIPS(opaque); 987 988 xilinx_spips_write(opaque, addr, value, size); 989 addr >>= 2; 990 991 if (addr == R_LQSPI_CFG) { 992 xilinx_qspips_invalidate_mmio_ptr(q); 993 } 994 if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { 995 fifo8_reset(&s->rx_fifo); 996 } 997 } 998 999 static void xlnx_zynqmp_qspips_write(void *opaque, hwaddr addr, 1000 uint64_t value, unsigned size) 1001 { 1002 XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(opaque); 1003 uint32_t reg = addr / 4; 1004 1005 if (reg <= R_MOD_ID) { 1006 xilinx_qspips_write(opaque, addr, value, size); 1007 } else { 1008 switch (reg) { 1009 case R_GQSPI_CNFG: 1010 if (FIELD_EX32(value, GQSPI_CNFG, GEN_FIFO_START) && 1011 ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE)) { 1012 s->man_start_com_g = true; 1013 } 1014 s->regs[reg] = value & ~(R_GQSPI_CNFG_GEN_FIFO_START_MASK); 1015 break; 1016 case R_GQSPI_GEN_FIFO: 1017 if (!fifo32_is_full(&s->fifo_g)) { 1018 fifo32_push(&s->fifo_g, value); 1019 } 1020 break; 1021 case R_GQSPI_TXD: 1022 tx_data_bytes(&s->tx_fifo_g, (uint32_t)value, 4, 1023 ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN)); 1024 break; 1025 case R_GQSPI_FIFO_CTRL: 1026 if (FIELD_EX32(value, GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET)) { 1027 fifo32_reset(&s->fifo_g); 1028 } 1029 if (FIELD_EX32(value, GQSPI_FIFO_CTRL, TX_FIFO_RESET)) { 1030 fifo8_reset(&s->tx_fifo_g); 1031 } 1032 if (FIELD_EX32(value, GQSPI_FIFO_CTRL, RX_FIFO_RESET)) { 1033 fifo8_reset(&s->rx_fifo_g); 1034 } 1035 break; 1036 case R_GQSPI_IDR: 1037 s->regs[R_GQSPI_IMR] |= value; 1038 break; 1039 case R_GQSPI_IER: 1040 s->regs[R_GQSPI_IMR] &= ~value; 1041 break; 1042 case R_GQSPI_ISR: 1043 s->regs[R_GQSPI_ISR] &= ~value; 1044 break; 1045 case R_GQSPI_IMR: 1046 case R_GQSPI_RXD: 1047 case R_GQSPI_GF_SNAPSHOT: 1048 case R_GQSPI_MOD_ID: 1049 break; 1050 default: 1051 s->regs[reg] = value; 1052 break; 1053 } 1054 xlnx_zynqmp_qspips_update_cs_lines(s); 1055 xlnx_zynqmp_qspips_check_flush(s); 1056 xlnx_zynqmp_qspips_update_cs_lines(s); 1057 xlnx_zynqmp_qspips_update_ixr(s); 1058 } 1059 xlnx_zynqmp_qspips_notify(s); 1060 } 1061 1062 static const MemoryRegionOps qspips_ops = { 1063 .read = xilinx_spips_read, 1064 .write = xilinx_qspips_write, 1065 .endianness = DEVICE_LITTLE_ENDIAN, 1066 }; 1067 1068 static const MemoryRegionOps xlnx_zynqmp_qspips_ops = { 1069 .read = xlnx_zynqmp_qspips_read, 1070 .write = xlnx_zynqmp_qspips_write, 1071 .endianness = DEVICE_LITTLE_ENDIAN, 1072 }; 1073 1074 #define LQSPI_CACHE_SIZE 1024 1075 1076 static void lqspi_load_cache(void *opaque, hwaddr addr) 1077 { 1078 XilinxQSPIPS *q = opaque; 1079 XilinxSPIPS *s = opaque; 1080 int i; 1081 int flash_addr = ((addr & ~(LQSPI_CACHE_SIZE - 1)) 1082 / num_effective_busses(s)); 1083 int slave = flash_addr >> LQSPI_ADDRESS_BITS; 1084 int cache_entry = 0; 1085 uint32_t u_page_save = s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE; 1086 1087 if (addr < q->lqspi_cached_addr || 1088 addr > q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { 1089 xilinx_qspips_invalidate_mmio_ptr(q); 1090 s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 1091 s->regs[R_LQSPI_STS] |= slave ? LQSPI_CFG_U_PAGE : 0; 1092 1093 DB_PRINT_L(0, "config reg status: %08x\n", s->regs[R_LQSPI_CFG]); 1094 1095 fifo8_reset(&s->tx_fifo); 1096 fifo8_reset(&s->rx_fifo); 1097 1098 /* instruction */ 1099 DB_PRINT_L(0, "pushing read instruction: %02x\n", 1100 (unsigned)(uint8_t)(s->regs[R_LQSPI_CFG] & 1101 LQSPI_CFG_INST_CODE)); 1102 fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE); 1103 /* read address */ 1104 DB_PRINT_L(0, "pushing read address %06x\n", flash_addr); 1105 if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_ADDR4) { 1106 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 24)); 1107 } 1108 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16)); 1109 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8)); 1110 fifo8_push(&s->tx_fifo, (uint8_t)flash_addr); 1111 /* mode bits */ 1112 if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) { 1113 fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG], 1114 LQSPI_CFG_MODE_SHIFT, 1115 LQSPI_CFG_MODE_WIDTH)); 1116 } 1117 /* dummy bytes */ 1118 for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT, 1119 LQSPI_CFG_DUMMY_WIDTH)); ++i) { 1120 DB_PRINT_L(0, "pushing dummy byte\n"); 1121 fifo8_push(&s->tx_fifo, 0); 1122 } 1123 xilinx_spips_update_cs_lines(s); 1124 xilinx_spips_flush_txfifo(s); 1125 fifo8_reset(&s->rx_fifo); 1126 1127 DB_PRINT_L(0, "starting QSPI data read\n"); 1128 1129 while (cache_entry < LQSPI_CACHE_SIZE) { 1130 for (i = 0; i < 64; ++i) { 1131 tx_data_bytes(&s->tx_fifo, 0, 1, false); 1132 } 1133 xilinx_spips_flush_txfifo(s); 1134 for (i = 0; i < 64; ++i) { 1135 rx_data_bytes(&s->rx_fifo, &q->lqspi_buf[cache_entry++], 1); 1136 } 1137 } 1138 1139 s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 1140 s->regs[R_LQSPI_STS] |= u_page_save; 1141 xilinx_spips_update_cs_lines(s); 1142 1143 q->lqspi_cached_addr = flash_addr * num_effective_busses(s); 1144 } 1145 } 1146 1147 static void *lqspi_request_mmio_ptr(void *opaque, hwaddr addr, unsigned *size, 1148 unsigned *offset) 1149 { 1150 XilinxQSPIPS *q = opaque; 1151 hwaddr offset_within_the_region; 1152 1153 if (!q->mmio_execution_enabled) { 1154 return NULL; 1155 } 1156 1157 offset_within_the_region = addr & ~(LQSPI_CACHE_SIZE - 1); 1158 lqspi_load_cache(opaque, offset_within_the_region); 1159 *size = LQSPI_CACHE_SIZE; 1160 *offset = offset_within_the_region; 1161 return q->lqspi_buf; 1162 } 1163 1164 static uint64_t 1165 lqspi_read(void *opaque, hwaddr addr, unsigned int size) 1166 { 1167 XilinxQSPIPS *q = opaque; 1168 uint32_t ret; 1169 1170 if (addr >= q->lqspi_cached_addr && 1171 addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { 1172 uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr]; 1173 ret = cpu_to_le32(*(uint32_t *)retp); 1174 DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr, 1175 (unsigned)ret); 1176 return ret; 1177 } else { 1178 lqspi_load_cache(opaque, addr); 1179 return lqspi_read(opaque, addr, size); 1180 } 1181 } 1182 1183 static const MemoryRegionOps lqspi_ops = { 1184 .read = lqspi_read, 1185 .request_ptr = lqspi_request_mmio_ptr, 1186 .endianness = DEVICE_NATIVE_ENDIAN, 1187 .valid = { 1188 .min_access_size = 1, 1189 .max_access_size = 4 1190 } 1191 }; 1192 1193 static void xilinx_spips_realize(DeviceState *dev, Error **errp) 1194 { 1195 XilinxSPIPS *s = XILINX_SPIPS(dev); 1196 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1197 XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s); 1198 qemu_irq *cs; 1199 int i; 1200 1201 DB_PRINT_L(0, "realized spips\n"); 1202 1203 s->spi = g_new(SSIBus *, s->num_busses); 1204 for (i = 0; i < s->num_busses; ++i) { 1205 char bus_name[16]; 1206 snprintf(bus_name, 16, "spi%d", i); 1207 s->spi[i] = ssi_create_bus(dev, bus_name); 1208 } 1209 1210 s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses); 1211 s->cs_lines_state = g_new0(bool, s->num_cs * s->num_busses); 1212 for (i = 0, cs = s->cs_lines; i < s->num_busses; ++i, cs += s->num_cs) { 1213 ssi_auto_connect_slaves(DEVICE(s), cs, s->spi[i]); 1214 } 1215 1216 sysbus_init_irq(sbd, &s->irq); 1217 for (i = 0; i < s->num_cs * s->num_busses; ++i) { 1218 sysbus_init_irq(sbd, &s->cs_lines[i]); 1219 } 1220 1221 memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s, 1222 "spi", XLNX_ZYNQMP_SPIPS_R_MAX * 4); 1223 sysbus_init_mmio(sbd, &s->iomem); 1224 1225 s->irqline = -1; 1226 1227 fifo8_create(&s->rx_fifo, xsc->rx_fifo_size); 1228 fifo8_create(&s->tx_fifo, xsc->tx_fifo_size); 1229 } 1230 1231 static void xilinx_qspips_realize(DeviceState *dev, Error **errp) 1232 { 1233 XilinxSPIPS *s = XILINX_SPIPS(dev); 1234 XilinxQSPIPS *q = XILINX_QSPIPS(dev); 1235 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1236 1237 DB_PRINT_L(0, "realized qspips\n"); 1238 1239 s->num_busses = 2; 1240 s->num_cs = 2; 1241 s->num_txrx_bytes = 4; 1242 1243 xilinx_spips_realize(dev, errp); 1244 memory_region_init_io(&s->mmlqspi, OBJECT(s), &lqspi_ops, s, "lqspi", 1245 (1 << LQSPI_ADDRESS_BITS) * 2); 1246 sysbus_init_mmio(sbd, &s->mmlqspi); 1247 1248 q->lqspi_cached_addr = ~0ULL; 1249 1250 /* mmio_execution breaks migration better aborting than having strange 1251 * bugs. 1252 */ 1253 if (q->mmio_execution_enabled) { 1254 error_setg(&q->migration_blocker, 1255 "enabling mmio_execution breaks migration"); 1256 migrate_add_blocker(q->migration_blocker, &error_fatal); 1257 } 1258 } 1259 1260 static void xlnx_zynqmp_qspips_realize(DeviceState *dev, Error **errp) 1261 { 1262 XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(dev); 1263 XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s); 1264 1265 xilinx_qspips_realize(dev, errp); 1266 fifo8_create(&s->rx_fifo_g, xsc->rx_fifo_size); 1267 fifo8_create(&s->tx_fifo_g, xsc->tx_fifo_size); 1268 fifo32_create(&s->fifo_g, 32); 1269 } 1270 1271 static void xlnx_zynqmp_qspips_init(Object *obj) 1272 { 1273 XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(obj); 1274 1275 object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SLAVE, 1276 (Object **)&rq->dma, 1277 object_property_allow_set_link, 1278 OBJ_PROP_LINK_UNREF_ON_RELEASE, 1279 NULL); 1280 } 1281 1282 static int xilinx_spips_post_load(void *opaque, int version_id) 1283 { 1284 xilinx_spips_update_ixr((XilinxSPIPS *)opaque); 1285 xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque); 1286 return 0; 1287 } 1288 1289 static const VMStateDescription vmstate_xilinx_spips = { 1290 .name = "xilinx_spips", 1291 .version_id = 2, 1292 .minimum_version_id = 2, 1293 .post_load = xilinx_spips_post_load, 1294 .fields = (VMStateField[]) { 1295 VMSTATE_FIFO8(tx_fifo, XilinxSPIPS), 1296 VMSTATE_FIFO8(rx_fifo, XilinxSPIPS), 1297 VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, XLNX_SPIPS_R_MAX), 1298 VMSTATE_UINT8(snoop_state, XilinxSPIPS), 1299 VMSTATE_END_OF_LIST() 1300 } 1301 }; 1302 1303 static int xlnx_zynqmp_qspips_post_load(void *opaque, int version_id) 1304 { 1305 XlnxZynqMPQSPIPS *s = (XlnxZynqMPQSPIPS *)opaque; 1306 XilinxSPIPS *qs = XILINX_SPIPS(s); 1307 1308 if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN) && 1309 fifo8_is_empty(&qs->rx_fifo) && fifo8_is_empty(&qs->tx_fifo)) { 1310 xlnx_zynqmp_qspips_update_ixr(s); 1311 xlnx_zynqmp_qspips_update_cs_lines(s); 1312 } 1313 return 0; 1314 } 1315 1316 static const VMStateDescription vmstate_xilinx_qspips = { 1317 .name = "xilinx_qspips", 1318 .version_id = 1, 1319 .minimum_version_id = 1, 1320 .fields = (VMStateField[]) { 1321 VMSTATE_STRUCT(parent_obj, XilinxQSPIPS, 0, 1322 vmstate_xilinx_spips, XilinxSPIPS), 1323 VMSTATE_END_OF_LIST() 1324 } 1325 }; 1326 1327 static const VMStateDescription vmstate_xlnx_zynqmp_qspips = { 1328 .name = "xlnx_zynqmp_qspips", 1329 .version_id = 1, 1330 .minimum_version_id = 1, 1331 .post_load = xlnx_zynqmp_qspips_post_load, 1332 .fields = (VMStateField[]) { 1333 VMSTATE_STRUCT(parent_obj, XlnxZynqMPQSPIPS, 0, 1334 vmstate_xilinx_qspips, XilinxQSPIPS), 1335 VMSTATE_FIFO8(tx_fifo_g, XlnxZynqMPQSPIPS), 1336 VMSTATE_FIFO8(rx_fifo_g, XlnxZynqMPQSPIPS), 1337 VMSTATE_FIFO32(fifo_g, XlnxZynqMPQSPIPS), 1338 VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPQSPIPS, XLNX_ZYNQMP_SPIPS_R_MAX), 1339 VMSTATE_END_OF_LIST() 1340 } 1341 }; 1342 1343 static Property xilinx_qspips_properties[] = { 1344 /* We had to turn this off for 2.10 as it is not compatible with migration. 1345 * It can be enabled but will prevent the device to be migrated. 1346 * This will go aways when a fix will be released. 1347 */ 1348 DEFINE_PROP_BOOL("x-mmio-exec", XilinxQSPIPS, mmio_execution_enabled, 1349 false), 1350 DEFINE_PROP_END_OF_LIST(), 1351 }; 1352 1353 static Property xilinx_spips_properties[] = { 1354 DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1), 1355 DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4), 1356 DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1), 1357 DEFINE_PROP_END_OF_LIST(), 1358 }; 1359 1360 static void xilinx_qspips_class_init(ObjectClass *klass, void * data) 1361 { 1362 DeviceClass *dc = DEVICE_CLASS(klass); 1363 XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 1364 1365 dc->realize = xilinx_qspips_realize; 1366 dc->props = xilinx_qspips_properties; 1367 xsc->reg_ops = &qspips_ops; 1368 xsc->rx_fifo_size = RXFF_A_Q; 1369 xsc->tx_fifo_size = TXFF_A_Q; 1370 } 1371 1372 static void xilinx_spips_class_init(ObjectClass *klass, void *data) 1373 { 1374 DeviceClass *dc = DEVICE_CLASS(klass); 1375 XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 1376 1377 dc->realize = xilinx_spips_realize; 1378 dc->reset = xilinx_spips_reset; 1379 dc->props = xilinx_spips_properties; 1380 dc->vmsd = &vmstate_xilinx_spips; 1381 1382 xsc->reg_ops = &spips_ops; 1383 xsc->rx_fifo_size = RXFF_A; 1384 xsc->tx_fifo_size = TXFF_A; 1385 } 1386 1387 static void xlnx_zynqmp_qspips_class_init(ObjectClass *klass, void * data) 1388 { 1389 DeviceClass *dc = DEVICE_CLASS(klass); 1390 XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 1391 1392 dc->realize = xlnx_zynqmp_qspips_realize; 1393 dc->reset = xlnx_zynqmp_qspips_reset; 1394 dc->vmsd = &vmstate_xlnx_zynqmp_qspips; 1395 xsc->reg_ops = &xlnx_zynqmp_qspips_ops; 1396 xsc->rx_fifo_size = RXFF_A_Q; 1397 xsc->tx_fifo_size = TXFF_A_Q; 1398 } 1399 1400 static const TypeInfo xilinx_spips_info = { 1401 .name = TYPE_XILINX_SPIPS, 1402 .parent = TYPE_SYS_BUS_DEVICE, 1403 .instance_size = sizeof(XilinxSPIPS), 1404 .class_init = xilinx_spips_class_init, 1405 .class_size = sizeof(XilinxSPIPSClass), 1406 }; 1407 1408 static const TypeInfo xilinx_qspips_info = { 1409 .name = TYPE_XILINX_QSPIPS, 1410 .parent = TYPE_XILINX_SPIPS, 1411 .instance_size = sizeof(XilinxQSPIPS), 1412 .class_init = xilinx_qspips_class_init, 1413 }; 1414 1415 static const TypeInfo xlnx_zynqmp_qspips_info = { 1416 .name = TYPE_XLNX_ZYNQMP_QSPIPS, 1417 .parent = TYPE_XILINX_QSPIPS, 1418 .instance_size = sizeof(XlnxZynqMPQSPIPS), 1419 .instance_init = xlnx_zynqmp_qspips_init, 1420 .class_init = xlnx_zynqmp_qspips_class_init, 1421 }; 1422 1423 static void xilinx_spips_register_types(void) 1424 { 1425 type_register_static(&xilinx_spips_info); 1426 type_register_static(&xilinx_qspips_info); 1427 type_register_static(&xlnx_zynqmp_qspips_info); 1428 } 1429 1430 type_init(xilinx_spips_register_types) 1431