1 /* 2 * QEMU model of the Xilinx Zynq SPI controller 3 * 4 * Copyright (c) 2012 Peter A. G. Crosthwaite 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/sysbus.h" 27 #include "hw/irq.h" 28 #include "hw/ptimer.h" 29 #include "hw/qdev-properties.h" 30 #include "qemu/log.h" 31 #include "qemu/module.h" 32 #include "qemu/bitops.h" 33 #include "hw/ssi/xilinx_spips.h" 34 #include "qapi/error.h" 35 #include "hw/register.h" 36 #include "sysemu/dma.h" 37 #include "migration/blocker.h" 38 #include "migration/vmstate.h" 39 40 #ifndef XILINX_SPIPS_ERR_DEBUG 41 #define XILINX_SPIPS_ERR_DEBUG 0 42 #endif 43 44 #define DB_PRINT_L(level, ...) do { \ 45 if (XILINX_SPIPS_ERR_DEBUG > (level)) { \ 46 fprintf(stderr, ": %s: ", __func__); \ 47 fprintf(stderr, ## __VA_ARGS__); \ 48 } \ 49 } while (0) 50 51 /* config register */ 52 #define R_CONFIG (0x00 / 4) 53 #define IFMODE (1U << 31) 54 #define R_CONFIG_ENDIAN (1 << 26) 55 #define MODEFAIL_GEN_EN (1 << 17) 56 #define MAN_START_COM (1 << 16) 57 #define MAN_START_EN (1 << 15) 58 #define MANUAL_CS (1 << 14) 59 #define CS (0xF << 10) 60 #define CS_SHIFT (10) 61 #define PERI_SEL (1 << 9) 62 #define REF_CLK (1 << 8) 63 #define FIFO_WIDTH (3 << 6) 64 #define BAUD_RATE_DIV (7 << 3) 65 #define CLK_PH (1 << 2) 66 #define CLK_POL (1 << 1) 67 #define MODE_SEL (1 << 0) 68 #define R_CONFIG_RSVD (0x7bf40000) 69 70 /* interrupt mechanism */ 71 #define R_INTR_STATUS (0x04 / 4) 72 #define R_INTR_STATUS_RESET (0x104) 73 #define R_INTR_EN (0x08 / 4) 74 #define R_INTR_DIS (0x0C / 4) 75 #define R_INTR_MASK (0x10 / 4) 76 #define IXR_TX_FIFO_UNDERFLOW (1 << 6) 77 /* Poll timeout not implemented */ 78 #define IXR_RX_FIFO_EMPTY (1 << 11) 79 #define IXR_GENERIC_FIFO_FULL (1 << 10) 80 #define IXR_GENERIC_FIFO_NOT_FULL (1 << 9) 81 #define IXR_TX_FIFO_EMPTY (1 << 8) 82 #define IXR_GENERIC_FIFO_EMPTY (1 << 7) 83 #define IXR_RX_FIFO_FULL (1 << 5) 84 #define IXR_RX_FIFO_NOT_EMPTY (1 << 4) 85 #define IXR_TX_FIFO_FULL (1 << 3) 86 #define IXR_TX_FIFO_NOT_FULL (1 << 2) 87 #define IXR_TX_FIFO_MODE_FAIL (1 << 1) 88 #define IXR_RX_FIFO_OVERFLOW (1 << 0) 89 #define IXR_ALL ((1 << 13) - 1) 90 #define GQSPI_IXR_MASK 0xFBE 91 #define IXR_SELF_CLEAR \ 92 (IXR_GENERIC_FIFO_EMPTY \ 93 | IXR_GENERIC_FIFO_FULL \ 94 | IXR_GENERIC_FIFO_NOT_FULL \ 95 | IXR_TX_FIFO_EMPTY \ 96 | IXR_TX_FIFO_FULL \ 97 | IXR_TX_FIFO_NOT_FULL \ 98 | IXR_RX_FIFO_EMPTY \ 99 | IXR_RX_FIFO_FULL \ 100 | IXR_RX_FIFO_NOT_EMPTY) 101 102 #define R_EN (0x14 / 4) 103 #define R_DELAY (0x18 / 4) 104 #define R_TX_DATA (0x1C / 4) 105 #define R_RX_DATA (0x20 / 4) 106 #define R_SLAVE_IDLE_COUNT (0x24 / 4) 107 #define R_TX_THRES (0x28 / 4) 108 #define R_RX_THRES (0x2C / 4) 109 #define R_GPIO (0x30 / 4) 110 #define R_LPBK_DLY_ADJ (0x38 / 4) 111 #define R_LPBK_DLY_ADJ_RESET (0x33) 112 #define R_IOU_TAPDLY_BYPASS (0x3C / 4) 113 #define R_TXD1 (0x80 / 4) 114 #define R_TXD2 (0x84 / 4) 115 #define R_TXD3 (0x88 / 4) 116 117 #define R_LQSPI_CFG (0xa0 / 4) 118 #define R_LQSPI_CFG_RESET 0x03A002EB 119 #define LQSPI_CFG_LQ_MODE (1U << 31) 120 #define LQSPI_CFG_TWO_MEM (1 << 30) 121 #define LQSPI_CFG_SEP_BUS (1 << 29) 122 #define LQSPI_CFG_U_PAGE (1 << 28) 123 #define LQSPI_CFG_ADDR4 (1 << 27) 124 #define LQSPI_CFG_MODE_EN (1 << 25) 125 #define LQSPI_CFG_MODE_WIDTH 8 126 #define LQSPI_CFG_MODE_SHIFT 16 127 #define LQSPI_CFG_DUMMY_WIDTH 3 128 #define LQSPI_CFG_DUMMY_SHIFT 8 129 #define LQSPI_CFG_INST_CODE 0xFF 130 131 #define R_CMND (0xc0 / 4) 132 #define R_CMND_RXFIFO_DRAIN (1 << 19) 133 FIELD(CMND, PARTIAL_BYTE_LEN, 16, 3) 134 #define R_CMND_EXT_ADD (1 << 15) 135 FIELD(CMND, RX_DISCARD, 8, 7) 136 FIELD(CMND, DUMMY_CYCLES, 2, 6) 137 #define R_CMND_DMA_EN (1 << 1) 138 #define R_CMND_PUSH_WAIT (1 << 0) 139 #define R_TRANSFER_SIZE (0xc4 / 4) 140 #define R_LQSPI_STS (0xA4 / 4) 141 #define LQSPI_STS_WR_RECVD (1 << 1) 142 143 #define R_DUMMY_CYCLE_EN (0xC8 / 4) 144 #define R_ECO (0xF8 / 4) 145 #define R_MOD_ID (0xFC / 4) 146 147 #define R_GQSPI_SELECT (0x144 / 4) 148 FIELD(GQSPI_SELECT, GENERIC_QSPI_EN, 0, 1) 149 #define R_GQSPI_ISR (0x104 / 4) 150 #define R_GQSPI_IER (0x108 / 4) 151 #define R_GQSPI_IDR (0x10c / 4) 152 #define R_GQSPI_IMR (0x110 / 4) 153 #define R_GQSPI_IMR_RESET (0xfbe) 154 #define R_GQSPI_TX_THRESH (0x128 / 4) 155 #define R_GQSPI_RX_THRESH (0x12c / 4) 156 #define R_GQSPI_GPIO (0x130 / 4) 157 #define R_GQSPI_LPBK_DLY_ADJ (0x138 / 4) 158 #define R_GQSPI_LPBK_DLY_ADJ_RESET (0x33) 159 #define R_GQSPI_CNFG (0x100 / 4) 160 FIELD(GQSPI_CNFG, MODE_EN, 30, 2) 161 FIELD(GQSPI_CNFG, GEN_FIFO_START_MODE, 29, 1) 162 FIELD(GQSPI_CNFG, GEN_FIFO_START, 28, 1) 163 FIELD(GQSPI_CNFG, ENDIAN, 26, 1) 164 /* Poll timeout not implemented */ 165 FIELD(GQSPI_CNFG, EN_POLL_TIMEOUT, 20, 1) 166 /* QEMU doesnt care about any of these last three */ 167 FIELD(GQSPI_CNFG, BR, 3, 3) 168 FIELD(GQSPI_CNFG, CPH, 2, 1) 169 FIELD(GQSPI_CNFG, CPL, 1, 1) 170 #define R_GQSPI_GEN_FIFO (0x140 / 4) 171 #define R_GQSPI_TXD (0x11c / 4) 172 #define R_GQSPI_RXD (0x120 / 4) 173 #define R_GQSPI_FIFO_CTRL (0x14c / 4) 174 FIELD(GQSPI_FIFO_CTRL, RX_FIFO_RESET, 2, 1) 175 FIELD(GQSPI_FIFO_CTRL, TX_FIFO_RESET, 1, 1) 176 FIELD(GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET, 0, 1) 177 #define R_GQSPI_GFIFO_THRESH (0x150 / 4) 178 #define R_GQSPI_DATA_STS (0x15c / 4) 179 /* 180 * We use the snapshot register to hold the core state for the currently 181 * or most recently executed command. So the generic fifo format is defined 182 * for the snapshot register 183 */ 184 #define R_GQSPI_GF_SNAPSHOT (0x160 / 4) 185 FIELD(GQSPI_GF_SNAPSHOT, POLL, 19, 1) 186 FIELD(GQSPI_GF_SNAPSHOT, STRIPE, 18, 1) 187 FIELD(GQSPI_GF_SNAPSHOT, RECIEVE, 17, 1) 188 FIELD(GQSPI_GF_SNAPSHOT, TRANSMIT, 16, 1) 189 FIELD(GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT, 14, 2) 190 FIELD(GQSPI_GF_SNAPSHOT, CHIP_SELECT, 12, 2) 191 FIELD(GQSPI_GF_SNAPSHOT, SPI_MODE, 10, 2) 192 FIELD(GQSPI_GF_SNAPSHOT, EXPONENT, 9, 1) 193 FIELD(GQSPI_GF_SNAPSHOT, DATA_XFER, 8, 1) 194 FIELD(GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA, 0, 8) 195 #define R_GQSPI_MOD_ID (0x1fc / 4) 196 #define R_GQSPI_MOD_ID_RESET (0x10a0000) 197 198 #define R_QSPIDMA_DST_CTRL (0x80c / 4) 199 #define R_QSPIDMA_DST_CTRL_RESET (0x803ffa00) 200 #define R_QSPIDMA_DST_I_MASK (0x820 / 4) 201 #define R_QSPIDMA_DST_I_MASK_RESET (0xfe) 202 #define R_QSPIDMA_DST_CTRL2 (0x824 / 4) 203 #define R_QSPIDMA_DST_CTRL2_RESET (0x081bfff8) 204 205 /* size of TXRX FIFOs */ 206 #define RXFF_A (128) 207 #define TXFF_A (128) 208 209 #define RXFF_A_Q (64 * 4) 210 #define TXFF_A_Q (64 * 4) 211 212 /* 16MB per linear region */ 213 #define LQSPI_ADDRESS_BITS 24 214 215 #define SNOOP_CHECKING 0xFF 216 #define SNOOP_ADDR 0xF0 217 #define SNOOP_NONE 0xEE 218 #define SNOOP_STRIPING 0 219 220 #define MIN_NUM_BUSSES 1 221 #define MAX_NUM_BUSSES 2 222 223 static inline int num_effective_busses(XilinxSPIPS *s) 224 { 225 return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && 226 s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1; 227 } 228 229 static void xilinx_spips_update_cs(XilinxSPIPS *s, int field) 230 { 231 int i; 232 233 for (i = 0; i < s->num_cs * s->num_busses; i++) { 234 bool old_state = s->cs_lines_state[i]; 235 bool new_state = field & (1 << i); 236 237 if (old_state != new_state) { 238 s->cs_lines_state[i] = new_state; 239 s->rx_discard = ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD); 240 DB_PRINT_L(1, "%sselecting peripheral %d\n", 241 new_state ? "" : "de", i); 242 } 243 qemu_set_irq(s->cs_lines[i], !new_state); 244 } 245 if (!(field & ((1 << (s->num_cs * s->num_busses)) - 1))) { 246 s->snoop_state = SNOOP_CHECKING; 247 s->cmd_dummies = 0; 248 s->link_state = 1; 249 s->link_state_next = 1; 250 s->link_state_next_when = 0; 251 DB_PRINT_L(1, "moving to snoop check state\n"); 252 } 253 } 254 255 static void xlnx_zynqmp_qspips_update_cs_lines(XlnxZynqMPQSPIPS *s) 256 { 257 if (s->regs[R_GQSPI_GF_SNAPSHOT]) { 258 int field = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, CHIP_SELECT); 259 bool upper_cs_sel = field & (1 << 1); 260 bool lower_cs_sel = field & 1; 261 bool bus0_enabled; 262 bool bus1_enabled; 263 uint8_t buses; 264 int cs = 0; 265 266 buses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT); 267 bus0_enabled = buses & 1; 268 bus1_enabled = buses & (1 << 1); 269 270 if (bus0_enabled && bus1_enabled) { 271 if (lower_cs_sel) { 272 cs |= 1; 273 } 274 if (upper_cs_sel) { 275 cs |= 1 << 3; 276 } 277 } else if (bus0_enabled) { 278 if (lower_cs_sel) { 279 cs |= 1; 280 } 281 if (upper_cs_sel) { 282 cs |= 1 << 1; 283 } 284 } else if (bus1_enabled) { 285 if (lower_cs_sel) { 286 cs |= 1 << 2; 287 } 288 if (upper_cs_sel) { 289 cs |= 1 << 3; 290 } 291 } 292 xilinx_spips_update_cs(XILINX_SPIPS(s), cs); 293 } 294 } 295 296 static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) 297 { 298 int field = ~((s->regs[R_CONFIG] & CS) >> CS_SHIFT); 299 300 /* In dual parallel, mirror low CS to both */ 301 if (num_effective_busses(s) == 2) { 302 /* Single bit chip-select for qspi */ 303 field &= 0x1; 304 field |= field << 3; 305 /* Dual stack U-Page */ 306 } else if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM && 307 s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE) { 308 /* Single bit chip-select for qspi */ 309 field &= 0x1; 310 /* change from CS0 to CS1 */ 311 field <<= 1; 312 } 313 /* Auto CS */ 314 if (!(s->regs[R_CONFIG] & MANUAL_CS) && 315 fifo8_is_empty(&s->tx_fifo)) { 316 field = 0; 317 } 318 xilinx_spips_update_cs(s, field); 319 } 320 321 static void xilinx_spips_update_ixr(XilinxSPIPS *s) 322 { 323 if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { 324 s->regs[R_INTR_STATUS] &= ~IXR_SELF_CLEAR; 325 s->regs[R_INTR_STATUS] |= 326 (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) | 327 (s->rx_fifo.num >= s->regs[R_RX_THRES] ? 328 IXR_RX_FIFO_NOT_EMPTY : 0) | 329 (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | 330 (fifo8_is_empty(&s->tx_fifo) ? IXR_TX_FIFO_EMPTY : 0) | 331 (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0); 332 } 333 int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] & 334 IXR_ALL); 335 if (new_irqline != s->irqline) { 336 s->irqline = new_irqline; 337 qemu_set_irq(s->irq, s->irqline); 338 } 339 } 340 341 static void xlnx_zynqmp_qspips_update_ixr(XlnxZynqMPQSPIPS *s) 342 { 343 uint32_t gqspi_int; 344 int new_irqline; 345 346 s->regs[R_GQSPI_ISR] &= ~IXR_SELF_CLEAR; 347 s->regs[R_GQSPI_ISR] |= 348 (fifo32_is_empty(&s->fifo_g) ? IXR_GENERIC_FIFO_EMPTY : 0) | 349 (fifo32_is_full(&s->fifo_g) ? IXR_GENERIC_FIFO_FULL : 0) | 350 (s->fifo_g.fifo.num < s->regs[R_GQSPI_GFIFO_THRESH] ? 351 IXR_GENERIC_FIFO_NOT_FULL : 0) | 352 (fifo8_is_empty(&s->rx_fifo_g) ? IXR_RX_FIFO_EMPTY : 0) | 353 (fifo8_is_full(&s->rx_fifo_g) ? IXR_RX_FIFO_FULL : 0) | 354 (s->rx_fifo_g.num >= s->regs[R_GQSPI_RX_THRESH] ? 355 IXR_RX_FIFO_NOT_EMPTY : 0) | 356 (fifo8_is_empty(&s->tx_fifo_g) ? IXR_TX_FIFO_EMPTY : 0) | 357 (fifo8_is_full(&s->tx_fifo_g) ? IXR_TX_FIFO_FULL : 0) | 358 (s->tx_fifo_g.num < s->regs[R_GQSPI_TX_THRESH] ? 359 IXR_TX_FIFO_NOT_FULL : 0); 360 361 /* GQSPI Interrupt Trigger Status */ 362 gqspi_int = (~s->regs[R_GQSPI_IMR]) & s->regs[R_GQSPI_ISR] & GQSPI_IXR_MASK; 363 new_irqline = !!(gqspi_int & IXR_ALL); 364 365 /* drive external interrupt pin */ 366 if (new_irqline != s->gqspi_irqline) { 367 s->gqspi_irqline = new_irqline; 368 qemu_set_irq(XILINX_SPIPS(s)->irq, s->gqspi_irqline); 369 } 370 } 371 372 static void xilinx_spips_reset(DeviceState *d) 373 { 374 XilinxSPIPS *s = XILINX_SPIPS(d); 375 376 memset(s->regs, 0, sizeof(s->regs)); 377 378 fifo8_reset(&s->rx_fifo); 379 fifo8_reset(&s->rx_fifo); 380 /* non zero resets */ 381 s->regs[R_CONFIG] |= MODEFAIL_GEN_EN; 382 s->regs[R_SLAVE_IDLE_COUNT] = 0xFF; 383 s->regs[R_TX_THRES] = 1; 384 s->regs[R_RX_THRES] = 1; 385 /* FIXME: move magic number definition somewhere sensible */ 386 s->regs[R_MOD_ID] = 0x01090106; 387 s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET; 388 s->link_state = 1; 389 s->link_state_next = 1; 390 s->link_state_next_when = 0; 391 s->snoop_state = SNOOP_CHECKING; 392 s->cmd_dummies = 0; 393 s->man_start_com = false; 394 xilinx_spips_update_ixr(s); 395 xilinx_spips_update_cs_lines(s); 396 } 397 398 static void xlnx_zynqmp_qspips_reset(DeviceState *d) 399 { 400 XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(d); 401 402 xilinx_spips_reset(d); 403 404 memset(s->regs, 0, sizeof(s->regs)); 405 406 fifo8_reset(&s->rx_fifo_g); 407 fifo8_reset(&s->rx_fifo_g); 408 fifo32_reset(&s->fifo_g); 409 s->regs[R_INTR_STATUS] = R_INTR_STATUS_RESET; 410 s->regs[R_GPIO] = 1; 411 s->regs[R_LPBK_DLY_ADJ] = R_LPBK_DLY_ADJ_RESET; 412 s->regs[R_GQSPI_GFIFO_THRESH] = 0x10; 413 s->regs[R_MOD_ID] = 0x01090101; 414 s->regs[R_GQSPI_IMR] = R_GQSPI_IMR_RESET; 415 s->regs[R_GQSPI_TX_THRESH] = 1; 416 s->regs[R_GQSPI_RX_THRESH] = 1; 417 s->regs[R_GQSPI_GPIO] = 1; 418 s->regs[R_GQSPI_LPBK_DLY_ADJ] = R_GQSPI_LPBK_DLY_ADJ_RESET; 419 s->regs[R_GQSPI_MOD_ID] = R_GQSPI_MOD_ID_RESET; 420 s->regs[R_QSPIDMA_DST_CTRL] = R_QSPIDMA_DST_CTRL_RESET; 421 s->regs[R_QSPIDMA_DST_I_MASK] = R_QSPIDMA_DST_I_MASK_RESET; 422 s->regs[R_QSPIDMA_DST_CTRL2] = R_QSPIDMA_DST_CTRL2_RESET; 423 s->man_start_com_g = false; 424 s->gqspi_irqline = 0; 425 xlnx_zynqmp_qspips_update_ixr(s); 426 } 427 428 /* 429 * N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) 430 * column wise (from element 0 to N-1). num is the length of x, and dir 431 * reverses the direction of the transform. Best illustrated by example: 432 * Each digit in the below array is a single bit (num == 3): 433 * 434 * {{ 76543210, } ----- stripe (dir == false) -----> {{ 741gdaFC, } 435 * { hgfedcba, } { 630fcHEB, } 436 * { HGFEDCBA, }} <---- upstripe (dir == true) ----- { 52hebGDA, }} 437 */ 438 439 static inline void stripe8(uint8_t *x, int num, bool dir) 440 { 441 uint8_t r[MAX_NUM_BUSSES]; 442 int idx[2] = {0, 0}; 443 int bit[2] = {0, 7}; 444 int d = dir; 445 446 assert(num <= MAX_NUM_BUSSES); 447 memset(r, 0, sizeof(uint8_t) * num); 448 449 for (idx[0] = 0; idx[0] < num; ++idx[0]) { 450 for (bit[0] = 7; bit[0] >= 0; bit[0]--) { 451 r[idx[!d]] |= x[idx[d]] & 1 << bit[d] ? 1 << bit[!d] : 0; 452 idx[1] = (idx[1] + 1) % num; 453 if (!idx[1]) { 454 bit[1]--; 455 } 456 } 457 } 458 memcpy(x, r, sizeof(uint8_t) * num); 459 } 460 461 static void xlnx_zynqmp_qspips_flush_fifo_g(XlnxZynqMPQSPIPS *s) 462 { 463 while (s->regs[R_GQSPI_DATA_STS] || !fifo32_is_empty(&s->fifo_g)) { 464 uint8_t tx_rx[2] = { 0 }; 465 int num_stripes = 1; 466 uint8_t busses; 467 int i; 468 469 if (!s->regs[R_GQSPI_DATA_STS]) { 470 uint8_t imm; 471 472 s->regs[R_GQSPI_GF_SNAPSHOT] = fifo32_pop(&s->fifo_g); 473 DB_PRINT_L(0, "GQSPI command: %x\n", s->regs[R_GQSPI_GF_SNAPSHOT]); 474 if (!s->regs[R_GQSPI_GF_SNAPSHOT]) { 475 DB_PRINT_L(0, "Dummy GQSPI Delay Command Entry, Do nothing"); 476 continue; 477 } 478 xlnx_zynqmp_qspips_update_cs_lines(s); 479 480 imm = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA); 481 if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) { 482 /* immedate transfer */ 483 if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) || 484 ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) { 485 s->regs[R_GQSPI_DATA_STS] = 1; 486 /* CS setup/hold - do nothing */ 487 } else { 488 s->regs[R_GQSPI_DATA_STS] = 0; 489 } 490 } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, EXPONENT)) { 491 if (imm > 31) { 492 qemu_log_mask(LOG_UNIMP, "QSPI exponential transfer too" 493 " long - 2 ^ %" PRId8 " requested\n", imm); 494 } 495 s->regs[R_GQSPI_DATA_STS] = 1ul << imm; 496 } else { 497 s->regs[R_GQSPI_DATA_STS] = imm; 498 } 499 } 500 /* Zero length transfer check */ 501 if (!s->regs[R_GQSPI_DATA_STS]) { 502 continue; 503 } 504 if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE) && 505 fifo8_is_full(&s->rx_fifo_g)) { 506 /* No space in RX fifo for transfer - try again later */ 507 return; 508 } 509 if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, STRIPE) && 510 (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) || 511 ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE))) { 512 num_stripes = 2; 513 } 514 if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) { 515 tx_rx[0] = ARRAY_FIELD_EX32(s->regs, 516 GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA); 517 } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT)) { 518 for (i = 0; i < num_stripes; ++i) { 519 if (!fifo8_is_empty(&s->tx_fifo_g)) { 520 tx_rx[i] = fifo8_pop(&s->tx_fifo_g); 521 s->tx_fifo_g_align++; 522 } else { 523 return; 524 } 525 } 526 } 527 if (num_stripes == 1) { 528 /* mirror */ 529 tx_rx[1] = tx_rx[0]; 530 } 531 busses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT); 532 for (i = 0; i < 2; ++i) { 533 DB_PRINT_L(1, "bus %d tx = %02x\n", i, tx_rx[i]); 534 tx_rx[i] = ssi_transfer(XILINX_SPIPS(s)->spi[i], tx_rx[i]); 535 DB_PRINT_L(1, "bus %d rx = %02x\n", i, tx_rx[i]); 536 } 537 if (s->regs[R_GQSPI_DATA_STS] > 1 && 538 busses == 0x3 && num_stripes == 2) { 539 s->regs[R_GQSPI_DATA_STS] -= 2; 540 } else if (s->regs[R_GQSPI_DATA_STS] > 0) { 541 s->regs[R_GQSPI_DATA_STS]--; 542 } 543 if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) { 544 for (i = 0; i < 2; ++i) { 545 if (busses & (1 << i)) { 546 DB_PRINT_L(1, "bus %d push_byte = %02x\n", i, tx_rx[i]); 547 fifo8_push(&s->rx_fifo_g, tx_rx[i]); 548 s->rx_fifo_g_align++; 549 } 550 } 551 } 552 if (!s->regs[R_GQSPI_DATA_STS]) { 553 for (; s->tx_fifo_g_align % 4; s->tx_fifo_g_align++) { 554 fifo8_pop(&s->tx_fifo_g); 555 } 556 for (; s->rx_fifo_g_align % 4; s->rx_fifo_g_align++) { 557 fifo8_push(&s->rx_fifo_g, 0); 558 } 559 } 560 } 561 } 562 563 static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command) 564 { 565 if (!qs) { 566 /* The SPI device is not a QSPI device */ 567 return -1; 568 } 569 570 switch (command) { /* check for dummies */ 571 case READ: /* no dummy bytes/cycles */ 572 case PP: 573 case DPP: 574 case QPP: 575 case READ_4: 576 case PP_4: 577 case QPP_4: 578 return 0; 579 case FAST_READ: 580 case DOR: 581 case QOR: 582 case FAST_READ_4: 583 case DOR_4: 584 case QOR_4: 585 return 1; 586 case DIOR: 587 case DIOR_4: 588 return 2; 589 case QIOR: 590 case QIOR_4: 591 return 4; 592 default: 593 return -1; 594 } 595 } 596 597 static inline uint8_t get_addr_length(XilinxSPIPS *s, uint8_t cmd) 598 { 599 switch (cmd) { 600 case PP_4: 601 case QPP_4: 602 case READ_4: 603 case QIOR_4: 604 case FAST_READ_4: 605 case DOR_4: 606 case QOR_4: 607 case DIOR_4: 608 return 4; 609 default: 610 return (s->regs[R_CMND] & R_CMND_EXT_ADD) ? 4 : 3; 611 } 612 } 613 614 static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) 615 { 616 int debug_level = 0; 617 XilinxQSPIPS *q = (XilinxQSPIPS *) object_dynamic_cast(OBJECT(s), 618 TYPE_XILINX_QSPIPS); 619 620 for (;;) { 621 int i; 622 uint8_t tx = 0; 623 uint8_t tx_rx[MAX_NUM_BUSSES] = { 0 }; 624 uint8_t dummy_cycles = 0; 625 uint8_t addr_length; 626 627 if (fifo8_is_empty(&s->tx_fifo)) { 628 xilinx_spips_update_ixr(s); 629 return; 630 } else if (s->snoop_state == SNOOP_STRIPING || 631 s->snoop_state == SNOOP_NONE) { 632 for (i = 0; i < num_effective_busses(s); ++i) { 633 tx_rx[i] = fifo8_pop(&s->tx_fifo); 634 } 635 stripe8(tx_rx, num_effective_busses(s), false); 636 } else if (s->snoop_state >= SNOOP_ADDR) { 637 tx = fifo8_pop(&s->tx_fifo); 638 for (i = 0; i < num_effective_busses(s); ++i) { 639 tx_rx[i] = tx; 640 } 641 } else { 642 /* 643 * Extract a dummy byte and generate dummy cycles according to the 644 * link state 645 */ 646 tx = fifo8_pop(&s->tx_fifo); 647 dummy_cycles = 8 / s->link_state; 648 } 649 650 for (i = 0; i < num_effective_busses(s); ++i) { 651 int bus = num_effective_busses(s) - 1 - i; 652 if (dummy_cycles) { 653 int d; 654 for (d = 0; d < dummy_cycles; ++d) { 655 tx_rx[0] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[0]); 656 } 657 } else { 658 DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]); 659 tx_rx[i] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]); 660 DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]); 661 } 662 } 663 664 if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { 665 DB_PRINT_L(debug_level, "dircarding drained rx byte\n"); 666 /* Do nothing */ 667 } else if (s->rx_discard) { 668 DB_PRINT_L(debug_level, "dircarding discarded rx byte\n"); 669 s->rx_discard -= 8 / s->link_state; 670 } else if (fifo8_is_full(&s->rx_fifo)) { 671 s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW; 672 DB_PRINT_L(0, "rx FIFO overflow"); 673 } else if (s->snoop_state == SNOOP_STRIPING) { 674 stripe8(tx_rx, num_effective_busses(s), true); 675 for (i = 0; i < num_effective_busses(s); ++i) { 676 fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]); 677 DB_PRINT_L(debug_level, "pushing striped rx byte\n"); 678 } 679 } else { 680 DB_PRINT_L(debug_level, "pushing unstriped rx byte\n"); 681 fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]); 682 } 683 684 if (s->link_state_next_when) { 685 s->link_state_next_when--; 686 if (!s->link_state_next_when) { 687 s->link_state = s->link_state_next; 688 } 689 } 690 691 DB_PRINT_L(debug_level, "initial snoop state: %x\n", 692 (unsigned)s->snoop_state); 693 switch (s->snoop_state) { 694 case (SNOOP_CHECKING): 695 /* Store the count of dummy bytes in the txfifo */ 696 s->cmd_dummies = xilinx_spips_num_dummies(q, tx); 697 addr_length = get_addr_length(s, tx); 698 if (s->cmd_dummies < 0) { 699 s->snoop_state = SNOOP_NONE; 700 } else { 701 s->snoop_state = SNOOP_ADDR + addr_length - 1; 702 } 703 switch (tx) { 704 case DPP: 705 case DOR: 706 case DOR_4: 707 s->link_state_next = 2; 708 s->link_state_next_when = addr_length + s->cmd_dummies; 709 break; 710 case QPP: 711 case QPP_4: 712 case QOR: 713 case QOR_4: 714 s->link_state_next = 4; 715 s->link_state_next_when = addr_length + s->cmd_dummies; 716 break; 717 case DIOR: 718 case DIOR_4: 719 s->link_state = 2; 720 break; 721 case QIOR: 722 case QIOR_4: 723 s->link_state = 4; 724 break; 725 } 726 break; 727 case (SNOOP_ADDR): 728 /* 729 * Address has been transmitted, transmit dummy cycles now if needed 730 */ 731 if (s->cmd_dummies < 0) { 732 s->snoop_state = SNOOP_NONE; 733 } else { 734 s->snoop_state = s->cmd_dummies; 735 } 736 break; 737 case (SNOOP_STRIPING): 738 case (SNOOP_NONE): 739 /* Once we hit the boring stuff - squelch debug noise */ 740 if (!debug_level) { 741 DB_PRINT_L(0, "squelching debug info ....\n"); 742 debug_level = 1; 743 } 744 break; 745 default: 746 s->snoop_state--; 747 } 748 DB_PRINT_L(debug_level, "final snoop state: %x\n", 749 (unsigned)s->snoop_state); 750 } 751 } 752 753 static inline void tx_data_bytes(Fifo8 *fifo, uint32_t value, int num, bool be) 754 { 755 int i; 756 for (i = 0; i < num && !fifo8_is_full(fifo); ++i) { 757 if (be) { 758 fifo8_push(fifo, (uint8_t)(value >> 24)); 759 value <<= 8; 760 } else { 761 fifo8_push(fifo, (uint8_t)value); 762 value >>= 8; 763 } 764 } 765 } 766 767 static void xilinx_spips_check_zero_pump(XilinxSPIPS *s) 768 { 769 if (!s->regs[R_TRANSFER_SIZE]) { 770 return; 771 } 772 if (!fifo8_is_empty(&s->tx_fifo) && s->regs[R_CMND] & R_CMND_PUSH_WAIT) { 773 return; 774 } 775 /* 776 * The zero pump must never fill tx fifo such that rx overflow is 777 * possible 778 */ 779 while (s->regs[R_TRANSFER_SIZE] && 780 s->rx_fifo.num + s->tx_fifo.num < RXFF_A_Q - 3) { 781 /* endianess just doesn't matter when zero pumping */ 782 tx_data_bytes(&s->tx_fifo, 0, 4, false); 783 s->regs[R_TRANSFER_SIZE] &= ~0x03ull; 784 s->regs[R_TRANSFER_SIZE] -= 4; 785 } 786 } 787 788 static void xilinx_spips_check_flush(XilinxSPIPS *s) 789 { 790 if (s->man_start_com || 791 (!fifo8_is_empty(&s->tx_fifo) && 792 !(s->regs[R_CONFIG] & MAN_START_EN))) { 793 xilinx_spips_check_zero_pump(s); 794 xilinx_spips_flush_txfifo(s); 795 } 796 if (fifo8_is_empty(&s->tx_fifo) && !s->regs[R_TRANSFER_SIZE]) { 797 s->man_start_com = false; 798 } 799 xilinx_spips_update_ixr(s); 800 } 801 802 static void xlnx_zynqmp_qspips_check_flush(XlnxZynqMPQSPIPS *s) 803 { 804 bool gqspi_has_work = s->regs[R_GQSPI_DATA_STS] || 805 !fifo32_is_empty(&s->fifo_g); 806 807 if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) { 808 if (s->man_start_com_g || (gqspi_has_work && 809 !ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE))) { 810 xlnx_zynqmp_qspips_flush_fifo_g(s); 811 } 812 } else { 813 xilinx_spips_check_flush(XILINX_SPIPS(s)); 814 } 815 if (!gqspi_has_work) { 816 s->man_start_com_g = false; 817 } 818 xlnx_zynqmp_qspips_update_ixr(s); 819 } 820 821 static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max) 822 { 823 int i; 824 825 for (i = 0; i < max && !fifo8_is_empty(fifo); ++i) { 826 value[i] = fifo8_pop(fifo); 827 } 828 return max - i; 829 } 830 831 static const void *pop_buf(Fifo8 *fifo, uint32_t max, uint32_t *num) 832 { 833 void *ret; 834 835 if (max == 0 || max > fifo->num) { 836 abort(); 837 } 838 *num = MIN(fifo->capacity - fifo->head, max); 839 ret = &fifo->data[fifo->head]; 840 fifo->head += *num; 841 fifo->head %= fifo->capacity; 842 fifo->num -= *num; 843 return ret; 844 } 845 846 static void xlnx_zynqmp_qspips_notify(void *opaque) 847 { 848 XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(opaque); 849 XilinxSPIPS *s = XILINX_SPIPS(rq); 850 Fifo8 *recv_fifo; 851 852 if (ARRAY_FIELD_EX32(rq->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) { 853 if (!(ARRAY_FIELD_EX32(rq->regs, GQSPI_CNFG, MODE_EN) == 2)) { 854 return; 855 } 856 recv_fifo = &rq->rx_fifo_g; 857 } else { 858 if (!(s->regs[R_CMND] & R_CMND_DMA_EN)) { 859 return; 860 } 861 recv_fifo = &s->rx_fifo; 862 } 863 while (recv_fifo->num >= 4 864 && stream_can_push(rq->dma, xlnx_zynqmp_qspips_notify, rq)) 865 { 866 size_t ret; 867 uint32_t num; 868 const void *rxd; 869 int len; 870 871 len = recv_fifo->num >= rq->dma_burst_size ? rq->dma_burst_size : 872 recv_fifo->num; 873 rxd = pop_buf(recv_fifo, len, &num); 874 875 memcpy(rq->dma_buf, rxd, num); 876 877 ret = stream_push(rq->dma, rq->dma_buf, num, false); 878 assert(ret == num); 879 xlnx_zynqmp_qspips_check_flush(rq); 880 } 881 } 882 883 static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, 884 unsigned size) 885 { 886 XilinxSPIPS *s = opaque; 887 uint32_t mask = ~0; 888 uint32_t ret; 889 uint8_t rx_buf[4]; 890 int shortfall; 891 892 addr >>= 2; 893 switch (addr) { 894 case R_CONFIG: 895 mask = ~(R_CONFIG_RSVD | MAN_START_COM); 896 break; 897 case R_INTR_STATUS: 898 ret = s->regs[addr] & IXR_ALL; 899 s->regs[addr] = 0; 900 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 901 xilinx_spips_update_ixr(s); 902 return ret; 903 case R_INTR_MASK: 904 mask = IXR_ALL; 905 break; 906 case R_EN: 907 mask = 0x1; 908 break; 909 case R_SLAVE_IDLE_COUNT: 910 mask = 0xFF; 911 break; 912 case R_MOD_ID: 913 mask = 0x01FFFFFF; 914 break; 915 case R_INTR_EN: 916 case R_INTR_DIS: 917 case R_TX_DATA: 918 mask = 0; 919 break; 920 case R_RX_DATA: 921 memset(rx_buf, 0, sizeof(rx_buf)); 922 shortfall = rx_data_bytes(&s->rx_fifo, rx_buf, s->num_txrx_bytes); 923 ret = s->regs[R_CONFIG] & R_CONFIG_ENDIAN ? 924 cpu_to_be32(*(uint32_t *)rx_buf) : 925 cpu_to_le32(*(uint32_t *)rx_buf); 926 if (!(s->regs[R_CONFIG] & R_CONFIG_ENDIAN)) { 927 ret <<= 8 * shortfall; 928 } 929 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 930 xilinx_spips_check_flush(s); 931 xilinx_spips_update_ixr(s); 932 return ret; 933 } 934 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, 935 s->regs[addr] & mask); 936 return s->regs[addr] & mask; 937 938 } 939 940 static uint64_t xlnx_zynqmp_qspips_read(void *opaque, 941 hwaddr addr, unsigned size) 942 { 943 XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(opaque); 944 uint32_t reg = addr / 4; 945 uint32_t ret; 946 uint8_t rx_buf[4]; 947 int shortfall; 948 949 if (reg <= R_MOD_ID) { 950 return xilinx_spips_read(opaque, addr, size); 951 } else { 952 switch (reg) { 953 case R_GQSPI_RXD: 954 if (fifo8_is_empty(&s->rx_fifo_g)) { 955 qemu_log_mask(LOG_GUEST_ERROR, 956 "Read from empty GQSPI RX FIFO\n"); 957 return 0; 958 } 959 memset(rx_buf, 0, sizeof(rx_buf)); 960 shortfall = rx_data_bytes(&s->rx_fifo_g, rx_buf, 961 XILINX_SPIPS(s)->num_txrx_bytes); 962 ret = ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN) ? 963 cpu_to_be32(*(uint32_t *)rx_buf) : 964 cpu_to_le32(*(uint32_t *)rx_buf); 965 if (!ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN)) { 966 ret <<= 8 * shortfall; 967 } 968 xlnx_zynqmp_qspips_check_flush(s); 969 xlnx_zynqmp_qspips_update_ixr(s); 970 return ret; 971 default: 972 return s->regs[reg]; 973 } 974 } 975 } 976 977 static void xilinx_spips_write(void *opaque, hwaddr addr, 978 uint64_t value, unsigned size) 979 { 980 int mask = ~0; 981 XilinxSPIPS *s = opaque; 982 bool try_flush = true; 983 984 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value); 985 addr >>= 2; 986 switch (addr) { 987 case R_CONFIG: 988 mask = ~(R_CONFIG_RSVD | MAN_START_COM); 989 if ((value & MAN_START_COM) && (s->regs[R_CONFIG] & MAN_START_EN)) { 990 s->man_start_com = true; 991 } 992 break; 993 case R_INTR_STATUS: 994 mask = IXR_ALL; 995 s->regs[R_INTR_STATUS] &= ~(mask & value); 996 goto no_reg_update; 997 case R_INTR_DIS: 998 mask = IXR_ALL; 999 s->regs[R_INTR_MASK] &= ~(mask & value); 1000 goto no_reg_update; 1001 case R_INTR_EN: 1002 mask = IXR_ALL; 1003 s->regs[R_INTR_MASK] |= mask & value; 1004 goto no_reg_update; 1005 case R_EN: 1006 mask = 0x1; 1007 break; 1008 case R_SLAVE_IDLE_COUNT: 1009 mask = 0xFF; 1010 break; 1011 case R_RX_DATA: 1012 case R_INTR_MASK: 1013 case R_MOD_ID: 1014 mask = 0; 1015 break; 1016 case R_TX_DATA: 1017 tx_data_bytes(&s->tx_fifo, (uint32_t)value, s->num_txrx_bytes, 1018 s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 1019 goto no_reg_update; 1020 case R_TXD1: 1021 tx_data_bytes(&s->tx_fifo, (uint32_t)value, 1, 1022 s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 1023 goto no_reg_update; 1024 case R_TXD2: 1025 tx_data_bytes(&s->tx_fifo, (uint32_t)value, 2, 1026 s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 1027 goto no_reg_update; 1028 case R_TXD3: 1029 tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3, 1030 s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 1031 goto no_reg_update; 1032 /* Skip SPI bus update for below registers writes */ 1033 case R_GPIO: 1034 case R_LPBK_DLY_ADJ: 1035 case R_IOU_TAPDLY_BYPASS: 1036 case R_DUMMY_CYCLE_EN: 1037 case R_ECO: 1038 try_flush = false; 1039 break; 1040 } 1041 s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); 1042 no_reg_update: 1043 if (try_flush) { 1044 xilinx_spips_update_cs_lines(s); 1045 xilinx_spips_check_flush(s); 1046 xilinx_spips_update_cs_lines(s); 1047 xilinx_spips_update_ixr(s); 1048 } 1049 } 1050 1051 static const MemoryRegionOps spips_ops = { 1052 .read = xilinx_spips_read, 1053 .write = xilinx_spips_write, 1054 .endianness = DEVICE_LITTLE_ENDIAN, 1055 }; 1056 1057 static void xilinx_qspips_invalidate_mmio_ptr(XilinxQSPIPS *q) 1058 { 1059 q->lqspi_cached_addr = ~0ULL; 1060 } 1061 1062 static void xilinx_qspips_write(void *opaque, hwaddr addr, 1063 uint64_t value, unsigned size) 1064 { 1065 XilinxQSPIPS *q = XILINX_QSPIPS(opaque); 1066 XilinxSPIPS *s = XILINX_SPIPS(opaque); 1067 1068 xilinx_spips_write(opaque, addr, value, size); 1069 addr >>= 2; 1070 1071 if (addr == R_LQSPI_CFG) { 1072 xilinx_qspips_invalidate_mmio_ptr(q); 1073 } 1074 if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { 1075 fifo8_reset(&s->rx_fifo); 1076 } 1077 } 1078 1079 static void xlnx_zynqmp_qspips_write(void *opaque, hwaddr addr, 1080 uint64_t value, unsigned size) 1081 { 1082 XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(opaque); 1083 uint32_t reg = addr / 4; 1084 1085 if (reg <= R_MOD_ID) { 1086 xilinx_qspips_write(opaque, addr, value, size); 1087 } else { 1088 switch (reg) { 1089 case R_GQSPI_CNFG: 1090 if (FIELD_EX32(value, GQSPI_CNFG, GEN_FIFO_START) && 1091 ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE)) { 1092 s->man_start_com_g = true; 1093 } 1094 s->regs[reg] = value & ~(R_GQSPI_CNFG_GEN_FIFO_START_MASK); 1095 break; 1096 case R_GQSPI_GEN_FIFO: 1097 if (!fifo32_is_full(&s->fifo_g)) { 1098 fifo32_push(&s->fifo_g, value); 1099 } 1100 break; 1101 case R_GQSPI_TXD: 1102 tx_data_bytes(&s->tx_fifo_g, (uint32_t)value, 4, 1103 ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN)); 1104 break; 1105 case R_GQSPI_FIFO_CTRL: 1106 if (FIELD_EX32(value, GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET)) { 1107 fifo32_reset(&s->fifo_g); 1108 } 1109 if (FIELD_EX32(value, GQSPI_FIFO_CTRL, TX_FIFO_RESET)) { 1110 fifo8_reset(&s->tx_fifo_g); 1111 } 1112 if (FIELD_EX32(value, GQSPI_FIFO_CTRL, RX_FIFO_RESET)) { 1113 fifo8_reset(&s->rx_fifo_g); 1114 } 1115 break; 1116 case R_GQSPI_IDR: 1117 s->regs[R_GQSPI_IMR] |= value; 1118 break; 1119 case R_GQSPI_IER: 1120 s->regs[R_GQSPI_IMR] &= ~value; 1121 break; 1122 case R_GQSPI_ISR: 1123 s->regs[R_GQSPI_ISR] &= ~value; 1124 break; 1125 case R_GQSPI_IMR: 1126 case R_GQSPI_RXD: 1127 case R_GQSPI_GF_SNAPSHOT: 1128 case R_GQSPI_MOD_ID: 1129 break; 1130 default: 1131 s->regs[reg] = value; 1132 break; 1133 } 1134 xlnx_zynqmp_qspips_update_cs_lines(s); 1135 xlnx_zynqmp_qspips_check_flush(s); 1136 xlnx_zynqmp_qspips_update_cs_lines(s); 1137 xlnx_zynqmp_qspips_update_ixr(s); 1138 } 1139 xlnx_zynqmp_qspips_notify(s); 1140 } 1141 1142 static const MemoryRegionOps qspips_ops = { 1143 .read = xilinx_spips_read, 1144 .write = xilinx_qspips_write, 1145 .endianness = DEVICE_LITTLE_ENDIAN, 1146 }; 1147 1148 static const MemoryRegionOps xlnx_zynqmp_qspips_ops = { 1149 .read = xlnx_zynqmp_qspips_read, 1150 .write = xlnx_zynqmp_qspips_write, 1151 .endianness = DEVICE_LITTLE_ENDIAN, 1152 }; 1153 1154 #define LQSPI_CACHE_SIZE 1024 1155 1156 static void lqspi_load_cache(void *opaque, hwaddr addr) 1157 { 1158 XilinxQSPIPS *q = opaque; 1159 XilinxSPIPS *s = opaque; 1160 int i; 1161 int flash_addr = ((addr & ~(LQSPI_CACHE_SIZE - 1)) 1162 / num_effective_busses(s)); 1163 int peripheral = flash_addr >> LQSPI_ADDRESS_BITS; 1164 int cache_entry = 0; 1165 uint32_t u_page_save = s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE; 1166 1167 if (addr < q->lqspi_cached_addr || 1168 addr > q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { 1169 xilinx_qspips_invalidate_mmio_ptr(q); 1170 s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 1171 s->regs[R_LQSPI_STS] |= peripheral ? LQSPI_CFG_U_PAGE : 0; 1172 1173 DB_PRINT_L(0, "config reg status: %08x\n", s->regs[R_LQSPI_CFG]); 1174 1175 fifo8_reset(&s->tx_fifo); 1176 fifo8_reset(&s->rx_fifo); 1177 1178 /* instruction */ 1179 DB_PRINT_L(0, "pushing read instruction: %02x\n", 1180 (unsigned)(uint8_t)(s->regs[R_LQSPI_CFG] & 1181 LQSPI_CFG_INST_CODE)); 1182 fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE); 1183 /* read address */ 1184 DB_PRINT_L(0, "pushing read address %06x\n", flash_addr); 1185 if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_ADDR4) { 1186 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 24)); 1187 } 1188 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16)); 1189 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8)); 1190 fifo8_push(&s->tx_fifo, (uint8_t)flash_addr); 1191 /* mode bits */ 1192 if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) { 1193 fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG], 1194 LQSPI_CFG_MODE_SHIFT, 1195 LQSPI_CFG_MODE_WIDTH)); 1196 } 1197 /* dummy bytes */ 1198 for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT, 1199 LQSPI_CFG_DUMMY_WIDTH)); ++i) { 1200 DB_PRINT_L(0, "pushing dummy byte\n"); 1201 fifo8_push(&s->tx_fifo, 0); 1202 } 1203 xilinx_spips_update_cs_lines(s); 1204 xilinx_spips_flush_txfifo(s); 1205 fifo8_reset(&s->rx_fifo); 1206 1207 DB_PRINT_L(0, "starting QSPI data read\n"); 1208 1209 while (cache_entry < LQSPI_CACHE_SIZE) { 1210 for (i = 0; i < 64; ++i) { 1211 tx_data_bytes(&s->tx_fifo, 0, 1, false); 1212 } 1213 xilinx_spips_flush_txfifo(s); 1214 for (i = 0; i < 64; ++i) { 1215 rx_data_bytes(&s->rx_fifo, &q->lqspi_buf[cache_entry++], 1); 1216 } 1217 } 1218 1219 s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 1220 s->regs[R_LQSPI_STS] |= u_page_save; 1221 xilinx_spips_update_cs_lines(s); 1222 1223 q->lqspi_cached_addr = flash_addr * num_effective_busses(s); 1224 } 1225 } 1226 1227 static MemTxResult lqspi_read(void *opaque, hwaddr addr, uint64_t *value, 1228 unsigned size, MemTxAttrs attrs) 1229 { 1230 XilinxQSPIPS *q = XILINX_QSPIPS(opaque); 1231 1232 if (addr >= q->lqspi_cached_addr && 1233 addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { 1234 uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr]; 1235 *value = cpu_to_le32(*(uint32_t *)retp); 1236 DB_PRINT_L(1, "addr: %08" HWADDR_PRIx ", data: %08" PRIx64 "\n", 1237 addr, *value); 1238 return MEMTX_OK; 1239 } 1240 1241 lqspi_load_cache(opaque, addr); 1242 return lqspi_read(opaque, addr, value, size, attrs); 1243 } 1244 1245 static MemTxResult lqspi_write(void *opaque, hwaddr offset, uint64_t value, 1246 unsigned size, MemTxAttrs attrs) 1247 { 1248 /* 1249 * From UG1085, Chapter 24 (Quad-SPI controllers): 1250 * - Writes are ignored 1251 * - AXI writes generate an external AXI slave error (SLVERR) 1252 */ 1253 qemu_log_mask(LOG_GUEST_ERROR, "%s Unexpected %u-bit access to 0x%" PRIx64 1254 " (value: 0x%" PRIx64 "\n", 1255 __func__, size << 3, offset, value); 1256 1257 return MEMTX_ERROR; 1258 } 1259 1260 static const MemoryRegionOps lqspi_ops = { 1261 .read_with_attrs = lqspi_read, 1262 .write_with_attrs = lqspi_write, 1263 .endianness = DEVICE_NATIVE_ENDIAN, 1264 .impl = { 1265 .min_access_size = 4, 1266 .max_access_size = 4, 1267 }, 1268 .valid = { 1269 .min_access_size = 1, 1270 .max_access_size = 4 1271 } 1272 }; 1273 1274 static void xilinx_spips_realize(DeviceState *dev, Error **errp) 1275 { 1276 XilinxSPIPS *s = XILINX_SPIPS(dev); 1277 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1278 XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s); 1279 int i; 1280 1281 DB_PRINT_L(0, "realized spips\n"); 1282 1283 if (s->num_busses > MAX_NUM_BUSSES) { 1284 error_setg(errp, 1285 "requested number of SPI busses %u exceeds maximum %d", 1286 s->num_busses, MAX_NUM_BUSSES); 1287 return; 1288 } 1289 if (s->num_busses < MIN_NUM_BUSSES) { 1290 error_setg(errp, 1291 "requested number of SPI busses %u is below minimum %d", 1292 s->num_busses, MIN_NUM_BUSSES); 1293 return; 1294 } 1295 1296 s->spi = g_new(SSIBus *, s->num_busses); 1297 for (i = 0; i < s->num_busses; ++i) { 1298 char bus_name[16]; 1299 snprintf(bus_name, 16, "spi%d", i); 1300 s->spi[i] = ssi_create_bus(dev, bus_name); 1301 } 1302 1303 s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses); 1304 s->cs_lines_state = g_new0(bool, s->num_cs * s->num_busses); 1305 1306 sysbus_init_irq(sbd, &s->irq); 1307 for (i = 0; i < s->num_cs * s->num_busses; ++i) { 1308 sysbus_init_irq(sbd, &s->cs_lines[i]); 1309 } 1310 1311 memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s, 1312 "spi", XLNX_ZYNQMP_SPIPS_R_MAX * 4); 1313 sysbus_init_mmio(sbd, &s->iomem); 1314 1315 s->irqline = -1; 1316 1317 fifo8_create(&s->rx_fifo, xsc->rx_fifo_size); 1318 fifo8_create(&s->tx_fifo, xsc->tx_fifo_size); 1319 } 1320 1321 static void xilinx_qspips_realize(DeviceState *dev, Error **errp) 1322 { 1323 XilinxSPIPS *s = XILINX_SPIPS(dev); 1324 XilinxQSPIPS *q = XILINX_QSPIPS(dev); 1325 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1326 1327 DB_PRINT_L(0, "realized qspips\n"); 1328 1329 s->num_busses = 2; 1330 s->num_cs = 2; 1331 s->num_txrx_bytes = 4; 1332 1333 xilinx_spips_realize(dev, errp); 1334 memory_region_init_io(&s->mmlqspi, OBJECT(s), &lqspi_ops, s, "lqspi", 1335 (1 << LQSPI_ADDRESS_BITS) * 2); 1336 sysbus_init_mmio(sbd, &s->mmlqspi); 1337 1338 q->lqspi_cached_addr = ~0ULL; 1339 } 1340 1341 static void xlnx_zynqmp_qspips_realize(DeviceState *dev, Error **errp) 1342 { 1343 XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(dev); 1344 XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s); 1345 1346 if (s->dma_burst_size > QSPI_DMA_MAX_BURST_SIZE) { 1347 error_setg(errp, 1348 "qspi dma burst size %u exceeds maximum limit %d", 1349 s->dma_burst_size, QSPI_DMA_MAX_BURST_SIZE); 1350 return; 1351 } 1352 xilinx_qspips_realize(dev, errp); 1353 fifo8_create(&s->rx_fifo_g, xsc->rx_fifo_size); 1354 fifo8_create(&s->tx_fifo_g, xsc->tx_fifo_size); 1355 fifo32_create(&s->fifo_g, 32); 1356 } 1357 1358 static void xlnx_zynqmp_qspips_init(Object *obj) 1359 { 1360 XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(obj); 1361 1362 object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SINK, 1363 (Object **)&rq->dma, 1364 object_property_allow_set_link, 1365 OBJ_PROP_LINK_STRONG); 1366 } 1367 1368 static int xilinx_spips_post_load(void *opaque, int version_id) 1369 { 1370 xilinx_spips_update_ixr((XilinxSPIPS *)opaque); 1371 xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque); 1372 return 0; 1373 } 1374 1375 static const VMStateDescription vmstate_xilinx_spips = { 1376 .name = "xilinx_spips", 1377 .version_id = 2, 1378 .minimum_version_id = 2, 1379 .post_load = xilinx_spips_post_load, 1380 .fields = (VMStateField[]) { 1381 VMSTATE_FIFO8(tx_fifo, XilinxSPIPS), 1382 VMSTATE_FIFO8(rx_fifo, XilinxSPIPS), 1383 VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, XLNX_SPIPS_R_MAX), 1384 VMSTATE_UINT8(snoop_state, XilinxSPIPS), 1385 VMSTATE_END_OF_LIST() 1386 } 1387 }; 1388 1389 static int xlnx_zynqmp_qspips_post_load(void *opaque, int version_id) 1390 { 1391 XlnxZynqMPQSPIPS *s = (XlnxZynqMPQSPIPS *)opaque; 1392 XilinxSPIPS *qs = XILINX_SPIPS(s); 1393 1394 if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN) && 1395 fifo8_is_empty(&qs->rx_fifo) && fifo8_is_empty(&qs->tx_fifo)) { 1396 xlnx_zynqmp_qspips_update_ixr(s); 1397 xlnx_zynqmp_qspips_update_cs_lines(s); 1398 } 1399 return 0; 1400 } 1401 1402 static const VMStateDescription vmstate_xilinx_qspips = { 1403 .name = "xilinx_qspips", 1404 .version_id = 1, 1405 .minimum_version_id = 1, 1406 .fields = (VMStateField[]) { 1407 VMSTATE_STRUCT(parent_obj, XilinxQSPIPS, 0, 1408 vmstate_xilinx_spips, XilinxSPIPS), 1409 VMSTATE_END_OF_LIST() 1410 } 1411 }; 1412 1413 static const VMStateDescription vmstate_xlnx_zynqmp_qspips = { 1414 .name = "xlnx_zynqmp_qspips", 1415 .version_id = 1, 1416 .minimum_version_id = 1, 1417 .post_load = xlnx_zynqmp_qspips_post_load, 1418 .fields = (VMStateField[]) { 1419 VMSTATE_STRUCT(parent_obj, XlnxZynqMPQSPIPS, 0, 1420 vmstate_xilinx_qspips, XilinxQSPIPS), 1421 VMSTATE_FIFO8(tx_fifo_g, XlnxZynqMPQSPIPS), 1422 VMSTATE_FIFO8(rx_fifo_g, XlnxZynqMPQSPIPS), 1423 VMSTATE_FIFO32(fifo_g, XlnxZynqMPQSPIPS), 1424 VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPQSPIPS, XLNX_ZYNQMP_SPIPS_R_MAX), 1425 VMSTATE_END_OF_LIST() 1426 } 1427 }; 1428 1429 static Property xilinx_zynqmp_qspips_properties[] = { 1430 DEFINE_PROP_UINT32("dma-burst-size", XlnxZynqMPQSPIPS, dma_burst_size, 64), 1431 DEFINE_PROP_END_OF_LIST(), 1432 }; 1433 1434 static Property xilinx_spips_properties[] = { 1435 DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1), 1436 DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4), 1437 DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1), 1438 DEFINE_PROP_END_OF_LIST(), 1439 }; 1440 1441 static void xilinx_qspips_class_init(ObjectClass *klass, void * data) 1442 { 1443 DeviceClass *dc = DEVICE_CLASS(klass); 1444 XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 1445 1446 dc->realize = xilinx_qspips_realize; 1447 xsc->reg_ops = &qspips_ops; 1448 xsc->rx_fifo_size = RXFF_A_Q; 1449 xsc->tx_fifo_size = TXFF_A_Q; 1450 } 1451 1452 static void xilinx_spips_class_init(ObjectClass *klass, void *data) 1453 { 1454 DeviceClass *dc = DEVICE_CLASS(klass); 1455 XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 1456 1457 dc->realize = xilinx_spips_realize; 1458 dc->reset = xilinx_spips_reset; 1459 device_class_set_props(dc, xilinx_spips_properties); 1460 dc->vmsd = &vmstate_xilinx_spips; 1461 1462 xsc->reg_ops = &spips_ops; 1463 xsc->rx_fifo_size = RXFF_A; 1464 xsc->tx_fifo_size = TXFF_A; 1465 } 1466 1467 static void xlnx_zynqmp_qspips_class_init(ObjectClass *klass, void * data) 1468 { 1469 DeviceClass *dc = DEVICE_CLASS(klass); 1470 XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 1471 1472 dc->realize = xlnx_zynqmp_qspips_realize; 1473 dc->reset = xlnx_zynqmp_qspips_reset; 1474 dc->vmsd = &vmstate_xlnx_zynqmp_qspips; 1475 device_class_set_props(dc, xilinx_zynqmp_qspips_properties); 1476 xsc->reg_ops = &xlnx_zynqmp_qspips_ops; 1477 xsc->rx_fifo_size = RXFF_A_Q; 1478 xsc->tx_fifo_size = TXFF_A_Q; 1479 } 1480 1481 static const TypeInfo xilinx_spips_info = { 1482 .name = TYPE_XILINX_SPIPS, 1483 .parent = TYPE_SYS_BUS_DEVICE, 1484 .instance_size = sizeof(XilinxSPIPS), 1485 .class_init = xilinx_spips_class_init, 1486 .class_size = sizeof(XilinxSPIPSClass), 1487 }; 1488 1489 static const TypeInfo xilinx_qspips_info = { 1490 .name = TYPE_XILINX_QSPIPS, 1491 .parent = TYPE_XILINX_SPIPS, 1492 .instance_size = sizeof(XilinxQSPIPS), 1493 .class_init = xilinx_qspips_class_init, 1494 }; 1495 1496 static const TypeInfo xlnx_zynqmp_qspips_info = { 1497 .name = TYPE_XLNX_ZYNQMP_QSPIPS, 1498 .parent = TYPE_XILINX_QSPIPS, 1499 .instance_size = sizeof(XlnxZynqMPQSPIPS), 1500 .instance_init = xlnx_zynqmp_qspips_init, 1501 .class_init = xlnx_zynqmp_qspips_class_init, 1502 }; 1503 1504 static void xilinx_spips_register_types(void) 1505 { 1506 type_register_static(&xilinx_spips_info); 1507 type_register_static(&xilinx_qspips_info); 1508 type_register_static(&xlnx_zynqmp_qspips_info); 1509 } 1510 1511 type_init(xilinx_spips_register_types) 1512