1 /* 2 * QEMU model of the Xilinx Zynq SPI controller 3 * 4 * Copyright (c) 2012 Peter A. G. Crosthwaite 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/sysbus.h" 27 #include "sysemu/sysemu.h" 28 #include "hw/ptimer.h" 29 #include "qemu/log.h" 30 #include "qemu/bitops.h" 31 #include "hw/ssi/xilinx_spips.h" 32 #include "qapi/error.h" 33 #include "hw/register.h" 34 #include "migration/blocker.h" 35 36 #ifndef XILINX_SPIPS_ERR_DEBUG 37 #define XILINX_SPIPS_ERR_DEBUG 0 38 #endif 39 40 #define DB_PRINT_L(level, ...) do { \ 41 if (XILINX_SPIPS_ERR_DEBUG > (level)) { \ 42 fprintf(stderr, ": %s: ", __func__); \ 43 fprintf(stderr, ## __VA_ARGS__); \ 44 } \ 45 } while (0); 46 47 /* config register */ 48 #define R_CONFIG (0x00 / 4) 49 #define IFMODE (1U << 31) 50 #define R_CONFIG_ENDIAN (1 << 26) 51 #define MODEFAIL_GEN_EN (1 << 17) 52 #define MAN_START_COM (1 << 16) 53 #define MAN_START_EN (1 << 15) 54 #define MANUAL_CS (1 << 14) 55 #define CS (0xF << 10) 56 #define CS_SHIFT (10) 57 #define PERI_SEL (1 << 9) 58 #define REF_CLK (1 << 8) 59 #define FIFO_WIDTH (3 << 6) 60 #define BAUD_RATE_DIV (7 << 3) 61 #define CLK_PH (1 << 2) 62 #define CLK_POL (1 << 1) 63 #define MODE_SEL (1 << 0) 64 #define R_CONFIG_RSVD (0x7bf40000) 65 66 /* interrupt mechanism */ 67 #define R_INTR_STATUS (0x04 / 4) 68 #define R_INTR_EN (0x08 / 4) 69 #define R_INTR_DIS (0x0C / 4) 70 #define R_INTR_MASK (0x10 / 4) 71 #define IXR_TX_FIFO_UNDERFLOW (1 << 6) 72 #define IXR_RX_FIFO_FULL (1 << 5) 73 #define IXR_RX_FIFO_NOT_EMPTY (1 << 4) 74 #define IXR_TX_FIFO_FULL (1 << 3) 75 #define IXR_TX_FIFO_NOT_FULL (1 << 2) 76 #define IXR_TX_FIFO_MODE_FAIL (1 << 1) 77 #define IXR_RX_FIFO_OVERFLOW (1 << 0) 78 #define IXR_ALL ((IXR_TX_FIFO_UNDERFLOW<<1)-1) 79 80 #define R_EN (0x14 / 4) 81 #define R_DELAY (0x18 / 4) 82 #define R_TX_DATA (0x1C / 4) 83 #define R_RX_DATA (0x20 / 4) 84 #define R_SLAVE_IDLE_COUNT (0x24 / 4) 85 #define R_TX_THRES (0x28 / 4) 86 #define R_RX_THRES (0x2C / 4) 87 #define R_TXD1 (0x80 / 4) 88 #define R_TXD2 (0x84 / 4) 89 #define R_TXD3 (0x88 / 4) 90 91 #define R_LQSPI_CFG (0xa0 / 4) 92 #define R_LQSPI_CFG_RESET 0x03A002EB 93 #define LQSPI_CFG_LQ_MODE (1U << 31) 94 #define LQSPI_CFG_TWO_MEM (1 << 30) 95 #define LQSPI_CFG_SEP_BUS (1 << 29) 96 #define LQSPI_CFG_U_PAGE (1 << 28) 97 #define LQSPI_CFG_ADDR4 (1 << 27) 98 #define LQSPI_CFG_MODE_EN (1 << 25) 99 #define LQSPI_CFG_MODE_WIDTH 8 100 #define LQSPI_CFG_MODE_SHIFT 16 101 #define LQSPI_CFG_DUMMY_WIDTH 3 102 #define LQSPI_CFG_DUMMY_SHIFT 8 103 #define LQSPI_CFG_INST_CODE 0xFF 104 105 #define R_CMND (0xc0 / 4) 106 #define R_CMND_RXFIFO_DRAIN (1 << 19) 107 FIELD(CMND, PARTIAL_BYTE_LEN, 16, 3) 108 #define R_CMND_EXT_ADD (1 << 15) 109 FIELD(CMND, RX_DISCARD, 8, 7) 110 FIELD(CMND, DUMMY_CYCLES, 2, 6) 111 #define R_CMND_DMA_EN (1 << 1) 112 #define R_CMND_PUSH_WAIT (1 << 0) 113 #define R_TRANSFER_SIZE (0xc4 / 4) 114 #define R_LQSPI_STS (0xA4 / 4) 115 #define LQSPI_STS_WR_RECVD (1 << 1) 116 117 #define R_MOD_ID (0xFC / 4) 118 119 /* size of TXRX FIFOs */ 120 #define RXFF_A 32 121 #define TXFF_A 32 122 123 #define RXFF_A_Q (64 * 4) 124 #define TXFF_A_Q (64 * 4) 125 126 /* 16MB per linear region */ 127 #define LQSPI_ADDRESS_BITS 24 128 129 #define SNOOP_CHECKING 0xFF 130 #define SNOOP_ADDR 0xF0 131 #define SNOOP_NONE 0xEE 132 #define SNOOP_STRIPING 0 133 134 static inline int num_effective_busses(XilinxSPIPS *s) 135 { 136 return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && 137 s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1; 138 } 139 140 static inline bool xilinx_spips_cs_is_set(XilinxSPIPS *s, int i, int field) 141 { 142 return ~field & (1 << i) && (s->regs[R_CONFIG] & MANUAL_CS 143 || !fifo8_is_empty(&s->tx_fifo)); 144 } 145 146 static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) 147 { 148 int i, j; 149 bool found = false; 150 int field = s->regs[R_CONFIG] >> CS_SHIFT; 151 152 for (i = 0; i < s->num_cs; i++) { 153 for (j = 0; j < num_effective_busses(s); j++) { 154 int upage = !!(s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE); 155 int cs_to_set = (j * s->num_cs + i + upage) % 156 (s->num_cs * s->num_busses); 157 158 if (xilinx_spips_cs_is_set(s, i, field) && !found) { 159 DB_PRINT_L(0, "selecting slave %d\n", i); 160 qemu_set_irq(s->cs_lines[cs_to_set], 0); 161 if (s->cs_lines_state[cs_to_set]) { 162 s->cs_lines_state[cs_to_set] = false; 163 s->rx_discard = ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD); 164 } 165 } else { 166 DB_PRINT_L(0, "deselecting slave %d\n", i); 167 qemu_set_irq(s->cs_lines[cs_to_set], 1); 168 s->cs_lines_state[cs_to_set] = true; 169 } 170 } 171 if (xilinx_spips_cs_is_set(s, i, field)) { 172 found = true; 173 } 174 } 175 if (!found) { 176 s->snoop_state = SNOOP_CHECKING; 177 s->cmd_dummies = 0; 178 s->link_state = 1; 179 s->link_state_next = 1; 180 s->link_state_next_when = 0; 181 DB_PRINT_L(1, "moving to snoop check state\n"); 182 } 183 } 184 185 static void xilinx_spips_update_ixr(XilinxSPIPS *s) 186 { 187 if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE) { 188 return; 189 } 190 /* These are set/cleared as they occur */ 191 s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW | 192 IXR_TX_FIFO_MODE_FAIL); 193 /* these are pure functions of fifo state, set them here */ 194 s->regs[R_INTR_STATUS] |= 195 (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) | 196 (s->rx_fifo.num >= s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY : 0) | 197 (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | 198 (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0); 199 /* drive external interrupt pin */ 200 int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] & 201 IXR_ALL); 202 if (new_irqline != s->irqline) { 203 s->irqline = new_irqline; 204 qemu_set_irq(s->irq, s->irqline); 205 } 206 } 207 208 static void xilinx_spips_reset(DeviceState *d) 209 { 210 XilinxSPIPS *s = XILINX_SPIPS(d); 211 212 int i; 213 for (i = 0; i < XLNX_SPIPS_R_MAX; i++) { 214 s->regs[i] = 0; 215 } 216 217 fifo8_reset(&s->rx_fifo); 218 fifo8_reset(&s->rx_fifo); 219 /* non zero resets */ 220 s->regs[R_CONFIG] |= MODEFAIL_GEN_EN; 221 s->regs[R_SLAVE_IDLE_COUNT] = 0xFF; 222 s->regs[R_TX_THRES] = 1; 223 s->regs[R_RX_THRES] = 1; 224 /* FIXME: move magic number definition somewhere sensible */ 225 s->regs[R_MOD_ID] = 0x01090106; 226 s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET; 227 s->link_state = 1; 228 s->link_state_next = 1; 229 s->link_state_next_when = 0; 230 s->snoop_state = SNOOP_CHECKING; 231 s->cmd_dummies = 0; 232 s->man_start_com = false; 233 xilinx_spips_update_ixr(s); 234 xilinx_spips_update_cs_lines(s); 235 } 236 237 /* N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) 238 * column wise (from element 0 to N-1). num is the length of x, and dir 239 * reverses the direction of the transform. Best illustrated by example: 240 * Each digit in the below array is a single bit (num == 3): 241 * 242 * {{ 76543210, } ----- stripe (dir == false) -----> {{ 741gdaFC, } 243 * { hgfedcba, } { 630fcHEB, } 244 * { HGFEDCBA, }} <---- upstripe (dir == true) ----- { 52hebGDA, }} 245 */ 246 247 static inline void stripe8(uint8_t *x, int num, bool dir) 248 { 249 uint8_t r[num]; 250 memset(r, 0, sizeof(uint8_t) * num); 251 int idx[2] = {0, 0}; 252 int bit[2] = {0, 7}; 253 int d = dir; 254 255 for (idx[0] = 0; idx[0] < num; ++idx[0]) { 256 for (bit[0] = 7; bit[0] >= 0; bit[0]--) { 257 r[idx[!d]] |= x[idx[d]] & 1 << bit[d] ? 1 << bit[!d] : 0; 258 idx[1] = (idx[1] + 1) % num; 259 if (!idx[1]) { 260 bit[1]--; 261 } 262 } 263 } 264 memcpy(x, r, sizeof(uint8_t) * num); 265 } 266 267 static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command) 268 { 269 if (!qs) { 270 /* The SPI device is not a QSPI device */ 271 return -1; 272 } 273 274 switch (command) { /* check for dummies */ 275 case READ: /* no dummy bytes/cycles */ 276 case PP: 277 case DPP: 278 case QPP: 279 case READ_4: 280 case PP_4: 281 case QPP_4: 282 return 0; 283 case FAST_READ: 284 case DOR: 285 case QOR: 286 case DOR_4: 287 case QOR_4: 288 return 1; 289 case DIOR: 290 case FAST_READ_4: 291 case DIOR_4: 292 return 2; 293 case QIOR: 294 case QIOR_4: 295 return 5; 296 default: 297 return -1; 298 } 299 } 300 301 static inline uint8_t get_addr_length(XilinxSPIPS *s, uint8_t cmd) 302 { 303 switch (cmd) { 304 case PP_4: 305 case QPP_4: 306 case READ_4: 307 case QIOR_4: 308 case FAST_READ_4: 309 case DOR_4: 310 case QOR_4: 311 case DIOR_4: 312 return 4; 313 default: 314 return (s->regs[R_CMND] & R_CMND_EXT_ADD) ? 4 : 3; 315 } 316 } 317 318 static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) 319 { 320 int debug_level = 0; 321 XilinxQSPIPS *q = (XilinxQSPIPS *) object_dynamic_cast(OBJECT(s), 322 TYPE_XILINX_QSPIPS); 323 324 for (;;) { 325 int i; 326 uint8_t tx = 0; 327 uint8_t tx_rx[num_effective_busses(s)]; 328 uint8_t dummy_cycles = 0; 329 uint8_t addr_length; 330 331 if (fifo8_is_empty(&s->tx_fifo)) { 332 xilinx_spips_update_ixr(s); 333 return; 334 } else if (s->snoop_state == SNOOP_STRIPING) { 335 for (i = 0; i < num_effective_busses(s); ++i) { 336 tx_rx[i] = fifo8_pop(&s->tx_fifo); 337 } 338 stripe8(tx_rx, num_effective_busses(s), false); 339 } else if (s->snoop_state >= SNOOP_ADDR) { 340 tx = fifo8_pop(&s->tx_fifo); 341 for (i = 0; i < num_effective_busses(s); ++i) { 342 tx_rx[i] = tx; 343 } 344 } else { 345 /* Extract a dummy byte and generate dummy cycles according to the 346 * link state */ 347 tx = fifo8_pop(&s->tx_fifo); 348 dummy_cycles = 8 / s->link_state; 349 } 350 351 for (i = 0; i < num_effective_busses(s); ++i) { 352 int bus = num_effective_busses(s) - 1 - i; 353 if (dummy_cycles) { 354 int d; 355 for (d = 0; d < dummy_cycles; ++d) { 356 tx_rx[0] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[0]); 357 } 358 } else { 359 DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]); 360 tx_rx[i] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]); 361 DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]); 362 } 363 } 364 365 if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { 366 DB_PRINT_L(debug_level, "dircarding drained rx byte\n"); 367 /* Do nothing */ 368 } else if (s->rx_discard) { 369 DB_PRINT_L(debug_level, "dircarding discarded rx byte\n"); 370 s->rx_discard -= 8 / s->link_state; 371 } else if (fifo8_is_full(&s->rx_fifo)) { 372 s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW; 373 DB_PRINT_L(0, "rx FIFO overflow"); 374 } else if (s->snoop_state == SNOOP_STRIPING) { 375 stripe8(tx_rx, num_effective_busses(s), true); 376 for (i = 0; i < num_effective_busses(s); ++i) { 377 fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]); 378 DB_PRINT_L(debug_level, "pushing striped rx byte\n"); 379 } 380 } else { 381 DB_PRINT_L(debug_level, "pushing unstriped rx byte\n"); 382 fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]); 383 } 384 385 if (s->link_state_next_when) { 386 s->link_state_next_when--; 387 if (!s->link_state_next_when) { 388 s->link_state = s->link_state_next; 389 } 390 } 391 392 DB_PRINT_L(debug_level, "initial snoop state: %x\n", 393 (unsigned)s->snoop_state); 394 switch (s->snoop_state) { 395 case (SNOOP_CHECKING): 396 /* Store the count of dummy bytes in the txfifo */ 397 s->cmd_dummies = xilinx_spips_num_dummies(q, tx); 398 addr_length = get_addr_length(s, tx); 399 if (s->cmd_dummies < 0) { 400 s->snoop_state = SNOOP_NONE; 401 } else { 402 s->snoop_state = SNOOP_ADDR + addr_length - 1; 403 } 404 switch (tx) { 405 case DPP: 406 case DOR: 407 case DOR_4: 408 s->link_state_next = 2; 409 s->link_state_next_when = addr_length + s->cmd_dummies; 410 break; 411 case QPP: 412 case QPP_4: 413 case QOR: 414 case QOR_4: 415 s->link_state_next = 4; 416 s->link_state_next_when = addr_length + s->cmd_dummies; 417 break; 418 case DIOR: 419 case DIOR_4: 420 s->link_state = 2; 421 break; 422 case QIOR: 423 case QIOR_4: 424 s->link_state = 4; 425 break; 426 } 427 break; 428 case (SNOOP_ADDR): 429 /* Address has been transmitted, transmit dummy cycles now if 430 * needed */ 431 if (s->cmd_dummies < 0) { 432 s->snoop_state = SNOOP_NONE; 433 } else { 434 s->snoop_state = s->cmd_dummies; 435 } 436 break; 437 case (SNOOP_STRIPING): 438 case (SNOOP_NONE): 439 /* Once we hit the boring stuff - squelch debug noise */ 440 if (!debug_level) { 441 DB_PRINT_L(0, "squelching debug info ....\n"); 442 debug_level = 1; 443 } 444 break; 445 default: 446 s->snoop_state--; 447 } 448 DB_PRINT_L(debug_level, "final snoop state: %x\n", 449 (unsigned)s->snoop_state); 450 } 451 } 452 453 static inline void tx_data_bytes(Fifo8 *fifo, uint32_t value, int num, bool be) 454 { 455 int i; 456 for (i = 0; i < num && !fifo8_is_full(fifo); ++i) { 457 if (be) { 458 fifo8_push(fifo, (uint8_t)(value >> 24)); 459 value <<= 8; 460 } else { 461 fifo8_push(fifo, (uint8_t)value); 462 value >>= 8; 463 } 464 } 465 } 466 467 static void xilinx_spips_check_zero_pump(XilinxSPIPS *s) 468 { 469 if (!s->regs[R_TRANSFER_SIZE]) { 470 return; 471 } 472 if (!fifo8_is_empty(&s->tx_fifo) && s->regs[R_CMND] & R_CMND_PUSH_WAIT) { 473 return; 474 } 475 /* 476 * The zero pump must never fill tx fifo such that rx overflow is 477 * possible 478 */ 479 while (s->regs[R_TRANSFER_SIZE] && 480 s->rx_fifo.num + s->tx_fifo.num < RXFF_A_Q - 3) { 481 /* endianess just doesn't matter when zero pumping */ 482 tx_data_bytes(&s->tx_fifo, 0, 4, false); 483 s->regs[R_TRANSFER_SIZE] &= ~0x03ull; 484 s->regs[R_TRANSFER_SIZE] -= 4; 485 } 486 } 487 488 static void xilinx_spips_check_flush(XilinxSPIPS *s) 489 { 490 if (s->man_start_com || 491 (!fifo8_is_empty(&s->tx_fifo) && 492 !(s->regs[R_CONFIG] & MAN_START_EN))) { 493 xilinx_spips_check_zero_pump(s); 494 xilinx_spips_flush_txfifo(s); 495 } 496 if (fifo8_is_empty(&s->tx_fifo) && !s->regs[R_TRANSFER_SIZE]) { 497 s->man_start_com = false; 498 } 499 xilinx_spips_update_ixr(s); 500 } 501 502 static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max) 503 { 504 int i; 505 506 for (i = 0; i < max && !fifo8_is_empty(fifo); ++i) { 507 value[i] = fifo8_pop(fifo); 508 } 509 return max - i; 510 } 511 512 static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, 513 unsigned size) 514 { 515 XilinxSPIPS *s = opaque; 516 uint32_t mask = ~0; 517 uint32_t ret; 518 uint8_t rx_buf[4]; 519 int shortfall; 520 521 addr >>= 2; 522 switch (addr) { 523 case R_CONFIG: 524 mask = ~(R_CONFIG_RSVD | MAN_START_COM); 525 break; 526 case R_INTR_STATUS: 527 ret = s->regs[addr] & IXR_ALL; 528 s->regs[addr] = 0; 529 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 530 xilinx_spips_update_ixr(s); 531 return ret; 532 case R_INTR_MASK: 533 mask = IXR_ALL; 534 break; 535 case R_EN: 536 mask = 0x1; 537 break; 538 case R_SLAVE_IDLE_COUNT: 539 mask = 0xFF; 540 break; 541 case R_MOD_ID: 542 mask = 0x01FFFFFF; 543 break; 544 case R_INTR_EN: 545 case R_INTR_DIS: 546 case R_TX_DATA: 547 mask = 0; 548 break; 549 case R_RX_DATA: 550 memset(rx_buf, 0, sizeof(rx_buf)); 551 shortfall = rx_data_bytes(&s->rx_fifo, rx_buf, s->num_txrx_bytes); 552 ret = s->regs[R_CONFIG] & R_CONFIG_ENDIAN ? 553 cpu_to_be32(*(uint32_t *)rx_buf) : 554 cpu_to_le32(*(uint32_t *)rx_buf); 555 if (!(s->regs[R_CONFIG] & R_CONFIG_ENDIAN)) { 556 ret <<= 8 * shortfall; 557 } 558 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 559 xilinx_spips_update_ixr(s); 560 return ret; 561 } 562 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, 563 s->regs[addr] & mask); 564 return s->regs[addr] & mask; 565 566 } 567 568 static void xilinx_spips_write(void *opaque, hwaddr addr, 569 uint64_t value, unsigned size) 570 { 571 int mask = ~0; 572 XilinxSPIPS *s = opaque; 573 574 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value); 575 addr >>= 2; 576 switch (addr) { 577 case R_CONFIG: 578 mask = ~(R_CONFIG_RSVD | MAN_START_COM); 579 if ((value & MAN_START_COM) && (s->regs[R_CONFIG] & MAN_START_EN)) { 580 s->man_start_com = true; 581 } 582 break; 583 case R_INTR_STATUS: 584 mask = IXR_ALL; 585 s->regs[R_INTR_STATUS] &= ~(mask & value); 586 goto no_reg_update; 587 case R_INTR_DIS: 588 mask = IXR_ALL; 589 s->regs[R_INTR_MASK] &= ~(mask & value); 590 goto no_reg_update; 591 case R_INTR_EN: 592 mask = IXR_ALL; 593 s->regs[R_INTR_MASK] |= mask & value; 594 goto no_reg_update; 595 case R_EN: 596 mask = 0x1; 597 break; 598 case R_SLAVE_IDLE_COUNT: 599 mask = 0xFF; 600 break; 601 case R_RX_DATA: 602 case R_INTR_MASK: 603 case R_MOD_ID: 604 mask = 0; 605 break; 606 case R_TX_DATA: 607 tx_data_bytes(&s->tx_fifo, (uint32_t)value, s->num_txrx_bytes, 608 s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 609 goto no_reg_update; 610 case R_TXD1: 611 tx_data_bytes(&s->tx_fifo, (uint32_t)value, 1, 612 s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 613 goto no_reg_update; 614 case R_TXD2: 615 tx_data_bytes(&s->tx_fifo, (uint32_t)value, 2, 616 s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 617 goto no_reg_update; 618 case R_TXD3: 619 tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3, 620 s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 621 goto no_reg_update; 622 } 623 s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); 624 no_reg_update: 625 xilinx_spips_update_cs_lines(s); 626 xilinx_spips_check_flush(s); 627 xilinx_spips_update_cs_lines(s); 628 xilinx_spips_update_ixr(s); 629 } 630 631 static const MemoryRegionOps spips_ops = { 632 .read = xilinx_spips_read, 633 .write = xilinx_spips_write, 634 .endianness = DEVICE_LITTLE_ENDIAN, 635 }; 636 637 static void xilinx_qspips_invalidate_mmio_ptr(XilinxQSPIPS *q) 638 { 639 XilinxSPIPS *s = &q->parent_obj; 640 641 if ((q->mmio_execution_enabled) && (q->lqspi_cached_addr != ~0ULL)) { 642 /* Invalidate the current mapped mmio */ 643 memory_region_invalidate_mmio_ptr(&s->mmlqspi, q->lqspi_cached_addr, 644 LQSPI_CACHE_SIZE); 645 } 646 647 q->lqspi_cached_addr = ~0ULL; 648 } 649 650 static void xilinx_qspips_write(void *opaque, hwaddr addr, 651 uint64_t value, unsigned size) 652 { 653 XilinxQSPIPS *q = XILINX_QSPIPS(opaque); 654 XilinxSPIPS *s = XILINX_SPIPS(opaque); 655 656 xilinx_spips_write(opaque, addr, value, size); 657 addr >>= 2; 658 659 if (addr == R_LQSPI_CFG) { 660 xilinx_qspips_invalidate_mmio_ptr(q); 661 } 662 if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { 663 fifo8_reset(&s->rx_fifo); 664 } 665 } 666 667 static const MemoryRegionOps qspips_ops = { 668 .read = xilinx_spips_read, 669 .write = xilinx_qspips_write, 670 .endianness = DEVICE_LITTLE_ENDIAN, 671 }; 672 673 #define LQSPI_CACHE_SIZE 1024 674 675 static void lqspi_load_cache(void *opaque, hwaddr addr) 676 { 677 XilinxQSPIPS *q = opaque; 678 XilinxSPIPS *s = opaque; 679 int i; 680 int flash_addr = ((addr & ~(LQSPI_CACHE_SIZE - 1)) 681 / num_effective_busses(s)); 682 int slave = flash_addr >> LQSPI_ADDRESS_BITS; 683 int cache_entry = 0; 684 uint32_t u_page_save = s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE; 685 686 if (addr < q->lqspi_cached_addr || 687 addr > q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { 688 xilinx_qspips_invalidate_mmio_ptr(q); 689 s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 690 s->regs[R_LQSPI_STS] |= slave ? LQSPI_CFG_U_PAGE : 0; 691 692 DB_PRINT_L(0, "config reg status: %08x\n", s->regs[R_LQSPI_CFG]); 693 694 fifo8_reset(&s->tx_fifo); 695 fifo8_reset(&s->rx_fifo); 696 697 /* instruction */ 698 DB_PRINT_L(0, "pushing read instruction: %02x\n", 699 (unsigned)(uint8_t)(s->regs[R_LQSPI_CFG] & 700 LQSPI_CFG_INST_CODE)); 701 fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE); 702 /* read address */ 703 DB_PRINT_L(0, "pushing read address %06x\n", flash_addr); 704 if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_ADDR4) { 705 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 24)); 706 } 707 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16)); 708 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8)); 709 fifo8_push(&s->tx_fifo, (uint8_t)flash_addr); 710 /* mode bits */ 711 if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) { 712 fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG], 713 LQSPI_CFG_MODE_SHIFT, 714 LQSPI_CFG_MODE_WIDTH)); 715 } 716 /* dummy bytes */ 717 for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT, 718 LQSPI_CFG_DUMMY_WIDTH)); ++i) { 719 DB_PRINT_L(0, "pushing dummy byte\n"); 720 fifo8_push(&s->tx_fifo, 0); 721 } 722 xilinx_spips_update_cs_lines(s); 723 xilinx_spips_flush_txfifo(s); 724 fifo8_reset(&s->rx_fifo); 725 726 DB_PRINT_L(0, "starting QSPI data read\n"); 727 728 while (cache_entry < LQSPI_CACHE_SIZE) { 729 for (i = 0; i < 64; ++i) { 730 tx_data_bytes(&s->tx_fifo, 0, 1, false); 731 } 732 xilinx_spips_flush_txfifo(s); 733 for (i = 0; i < 64; ++i) { 734 rx_data_bytes(&s->rx_fifo, &q->lqspi_buf[cache_entry++], 1); 735 } 736 } 737 738 s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 739 s->regs[R_LQSPI_STS] |= u_page_save; 740 xilinx_spips_update_cs_lines(s); 741 742 q->lqspi_cached_addr = flash_addr * num_effective_busses(s); 743 } 744 } 745 746 static void *lqspi_request_mmio_ptr(void *opaque, hwaddr addr, unsigned *size, 747 unsigned *offset) 748 { 749 XilinxQSPIPS *q = opaque; 750 hwaddr offset_within_the_region; 751 752 if (!q->mmio_execution_enabled) { 753 return NULL; 754 } 755 756 offset_within_the_region = addr & ~(LQSPI_CACHE_SIZE - 1); 757 lqspi_load_cache(opaque, offset_within_the_region); 758 *size = LQSPI_CACHE_SIZE; 759 *offset = offset_within_the_region; 760 return q->lqspi_buf; 761 } 762 763 static uint64_t 764 lqspi_read(void *opaque, hwaddr addr, unsigned int size) 765 { 766 XilinxQSPIPS *q = opaque; 767 uint32_t ret; 768 769 if (addr >= q->lqspi_cached_addr && 770 addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { 771 uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr]; 772 ret = cpu_to_le32(*(uint32_t *)retp); 773 DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr, 774 (unsigned)ret); 775 return ret; 776 } else { 777 lqspi_load_cache(opaque, addr); 778 return lqspi_read(opaque, addr, size); 779 } 780 } 781 782 static const MemoryRegionOps lqspi_ops = { 783 .read = lqspi_read, 784 .request_ptr = lqspi_request_mmio_ptr, 785 .endianness = DEVICE_NATIVE_ENDIAN, 786 .valid = { 787 .min_access_size = 1, 788 .max_access_size = 4 789 } 790 }; 791 792 static void xilinx_spips_realize(DeviceState *dev, Error **errp) 793 { 794 XilinxSPIPS *s = XILINX_SPIPS(dev); 795 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 796 XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s); 797 qemu_irq *cs; 798 int i; 799 800 DB_PRINT_L(0, "realized spips\n"); 801 802 s->spi = g_new(SSIBus *, s->num_busses); 803 for (i = 0; i < s->num_busses; ++i) { 804 char bus_name[16]; 805 snprintf(bus_name, 16, "spi%d", i); 806 s->spi[i] = ssi_create_bus(dev, bus_name); 807 } 808 809 s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses); 810 s->cs_lines_state = g_new0(bool, s->num_cs * s->num_busses); 811 for (i = 0, cs = s->cs_lines; i < s->num_busses; ++i, cs += s->num_cs) { 812 ssi_auto_connect_slaves(DEVICE(s), cs, s->spi[i]); 813 } 814 815 sysbus_init_irq(sbd, &s->irq); 816 for (i = 0; i < s->num_cs * s->num_busses; ++i) { 817 sysbus_init_irq(sbd, &s->cs_lines[i]); 818 } 819 820 memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s, 821 "spi", XLNX_SPIPS_R_MAX * 4); 822 sysbus_init_mmio(sbd, &s->iomem); 823 824 s->irqline = -1; 825 826 fifo8_create(&s->rx_fifo, xsc->rx_fifo_size); 827 fifo8_create(&s->tx_fifo, xsc->tx_fifo_size); 828 } 829 830 static void xilinx_qspips_realize(DeviceState *dev, Error **errp) 831 { 832 XilinxSPIPS *s = XILINX_SPIPS(dev); 833 XilinxQSPIPS *q = XILINX_QSPIPS(dev); 834 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 835 836 DB_PRINT_L(0, "realized qspips\n"); 837 838 s->num_busses = 2; 839 s->num_cs = 2; 840 s->num_txrx_bytes = 4; 841 842 xilinx_spips_realize(dev, errp); 843 memory_region_init_io(&s->mmlqspi, OBJECT(s), &lqspi_ops, s, "lqspi", 844 (1 << LQSPI_ADDRESS_BITS) * 2); 845 sysbus_init_mmio(sbd, &s->mmlqspi); 846 847 q->lqspi_cached_addr = ~0ULL; 848 849 /* mmio_execution breaks migration better aborting than having strange 850 * bugs. 851 */ 852 if (q->mmio_execution_enabled) { 853 error_setg(&q->migration_blocker, 854 "enabling mmio_execution breaks migration"); 855 migrate_add_blocker(q->migration_blocker, &error_fatal); 856 } 857 } 858 859 static int xilinx_spips_post_load(void *opaque, int version_id) 860 { 861 xilinx_spips_update_ixr((XilinxSPIPS *)opaque); 862 xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque); 863 return 0; 864 } 865 866 static const VMStateDescription vmstate_xilinx_spips = { 867 .name = "xilinx_spips", 868 .version_id = 2, 869 .minimum_version_id = 2, 870 .post_load = xilinx_spips_post_load, 871 .fields = (VMStateField[]) { 872 VMSTATE_FIFO8(tx_fifo, XilinxSPIPS), 873 VMSTATE_FIFO8(rx_fifo, XilinxSPIPS), 874 VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, XLNX_SPIPS_R_MAX), 875 VMSTATE_UINT8(snoop_state, XilinxSPIPS), 876 VMSTATE_END_OF_LIST() 877 } 878 }; 879 880 static Property xilinx_qspips_properties[] = { 881 /* We had to turn this off for 2.10 as it is not compatible with migration. 882 * It can be enabled but will prevent the device to be migrated. 883 * This will go aways when a fix will be released. 884 */ 885 DEFINE_PROP_BOOL("x-mmio-exec", XilinxQSPIPS, mmio_execution_enabled, 886 false), 887 DEFINE_PROP_END_OF_LIST(), 888 }; 889 890 static Property xilinx_spips_properties[] = { 891 DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1), 892 DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4), 893 DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1), 894 DEFINE_PROP_END_OF_LIST(), 895 }; 896 897 static void xilinx_qspips_class_init(ObjectClass *klass, void * data) 898 { 899 DeviceClass *dc = DEVICE_CLASS(klass); 900 XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 901 902 dc->realize = xilinx_qspips_realize; 903 dc->props = xilinx_qspips_properties; 904 xsc->reg_ops = &qspips_ops; 905 xsc->rx_fifo_size = RXFF_A_Q; 906 xsc->tx_fifo_size = TXFF_A_Q; 907 } 908 909 static void xilinx_spips_class_init(ObjectClass *klass, void *data) 910 { 911 DeviceClass *dc = DEVICE_CLASS(klass); 912 XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 913 914 dc->realize = xilinx_spips_realize; 915 dc->reset = xilinx_spips_reset; 916 dc->props = xilinx_spips_properties; 917 dc->vmsd = &vmstate_xilinx_spips; 918 919 xsc->reg_ops = &spips_ops; 920 xsc->rx_fifo_size = RXFF_A; 921 xsc->tx_fifo_size = TXFF_A; 922 } 923 924 static const TypeInfo xilinx_spips_info = { 925 .name = TYPE_XILINX_SPIPS, 926 .parent = TYPE_SYS_BUS_DEVICE, 927 .instance_size = sizeof(XilinxSPIPS), 928 .class_init = xilinx_spips_class_init, 929 .class_size = sizeof(XilinxSPIPSClass), 930 }; 931 932 static const TypeInfo xilinx_qspips_info = { 933 .name = TYPE_XILINX_QSPIPS, 934 .parent = TYPE_XILINX_SPIPS, 935 .instance_size = sizeof(XilinxQSPIPS), 936 .class_init = xilinx_qspips_class_init, 937 }; 938 939 static void xilinx_spips_register_types(void) 940 { 941 type_register_static(&xilinx_spips_info); 942 type_register_static(&xilinx_qspips_info); 943 } 944 945 type_init(xilinx_spips_register_types) 946