1 /* 2 * QEMU model of the Xilinx Zynq SPI controller 3 * 4 * Copyright (c) 2012 Peter A. G. Crosthwaite 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/sysbus.h" 27 #include "sysemu/sysemu.h" 28 #include "hw/ptimer.h" 29 #include "qemu/log.h" 30 #include "qemu/bitops.h" 31 #include "hw/ssi/xilinx_spips.h" 32 #include "qapi/error.h" 33 #include "hw/register.h" 34 #include "migration/blocker.h" 35 36 #ifndef XILINX_SPIPS_ERR_DEBUG 37 #define XILINX_SPIPS_ERR_DEBUG 0 38 #endif 39 40 #define DB_PRINT_L(level, ...) do { \ 41 if (XILINX_SPIPS_ERR_DEBUG > (level)) { \ 42 fprintf(stderr, ": %s: ", __func__); \ 43 fprintf(stderr, ## __VA_ARGS__); \ 44 } \ 45 } while (0); 46 47 /* config register */ 48 #define R_CONFIG (0x00 / 4) 49 #define IFMODE (1U << 31) 50 #define R_CONFIG_ENDIAN (1 << 26) 51 #define MODEFAIL_GEN_EN (1 << 17) 52 #define MAN_START_COM (1 << 16) 53 #define MAN_START_EN (1 << 15) 54 #define MANUAL_CS (1 << 14) 55 #define CS (0xF << 10) 56 #define CS_SHIFT (10) 57 #define PERI_SEL (1 << 9) 58 #define REF_CLK (1 << 8) 59 #define FIFO_WIDTH (3 << 6) 60 #define BAUD_RATE_DIV (7 << 3) 61 #define CLK_PH (1 << 2) 62 #define CLK_POL (1 << 1) 63 #define MODE_SEL (1 << 0) 64 #define R_CONFIG_RSVD (0x7bf40000) 65 66 /* interrupt mechanism */ 67 #define R_INTR_STATUS (0x04 / 4) 68 #define R_INTR_EN (0x08 / 4) 69 #define R_INTR_DIS (0x0C / 4) 70 #define R_INTR_MASK (0x10 / 4) 71 #define IXR_TX_FIFO_UNDERFLOW (1 << 6) 72 #define IXR_RX_FIFO_FULL (1 << 5) 73 #define IXR_RX_FIFO_NOT_EMPTY (1 << 4) 74 #define IXR_TX_FIFO_FULL (1 << 3) 75 #define IXR_TX_FIFO_NOT_FULL (1 << 2) 76 #define IXR_TX_FIFO_MODE_FAIL (1 << 1) 77 #define IXR_RX_FIFO_OVERFLOW (1 << 0) 78 #define IXR_ALL ((IXR_TX_FIFO_UNDERFLOW<<1)-1) 79 80 #define R_EN (0x14 / 4) 81 #define R_DELAY (0x18 / 4) 82 #define R_TX_DATA (0x1C / 4) 83 #define R_RX_DATA (0x20 / 4) 84 #define R_SLAVE_IDLE_COUNT (0x24 / 4) 85 #define R_TX_THRES (0x28 / 4) 86 #define R_RX_THRES (0x2C / 4) 87 #define R_TXD1 (0x80 / 4) 88 #define R_TXD2 (0x84 / 4) 89 #define R_TXD3 (0x88 / 4) 90 91 #define R_LQSPI_CFG (0xa0 / 4) 92 #define R_LQSPI_CFG_RESET 0x03A002EB 93 #define LQSPI_CFG_LQ_MODE (1U << 31) 94 #define LQSPI_CFG_TWO_MEM (1 << 30) 95 #define LQSPI_CFG_SEP_BUS (1 << 30) 96 #define LQSPI_CFG_U_PAGE (1 << 28) 97 #define LQSPI_CFG_MODE_EN (1 << 25) 98 #define LQSPI_CFG_MODE_WIDTH 8 99 #define LQSPI_CFG_MODE_SHIFT 16 100 #define LQSPI_CFG_DUMMY_WIDTH 3 101 #define LQSPI_CFG_DUMMY_SHIFT 8 102 #define LQSPI_CFG_INST_CODE 0xFF 103 104 #define R_CMND (0xc0 / 4) 105 #define R_CMND_RXFIFO_DRAIN (1 << 19) 106 FIELD(CMND, PARTIAL_BYTE_LEN, 16, 3) 107 #define R_CMND_EXT_ADD (1 << 15) 108 FIELD(CMND, RX_DISCARD, 8, 7) 109 FIELD(CMND, DUMMY_CYCLES, 2, 6) 110 #define R_CMND_DMA_EN (1 << 1) 111 #define R_CMND_PUSH_WAIT (1 << 0) 112 #define R_TRANSFER_SIZE (0xc4 / 4) 113 #define R_LQSPI_STS (0xA4 / 4) 114 #define LQSPI_STS_WR_RECVD (1 << 1) 115 116 #define R_MOD_ID (0xFC / 4) 117 118 /* size of TXRX FIFOs */ 119 #define RXFF_A 32 120 #define TXFF_A 32 121 122 #define RXFF_A_Q (64 * 4) 123 #define TXFF_A_Q (64 * 4) 124 125 /* 16MB per linear region */ 126 #define LQSPI_ADDRESS_BITS 24 127 128 #define SNOOP_CHECKING 0xFF 129 #define SNOOP_ADDR 0xF0 130 #define SNOOP_NONE 0xEE 131 #define SNOOP_STRIPING 0 132 133 static inline int num_effective_busses(XilinxSPIPS *s) 134 { 135 return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && 136 s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1; 137 } 138 139 static inline bool xilinx_spips_cs_is_set(XilinxSPIPS *s, int i, int field) 140 { 141 return ~field & (1 << i) && (s->regs[R_CONFIG] & MANUAL_CS 142 || !fifo8_is_empty(&s->tx_fifo)); 143 } 144 145 static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) 146 { 147 int i, j; 148 bool found = false; 149 int field = s->regs[R_CONFIG] >> CS_SHIFT; 150 151 for (i = 0; i < s->num_cs; i++) { 152 for (j = 0; j < num_effective_busses(s); j++) { 153 int upage = !!(s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE); 154 int cs_to_set = (j * s->num_cs + i + upage) % 155 (s->num_cs * s->num_busses); 156 157 if (xilinx_spips_cs_is_set(s, i, field) && !found) { 158 DB_PRINT_L(0, "selecting slave %d\n", i); 159 qemu_set_irq(s->cs_lines[cs_to_set], 0); 160 if (s->cs_lines_state[cs_to_set]) { 161 s->cs_lines_state[cs_to_set] = false; 162 s->rx_discard = ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD); 163 } 164 } else { 165 DB_PRINT_L(0, "deselecting slave %d\n", i); 166 qemu_set_irq(s->cs_lines[cs_to_set], 1); 167 s->cs_lines_state[cs_to_set] = true; 168 } 169 } 170 if (xilinx_spips_cs_is_set(s, i, field)) { 171 found = true; 172 } 173 } 174 if (!found) { 175 s->snoop_state = SNOOP_CHECKING; 176 s->cmd_dummies = 0; 177 s->link_state = 1; 178 s->link_state_next = 1; 179 s->link_state_next_when = 0; 180 DB_PRINT_L(1, "moving to snoop check state\n"); 181 } 182 } 183 184 static void xilinx_spips_update_ixr(XilinxSPIPS *s) 185 { 186 if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE) { 187 return; 188 } 189 /* These are set/cleared as they occur */ 190 s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW | 191 IXR_TX_FIFO_MODE_FAIL); 192 /* these are pure functions of fifo state, set them here */ 193 s->regs[R_INTR_STATUS] |= 194 (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) | 195 (s->rx_fifo.num >= s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY : 0) | 196 (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | 197 (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0); 198 /* drive external interrupt pin */ 199 int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] & 200 IXR_ALL); 201 if (new_irqline != s->irqline) { 202 s->irqline = new_irqline; 203 qemu_set_irq(s->irq, s->irqline); 204 } 205 } 206 207 static void xilinx_spips_reset(DeviceState *d) 208 { 209 XilinxSPIPS *s = XILINX_SPIPS(d); 210 211 int i; 212 for (i = 0; i < XLNX_SPIPS_R_MAX; i++) { 213 s->regs[i] = 0; 214 } 215 216 fifo8_reset(&s->rx_fifo); 217 fifo8_reset(&s->rx_fifo); 218 /* non zero resets */ 219 s->regs[R_CONFIG] |= MODEFAIL_GEN_EN; 220 s->regs[R_SLAVE_IDLE_COUNT] = 0xFF; 221 s->regs[R_TX_THRES] = 1; 222 s->regs[R_RX_THRES] = 1; 223 /* FIXME: move magic number definition somewhere sensible */ 224 s->regs[R_MOD_ID] = 0x01090106; 225 s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET; 226 s->link_state = 1; 227 s->link_state_next = 1; 228 s->link_state_next_when = 0; 229 s->snoop_state = SNOOP_CHECKING; 230 s->cmd_dummies = 0; 231 s->man_start_com = false; 232 xilinx_spips_update_ixr(s); 233 xilinx_spips_update_cs_lines(s); 234 } 235 236 /* N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) 237 * column wise (from element 0 to N-1). num is the length of x, and dir 238 * reverses the direction of the transform. Best illustrated by example: 239 * Each digit in the below array is a single bit (num == 3): 240 * 241 * {{ 76543210, } ----- stripe (dir == false) -----> {{ 741gdaFC, } 242 * { hgfedcba, } { 630fcHEB, } 243 * { HGFEDCBA, }} <---- upstripe (dir == true) ----- { 52hebGDA, }} 244 */ 245 246 static inline void stripe8(uint8_t *x, int num, bool dir) 247 { 248 uint8_t r[num]; 249 memset(r, 0, sizeof(uint8_t) * num); 250 int idx[2] = {0, 0}; 251 int bit[2] = {0, 7}; 252 int d = dir; 253 254 for (idx[0] = 0; idx[0] < num; ++idx[0]) { 255 for (bit[0] = 7; bit[0] >= 0; bit[0]--) { 256 r[idx[!d]] |= x[idx[d]] & 1 << bit[d] ? 1 << bit[!d] : 0; 257 idx[1] = (idx[1] + 1) % num; 258 if (!idx[1]) { 259 bit[1]--; 260 } 261 } 262 } 263 memcpy(x, r, sizeof(uint8_t) * num); 264 } 265 266 static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command) 267 { 268 if (!qs) { 269 /* The SPI device is not a QSPI device */ 270 return -1; 271 } 272 273 switch (command) { /* check for dummies */ 274 case READ: /* no dummy bytes/cycles */ 275 case PP: 276 case DPP: 277 case QPP: 278 case READ_4: 279 case PP_4: 280 case QPP_4: 281 return 0; 282 case FAST_READ: 283 case DOR: 284 case QOR: 285 case DOR_4: 286 case QOR_4: 287 return 1; 288 case DIOR: 289 case FAST_READ_4: 290 case DIOR_4: 291 return 2; 292 case QIOR: 293 case QIOR_4: 294 return 5; 295 default: 296 return -1; 297 } 298 } 299 300 static inline uint8_t get_addr_length(XilinxSPIPS *s, uint8_t cmd) 301 { 302 switch (cmd) { 303 case PP_4: 304 case QPP_4: 305 case READ_4: 306 case QIOR_4: 307 case FAST_READ_4: 308 case DOR_4: 309 case QOR_4: 310 case DIOR_4: 311 return 4; 312 default: 313 return (s->regs[R_CMND] & R_CMND_EXT_ADD) ? 4 : 3; 314 } 315 } 316 317 static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) 318 { 319 int debug_level = 0; 320 XilinxQSPIPS *q = (XilinxQSPIPS *) object_dynamic_cast(OBJECT(s), 321 TYPE_XILINX_QSPIPS); 322 323 for (;;) { 324 int i; 325 uint8_t tx = 0; 326 uint8_t tx_rx[num_effective_busses(s)]; 327 uint8_t dummy_cycles = 0; 328 uint8_t addr_length; 329 330 if (fifo8_is_empty(&s->tx_fifo)) { 331 if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { 332 s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW; 333 } 334 xilinx_spips_update_ixr(s); 335 return; 336 } else if (s->snoop_state == SNOOP_STRIPING) { 337 for (i = 0; i < num_effective_busses(s); ++i) { 338 tx_rx[i] = fifo8_pop(&s->tx_fifo); 339 } 340 stripe8(tx_rx, num_effective_busses(s), false); 341 } else if (s->snoop_state >= SNOOP_ADDR) { 342 tx = fifo8_pop(&s->tx_fifo); 343 for (i = 0; i < num_effective_busses(s); ++i) { 344 tx_rx[i] = tx; 345 } 346 } else { 347 /* Extract a dummy byte and generate dummy cycles according to the 348 * link state */ 349 tx = fifo8_pop(&s->tx_fifo); 350 dummy_cycles = 8 / s->link_state; 351 } 352 353 for (i = 0; i < num_effective_busses(s); ++i) { 354 int bus = num_effective_busses(s) - 1 - i; 355 if (dummy_cycles) { 356 int d; 357 for (d = 0; d < dummy_cycles; ++d) { 358 tx_rx[0] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[0]); 359 } 360 } else { 361 DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]); 362 tx_rx[i] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]); 363 DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]); 364 } 365 } 366 367 if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { 368 DB_PRINT_L(debug_level, "dircarding drained rx byte\n"); 369 /* Do nothing */ 370 } else if (s->rx_discard) { 371 DB_PRINT_L(debug_level, "dircarding discarded rx byte\n"); 372 s->rx_discard -= 8 / s->link_state; 373 } else if (fifo8_is_full(&s->rx_fifo)) { 374 s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW; 375 DB_PRINT_L(0, "rx FIFO overflow"); 376 } else if (s->snoop_state == SNOOP_STRIPING) { 377 stripe8(tx_rx, num_effective_busses(s), true); 378 for (i = 0; i < num_effective_busses(s); ++i) { 379 fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]); 380 DB_PRINT_L(debug_level, "pushing striped rx byte\n"); 381 } 382 } else { 383 DB_PRINT_L(debug_level, "pushing unstriped rx byte\n"); 384 fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]); 385 } 386 387 if (s->link_state_next_when) { 388 s->link_state_next_when--; 389 if (!s->link_state_next_when) { 390 s->link_state = s->link_state_next; 391 } 392 } 393 394 DB_PRINT_L(debug_level, "initial snoop state: %x\n", 395 (unsigned)s->snoop_state); 396 switch (s->snoop_state) { 397 case (SNOOP_CHECKING): 398 /* Store the count of dummy bytes in the txfifo */ 399 s->cmd_dummies = xilinx_spips_num_dummies(q, tx); 400 addr_length = get_addr_length(s, tx); 401 if (s->cmd_dummies < 0) { 402 s->snoop_state = SNOOP_NONE; 403 } else { 404 s->snoop_state = SNOOP_ADDR + addr_length - 1; 405 } 406 switch (tx) { 407 case DPP: 408 case DOR: 409 case DOR_4: 410 s->link_state_next = 2; 411 s->link_state_next_when = addr_length + s->cmd_dummies; 412 break; 413 case QPP: 414 case QPP_4: 415 case QOR: 416 case QOR_4: 417 s->link_state_next = 4; 418 s->link_state_next_when = addr_length + s->cmd_dummies; 419 break; 420 case DIOR: 421 case DIOR_4: 422 s->link_state = 2; 423 break; 424 case QIOR: 425 case QIOR_4: 426 s->link_state = 4; 427 break; 428 } 429 break; 430 case (SNOOP_ADDR): 431 /* Address has been transmitted, transmit dummy cycles now if 432 * needed */ 433 if (s->cmd_dummies < 0) { 434 s->snoop_state = SNOOP_NONE; 435 } else { 436 s->snoop_state = s->cmd_dummies; 437 } 438 break; 439 case (SNOOP_STRIPING): 440 case (SNOOP_NONE): 441 /* Once we hit the boring stuff - squelch debug noise */ 442 if (!debug_level) { 443 DB_PRINT_L(0, "squelching debug info ....\n"); 444 debug_level = 1; 445 } 446 break; 447 default: 448 s->snoop_state--; 449 } 450 DB_PRINT_L(debug_level, "final snoop state: %x\n", 451 (unsigned)s->snoop_state); 452 } 453 } 454 455 static inline void tx_data_bytes(Fifo8 *fifo, uint32_t value, int num, bool be) 456 { 457 int i; 458 for (i = 0; i < num && !fifo8_is_full(fifo); ++i) { 459 if (be) { 460 fifo8_push(fifo, (uint8_t)(value >> 24)); 461 value <<= 8; 462 } else { 463 fifo8_push(fifo, (uint8_t)value); 464 value >>= 8; 465 } 466 } 467 } 468 469 static void xilinx_spips_check_zero_pump(XilinxSPIPS *s) 470 { 471 if (!s->regs[R_TRANSFER_SIZE]) { 472 return; 473 } 474 if (!fifo8_is_empty(&s->tx_fifo) && s->regs[R_CMND] & R_CMND_PUSH_WAIT) { 475 return; 476 } 477 /* 478 * The zero pump must never fill tx fifo such that rx overflow is 479 * possible 480 */ 481 while (s->regs[R_TRANSFER_SIZE] && 482 s->rx_fifo.num + s->tx_fifo.num < RXFF_A_Q - 3) { 483 /* endianess just doesn't matter when zero pumping */ 484 tx_data_bytes(&s->tx_fifo, 0, 4, false); 485 s->regs[R_TRANSFER_SIZE] &= ~0x03ull; 486 s->regs[R_TRANSFER_SIZE] -= 4; 487 } 488 } 489 490 static void xilinx_spips_check_flush(XilinxSPIPS *s) 491 { 492 if (s->man_start_com || 493 (!fifo8_is_empty(&s->tx_fifo) && 494 !(s->regs[R_CONFIG] & MAN_START_EN))) { 495 xilinx_spips_check_zero_pump(s); 496 xilinx_spips_flush_txfifo(s); 497 } 498 if (fifo8_is_empty(&s->tx_fifo) && !s->regs[R_TRANSFER_SIZE]) { 499 s->man_start_com = false; 500 } 501 xilinx_spips_update_ixr(s); 502 } 503 504 static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max) 505 { 506 int i; 507 508 for (i = 0; i < max && !fifo8_is_empty(fifo); ++i) { 509 value[i] = fifo8_pop(fifo); 510 } 511 return max - i; 512 } 513 514 static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, 515 unsigned size) 516 { 517 XilinxSPIPS *s = opaque; 518 uint32_t mask = ~0; 519 uint32_t ret; 520 uint8_t rx_buf[4]; 521 int shortfall; 522 523 addr >>= 2; 524 switch (addr) { 525 case R_CONFIG: 526 mask = ~(R_CONFIG_RSVD | MAN_START_COM); 527 break; 528 case R_INTR_STATUS: 529 ret = s->regs[addr] & IXR_ALL; 530 s->regs[addr] = 0; 531 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 532 return ret; 533 case R_INTR_MASK: 534 mask = IXR_ALL; 535 break; 536 case R_EN: 537 mask = 0x1; 538 break; 539 case R_SLAVE_IDLE_COUNT: 540 mask = 0xFF; 541 break; 542 case R_MOD_ID: 543 mask = 0x01FFFFFF; 544 break; 545 case R_INTR_EN: 546 case R_INTR_DIS: 547 case R_TX_DATA: 548 mask = 0; 549 break; 550 case R_RX_DATA: 551 memset(rx_buf, 0, sizeof(rx_buf)); 552 shortfall = rx_data_bytes(&s->rx_fifo, rx_buf, s->num_txrx_bytes); 553 ret = s->regs[R_CONFIG] & R_CONFIG_ENDIAN ? 554 cpu_to_be32(*(uint32_t *)rx_buf) : 555 cpu_to_le32(*(uint32_t *)rx_buf); 556 if (!(s->regs[R_CONFIG] & R_CONFIG_ENDIAN)) { 557 ret <<= 8 * shortfall; 558 } 559 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); 560 xilinx_spips_update_ixr(s); 561 return ret; 562 } 563 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, 564 s->regs[addr] & mask); 565 return s->regs[addr] & mask; 566 567 } 568 569 static void xilinx_spips_write(void *opaque, hwaddr addr, 570 uint64_t value, unsigned size) 571 { 572 int mask = ~0; 573 XilinxSPIPS *s = opaque; 574 575 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value); 576 addr >>= 2; 577 switch (addr) { 578 case R_CONFIG: 579 mask = ~(R_CONFIG_RSVD | MAN_START_COM); 580 if ((value & MAN_START_COM) && (s->regs[R_CONFIG] & MAN_START_EN)) { 581 s->man_start_com = true; 582 } 583 break; 584 case R_INTR_STATUS: 585 mask = IXR_ALL; 586 s->regs[R_INTR_STATUS] &= ~(mask & value); 587 goto no_reg_update; 588 case R_INTR_DIS: 589 mask = IXR_ALL; 590 s->regs[R_INTR_MASK] &= ~(mask & value); 591 goto no_reg_update; 592 case R_INTR_EN: 593 mask = IXR_ALL; 594 s->regs[R_INTR_MASK] |= mask & value; 595 goto no_reg_update; 596 case R_EN: 597 mask = 0x1; 598 break; 599 case R_SLAVE_IDLE_COUNT: 600 mask = 0xFF; 601 break; 602 case R_RX_DATA: 603 case R_INTR_MASK: 604 case R_MOD_ID: 605 mask = 0; 606 break; 607 case R_TX_DATA: 608 tx_data_bytes(&s->tx_fifo, (uint32_t)value, s->num_txrx_bytes, 609 s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 610 goto no_reg_update; 611 case R_TXD1: 612 tx_data_bytes(&s->tx_fifo, (uint32_t)value, 1, 613 s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 614 goto no_reg_update; 615 case R_TXD2: 616 tx_data_bytes(&s->tx_fifo, (uint32_t)value, 2, 617 s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 618 goto no_reg_update; 619 case R_TXD3: 620 tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3, 621 s->regs[R_CONFIG] & R_CONFIG_ENDIAN); 622 goto no_reg_update; 623 } 624 s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); 625 no_reg_update: 626 xilinx_spips_update_cs_lines(s); 627 xilinx_spips_check_flush(s); 628 xilinx_spips_update_cs_lines(s); 629 xilinx_spips_update_ixr(s); 630 } 631 632 static const MemoryRegionOps spips_ops = { 633 .read = xilinx_spips_read, 634 .write = xilinx_spips_write, 635 .endianness = DEVICE_LITTLE_ENDIAN, 636 }; 637 638 static void xilinx_qspips_invalidate_mmio_ptr(XilinxQSPIPS *q) 639 { 640 XilinxSPIPS *s = &q->parent_obj; 641 642 if ((q->mmio_execution_enabled) && (q->lqspi_cached_addr != ~0ULL)) { 643 /* Invalidate the current mapped mmio */ 644 memory_region_invalidate_mmio_ptr(&s->mmlqspi, q->lqspi_cached_addr, 645 LQSPI_CACHE_SIZE); 646 } 647 648 q->lqspi_cached_addr = ~0ULL; 649 } 650 651 static void xilinx_qspips_write(void *opaque, hwaddr addr, 652 uint64_t value, unsigned size) 653 { 654 XilinxQSPIPS *q = XILINX_QSPIPS(opaque); 655 XilinxSPIPS *s = XILINX_SPIPS(opaque); 656 657 xilinx_spips_write(opaque, addr, value, size); 658 addr >>= 2; 659 660 if (addr == R_LQSPI_CFG) { 661 xilinx_qspips_invalidate_mmio_ptr(q); 662 } 663 if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { 664 fifo8_reset(&s->rx_fifo); 665 } 666 } 667 668 static const MemoryRegionOps qspips_ops = { 669 .read = xilinx_spips_read, 670 .write = xilinx_qspips_write, 671 .endianness = DEVICE_LITTLE_ENDIAN, 672 }; 673 674 #define LQSPI_CACHE_SIZE 1024 675 676 static void lqspi_load_cache(void *opaque, hwaddr addr) 677 { 678 XilinxQSPIPS *q = opaque; 679 XilinxSPIPS *s = opaque; 680 int i; 681 int flash_addr = ((addr & ~(LQSPI_CACHE_SIZE - 1)) 682 / num_effective_busses(s)); 683 int slave = flash_addr >> LQSPI_ADDRESS_BITS; 684 int cache_entry = 0; 685 uint32_t u_page_save = s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE; 686 687 if (addr < q->lqspi_cached_addr || 688 addr > q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { 689 xilinx_qspips_invalidate_mmio_ptr(q); 690 s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 691 s->regs[R_LQSPI_STS] |= slave ? LQSPI_CFG_U_PAGE : 0; 692 693 DB_PRINT_L(0, "config reg status: %08x\n", s->regs[R_LQSPI_CFG]); 694 695 fifo8_reset(&s->tx_fifo); 696 fifo8_reset(&s->rx_fifo); 697 698 /* instruction */ 699 DB_PRINT_L(0, "pushing read instruction: %02x\n", 700 (unsigned)(uint8_t)(s->regs[R_LQSPI_CFG] & 701 LQSPI_CFG_INST_CODE)); 702 fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE); 703 /* read address */ 704 DB_PRINT_L(0, "pushing read address %06x\n", flash_addr); 705 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16)); 706 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8)); 707 fifo8_push(&s->tx_fifo, (uint8_t)flash_addr); 708 /* mode bits */ 709 if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) { 710 fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG], 711 LQSPI_CFG_MODE_SHIFT, 712 LQSPI_CFG_MODE_WIDTH)); 713 } 714 /* dummy bytes */ 715 for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT, 716 LQSPI_CFG_DUMMY_WIDTH)); ++i) { 717 DB_PRINT_L(0, "pushing dummy byte\n"); 718 fifo8_push(&s->tx_fifo, 0); 719 } 720 xilinx_spips_update_cs_lines(s); 721 xilinx_spips_flush_txfifo(s); 722 fifo8_reset(&s->rx_fifo); 723 724 DB_PRINT_L(0, "starting QSPI data read\n"); 725 726 while (cache_entry < LQSPI_CACHE_SIZE) { 727 for (i = 0; i < 64; ++i) { 728 tx_data_bytes(&s->tx_fifo, 0, 1, false); 729 } 730 xilinx_spips_flush_txfifo(s); 731 for (i = 0; i < 64; ++i) { 732 rx_data_bytes(&s->rx_fifo, &q->lqspi_buf[cache_entry++], 1); 733 } 734 } 735 736 s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE; 737 s->regs[R_LQSPI_STS] |= u_page_save; 738 xilinx_spips_update_cs_lines(s); 739 740 q->lqspi_cached_addr = flash_addr * num_effective_busses(s); 741 } 742 } 743 744 static void *lqspi_request_mmio_ptr(void *opaque, hwaddr addr, unsigned *size, 745 unsigned *offset) 746 { 747 XilinxQSPIPS *q = opaque; 748 hwaddr offset_within_the_region; 749 750 if (!q->mmio_execution_enabled) { 751 return NULL; 752 } 753 754 offset_within_the_region = addr & ~(LQSPI_CACHE_SIZE - 1); 755 lqspi_load_cache(opaque, offset_within_the_region); 756 *size = LQSPI_CACHE_SIZE; 757 *offset = offset_within_the_region; 758 return q->lqspi_buf; 759 } 760 761 static uint64_t 762 lqspi_read(void *opaque, hwaddr addr, unsigned int size) 763 { 764 XilinxQSPIPS *q = opaque; 765 uint32_t ret; 766 767 if (addr >= q->lqspi_cached_addr && 768 addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) { 769 uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr]; 770 ret = cpu_to_le32(*(uint32_t *)retp); 771 DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr, 772 (unsigned)ret); 773 return ret; 774 } else { 775 lqspi_load_cache(opaque, addr); 776 return lqspi_read(opaque, addr, size); 777 } 778 } 779 780 static const MemoryRegionOps lqspi_ops = { 781 .read = lqspi_read, 782 .request_ptr = lqspi_request_mmio_ptr, 783 .endianness = DEVICE_NATIVE_ENDIAN, 784 .valid = { 785 .min_access_size = 1, 786 .max_access_size = 4 787 } 788 }; 789 790 static void xilinx_spips_realize(DeviceState *dev, Error **errp) 791 { 792 XilinxSPIPS *s = XILINX_SPIPS(dev); 793 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 794 XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s); 795 qemu_irq *cs; 796 int i; 797 798 DB_PRINT_L(0, "realized spips\n"); 799 800 s->spi = g_new(SSIBus *, s->num_busses); 801 for (i = 0; i < s->num_busses; ++i) { 802 char bus_name[16]; 803 snprintf(bus_name, 16, "spi%d", i); 804 s->spi[i] = ssi_create_bus(dev, bus_name); 805 } 806 807 s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses); 808 s->cs_lines_state = g_new0(bool, s->num_cs * s->num_busses); 809 for (i = 0, cs = s->cs_lines; i < s->num_busses; ++i, cs += s->num_cs) { 810 ssi_auto_connect_slaves(DEVICE(s), cs, s->spi[i]); 811 } 812 813 sysbus_init_irq(sbd, &s->irq); 814 for (i = 0; i < s->num_cs * s->num_busses; ++i) { 815 sysbus_init_irq(sbd, &s->cs_lines[i]); 816 } 817 818 memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s, 819 "spi", XLNX_SPIPS_R_MAX * 4); 820 sysbus_init_mmio(sbd, &s->iomem); 821 822 s->irqline = -1; 823 824 fifo8_create(&s->rx_fifo, xsc->rx_fifo_size); 825 fifo8_create(&s->tx_fifo, xsc->tx_fifo_size); 826 } 827 828 static void xilinx_qspips_realize(DeviceState *dev, Error **errp) 829 { 830 XilinxSPIPS *s = XILINX_SPIPS(dev); 831 XilinxQSPIPS *q = XILINX_QSPIPS(dev); 832 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 833 834 DB_PRINT_L(0, "realized qspips\n"); 835 836 s->num_busses = 2; 837 s->num_cs = 2; 838 s->num_txrx_bytes = 4; 839 840 xilinx_spips_realize(dev, errp); 841 memory_region_init_io(&s->mmlqspi, OBJECT(s), &lqspi_ops, s, "lqspi", 842 (1 << LQSPI_ADDRESS_BITS) * 2); 843 sysbus_init_mmio(sbd, &s->mmlqspi); 844 845 q->lqspi_cached_addr = ~0ULL; 846 847 /* mmio_execution breaks migration better aborting than having strange 848 * bugs. 849 */ 850 if (q->mmio_execution_enabled) { 851 error_setg(&q->migration_blocker, 852 "enabling mmio_execution breaks migration"); 853 migrate_add_blocker(q->migration_blocker, &error_fatal); 854 } 855 } 856 857 static int xilinx_spips_post_load(void *opaque, int version_id) 858 { 859 xilinx_spips_update_ixr((XilinxSPIPS *)opaque); 860 xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque); 861 return 0; 862 } 863 864 static const VMStateDescription vmstate_xilinx_spips = { 865 .name = "xilinx_spips", 866 .version_id = 2, 867 .minimum_version_id = 2, 868 .post_load = xilinx_spips_post_load, 869 .fields = (VMStateField[]) { 870 VMSTATE_FIFO8(tx_fifo, XilinxSPIPS), 871 VMSTATE_FIFO8(rx_fifo, XilinxSPIPS), 872 VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, XLNX_SPIPS_R_MAX), 873 VMSTATE_UINT8(snoop_state, XilinxSPIPS), 874 VMSTATE_END_OF_LIST() 875 } 876 }; 877 878 static Property xilinx_qspips_properties[] = { 879 /* We had to turn this off for 2.10 as it is not compatible with migration. 880 * It can be enabled but will prevent the device to be migrated. 881 * This will go aways when a fix will be released. 882 */ 883 DEFINE_PROP_BOOL("x-mmio-exec", XilinxQSPIPS, mmio_execution_enabled, 884 false), 885 DEFINE_PROP_END_OF_LIST(), 886 }; 887 888 static Property xilinx_spips_properties[] = { 889 DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1), 890 DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4), 891 DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1), 892 DEFINE_PROP_END_OF_LIST(), 893 }; 894 895 static void xilinx_qspips_class_init(ObjectClass *klass, void * data) 896 { 897 DeviceClass *dc = DEVICE_CLASS(klass); 898 XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 899 900 dc->realize = xilinx_qspips_realize; 901 dc->props = xilinx_qspips_properties; 902 xsc->reg_ops = &qspips_ops; 903 xsc->rx_fifo_size = RXFF_A_Q; 904 xsc->tx_fifo_size = TXFF_A_Q; 905 } 906 907 static void xilinx_spips_class_init(ObjectClass *klass, void *data) 908 { 909 DeviceClass *dc = DEVICE_CLASS(klass); 910 XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); 911 912 dc->realize = xilinx_spips_realize; 913 dc->reset = xilinx_spips_reset; 914 dc->props = xilinx_spips_properties; 915 dc->vmsd = &vmstate_xilinx_spips; 916 917 xsc->reg_ops = &spips_ops; 918 xsc->rx_fifo_size = RXFF_A; 919 xsc->tx_fifo_size = TXFF_A; 920 } 921 922 static const TypeInfo xilinx_spips_info = { 923 .name = TYPE_XILINX_SPIPS, 924 .parent = TYPE_SYS_BUS_DEVICE, 925 .instance_size = sizeof(XilinxSPIPS), 926 .class_init = xilinx_spips_class_init, 927 .class_size = sizeof(XilinxSPIPSClass), 928 }; 929 930 static const TypeInfo xilinx_qspips_info = { 931 .name = TYPE_XILINX_QSPIPS, 932 .parent = TYPE_XILINX_SPIPS, 933 .instance_size = sizeof(XilinxQSPIPS), 934 .class_init = xilinx_qspips_class_init, 935 }; 936 937 static void xilinx_spips_register_types(void) 938 { 939 type_register_static(&xilinx_spips_info); 940 type_register_static(&xilinx_qspips_info); 941 } 942 943 type_init(xilinx_spips_register_types) 944