xref: /qemu/hw/ssi/xilinx_spi.c (revision 70ce076fa6dff60585c229a4b641b13e64bf03cf) 
1 /*
2  * QEMU model of the Xilinx SPI Controller
3  *
4  * Copyright (C) 2010 Edgar E. Iglesias.
5  * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
6  * Copyright (C) 2012 PetaLogix
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a copy
9  * of this software and associated documentation files (the "Software"), to deal
10  * in the Software without restriction, including without limitation the rights
11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12  * copies of the Software, and to permit persons to whom the Software is
13  * furnished to do so, subject to the following conditions:
14  *
15  * The above copyright notice and this permission notice shall be included in
16  * all copies or substantial portions of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24  * THE SOFTWARE.
25  */
26 
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "hw/sysbus.h"
30 #include "migration/vmstate.h"
31 #include "qemu/module.h"
32 #include "qemu/fifo8.h"
33 
34 #include "hw/irq.h"
35 #include "hw/qdev-properties.h"
36 #include "hw/qdev-properties-system.h"
37 #include "hw/ssi/ssi.h"
38 #include "qom/object.h"
39 
40 #ifdef XILINX_SPI_ERR_DEBUG
41 #define DB_PRINT(...) do { \
42     fprintf(stderr,  ": %s: ", __func__); \
43     fprintf(stderr, ## __VA_ARGS__); \
44     } while (0)
45 #else
46     #define DB_PRINT(...)
47 #endif
48 
49 #define R_DGIER     (0x1c / 4)
50 #define R_DGIER_IE  (1 << 31)
51 
52 #define R_IPISR     (0x20 / 4)
53 #define IRQ_DRR_NOT_EMPTY    (1 << (31 - 23))
54 #define IRQ_DRR_OVERRUN      (1 << (31 - 26))
55 #define IRQ_DRR_FULL         (1 << (31 - 27))
56 #define IRQ_TX_FF_HALF_EMPTY (1 << 6)
57 #define IRQ_DTR_UNDERRUN     (1 << 3)
58 #define IRQ_DTR_EMPTY        (1 << (31 - 29))
59 
60 #define R_IPIER     (0x28 / 4)
61 #define R_SRR       (0x40 / 4)
62 #define R_SPICR     (0x60 / 4)
63 #define R_SPICR_TXFF_RST     (1 << 5)
64 #define R_SPICR_RXFF_RST     (1 << 6)
65 #define R_SPICR_MTI          (1 << 8)
66 
67 #define R_SPISR     (0x64 / 4)
68 #define SR_TX_FULL    (1 << 3)
69 #define SR_TX_EMPTY   (1 << 2)
70 #define SR_RX_FULL    (1 << 1)
71 #define SR_RX_EMPTY   (1 << 0)
72 
73 #define R_SPIDTR    (0x68 / 4)
74 #define R_SPIDRR    (0x6C / 4)
75 #define R_SPISSR    (0x70 / 4)
76 #define R_TX_FF_OCY (0x74 / 4)
77 #define R_RX_FF_OCY (0x78 / 4)
78 #define R_MAX       (0x7C / 4)
79 
80 #define FIFO_CAPACITY 256
81 
82 #define TYPE_XILINX_SPI "xlnx.xps-spi"
83 OBJECT_DECLARE_SIMPLE_TYPE(XilinxSPI, XILINX_SPI)
84 
85 struct XilinxSPI {
86     SysBusDevice parent_obj;
87 
88     EndianMode model_endianness;
89     MemoryRegion mmio;
90 
91     qemu_irq irq;
92     int irqline;
93 
94     uint8_t num_cs;
95     qemu_irq *cs_lines;
96 
97     SSIBus *spi;
98 
99     Fifo8 rx_fifo;
100     Fifo8 tx_fifo;
101 
102     uint32_t regs[R_MAX];
103 };
104 
105 static void txfifo_reset(XilinxSPI *s)
106 {
107     fifo8_reset(&s->tx_fifo);
108 
109     s->regs[R_SPISR] &= ~SR_TX_FULL;
110     s->regs[R_SPISR] |= SR_TX_EMPTY;
111 }
112 
113 static void rxfifo_reset(XilinxSPI *s)
114 {
115     fifo8_reset(&s->rx_fifo);
116 
117     s->regs[R_SPISR] |= SR_RX_EMPTY;
118     s->regs[R_SPISR] &= ~SR_RX_FULL;
119 }
120 
121 static void xlx_spi_update_cs(XilinxSPI *s)
122 {
123     int i;
124 
125     for (i = 0; i < s->num_cs; ++i) {
126         qemu_set_irq(s->cs_lines[i], !(~s->regs[R_SPISSR] & 1 << i));
127     }
128 }
129 
130 static void xlx_spi_update_irq(XilinxSPI *s)
131 {
132     uint32_t pending;
133 
134     s->regs[R_IPISR] |=
135             (!fifo8_is_empty(&s->rx_fifo) ? IRQ_DRR_NOT_EMPTY : 0) |
136             (fifo8_is_full(&s->rx_fifo) ? IRQ_DRR_FULL : 0);
137 
138     pending = s->regs[R_IPISR] & s->regs[R_IPIER];
139 
140     pending = pending && (s->regs[R_DGIER] & R_DGIER_IE);
141     pending = !!pending;
142 
143     /* This call lies right in the data paths so don't call the
144        irq chain unless things really changed.  */
145     if (pending != s->irqline) {
146         s->irqline = pending;
147         DB_PRINT("irq_change of state %u ISR:%x IER:%X\n",
148                     pending, s->regs[R_IPISR], s->regs[R_IPIER]);
149         qemu_set_irq(s->irq, pending);
150     }
151 
152 }
153 
154 static void xlx_spi_do_reset(XilinxSPI *s)
155 {
156     memset(s->regs, 0, sizeof s->regs);
157 
158     rxfifo_reset(s);
159     txfifo_reset(s);
160 
161     s->regs[R_SPISSR] = ~0;
162     s->regs[R_SPICR] = R_SPICR_MTI;
163     xlx_spi_update_irq(s);
164     xlx_spi_update_cs(s);
165 }
166 
167 static void xlx_spi_reset(DeviceState *d)
168 {
169     xlx_spi_do_reset(XILINX_SPI(d));
170 }
171 
172 static inline int spi_master_enabled(XilinxSPI *s)
173 {
174     return !(s->regs[R_SPICR] & R_SPICR_MTI);
175 }
176 
177 static void spi_flush_txfifo(XilinxSPI *s)
178 {
179     uint32_t tx;
180     uint32_t rx;
181 
182     while (!fifo8_is_empty(&s->tx_fifo)) {
183         tx = (uint32_t)fifo8_pop(&s->tx_fifo);
184         DB_PRINT("data tx:%x\n", tx);
185         rx = ssi_transfer(s->spi, tx);
186         DB_PRINT("data rx:%x\n", rx);
187         if (fifo8_is_full(&s->rx_fifo)) {
188             s->regs[R_IPISR] |= IRQ_DRR_OVERRUN;
189         } else {
190             fifo8_push(&s->rx_fifo, (uint8_t)rx);
191             if (fifo8_is_full(&s->rx_fifo)) {
192                 s->regs[R_SPISR] |= SR_RX_FULL;
193                 s->regs[R_IPISR] |= IRQ_DRR_FULL;
194             }
195         }
196 
197         s->regs[R_SPISR] &= ~SR_RX_EMPTY;
198         s->regs[R_SPISR] &= ~SR_TX_FULL;
199         s->regs[R_SPISR] |= SR_TX_EMPTY;
200 
201         s->regs[R_IPISR] |= IRQ_DTR_EMPTY;
202         s->regs[R_IPISR] |= IRQ_DRR_NOT_EMPTY;
203     }
204 
205 }
206 
207 static uint64_t
208 spi_read(void *opaque, hwaddr addr, unsigned int size)
209 {
210     XilinxSPI *s = opaque;
211     uint32_t r = 0;
212 
213     addr >>= 2;
214     switch (addr) {
215     case R_SPIDRR:
216         if (fifo8_is_empty(&s->rx_fifo)) {
217             DB_PRINT("Read from empty FIFO!\n");
218             return 0xdeadbeef;
219         }
220 
221         s->regs[R_SPISR] &= ~SR_RX_FULL;
222         r = fifo8_pop(&s->rx_fifo);
223         if (fifo8_is_empty(&s->rx_fifo)) {
224             s->regs[R_SPISR] |= SR_RX_EMPTY;
225         }
226         break;
227 
228     case R_SPISR:
229         r = s->regs[addr];
230         break;
231 
232     default:
233         if (addr < ARRAY_SIZE(s->regs)) {
234             r = s->regs[addr];
235         }
236         break;
237 
238     }
239     DB_PRINT("addr=" HWADDR_FMT_plx " = %x\n", addr * 4, r);
240     xlx_spi_update_irq(s);
241     return r;
242 }
243 
244 static void
245 spi_write(void *opaque, hwaddr addr,
246             uint64_t val64, unsigned int size)
247 {
248     XilinxSPI *s = opaque;
249     uint32_t value = val64;
250 
251     DB_PRINT("addr=" HWADDR_FMT_plx " = %x\n", addr, value);
252     addr >>= 2;
253     switch (addr) {
254     case R_SRR:
255         if (value != 0xa) {
256             DB_PRINT("Invalid write to SRR %x\n", value);
257         } else {
258             xlx_spi_do_reset(s);
259         }
260         break;
261 
262     case R_SPIDTR:
263         s->regs[R_SPISR] &= ~SR_TX_EMPTY;
264         fifo8_push(&s->tx_fifo, (uint8_t)value);
265         if (fifo8_is_full(&s->tx_fifo)) {
266             s->regs[R_SPISR] |= SR_TX_FULL;
267         }
268         if (!spi_master_enabled(s)) {
269             goto done;
270         } else {
271             DB_PRINT("DTR and master enabled\n");
272         }
273         spi_flush_txfifo(s);
274         break;
275 
276     case R_SPISR:
277         DB_PRINT("Invalid write to SPISR %x\n", value);
278         break;
279 
280     case R_IPISR:
281         /* Toggle the bits.  */
282         s->regs[addr] ^= value;
283         break;
284 
285     /* Slave Select Register.  */
286     case R_SPISSR:
287         s->regs[addr] = value;
288         xlx_spi_update_cs(s);
289         break;
290 
291     case R_SPICR:
292         /* FIXME: reset irq and sr state to empty queues.  */
293         if (value & R_SPICR_RXFF_RST) {
294             rxfifo_reset(s);
295         }
296 
297         if (value & R_SPICR_TXFF_RST) {
298             txfifo_reset(s);
299         }
300         value &= ~(R_SPICR_RXFF_RST | R_SPICR_TXFF_RST);
301         s->regs[addr] = value;
302 
303         if (!(value & R_SPICR_MTI)) {
304             spi_flush_txfifo(s);
305         }
306         break;
307 
308     default:
309         if (addr < ARRAY_SIZE(s->regs)) {
310             s->regs[addr] = value;
311         }
312         break;
313     }
314 
315 done:
316     xlx_spi_update_irq(s);
317 }
318 
319 static const MemoryRegionOps spi_ops[2] = {
320     [0 ... 1] = {
321         .read = spi_read,
322         .write = spi_write,
323         .valid = {
324             .min_access_size = 4,
325             .max_access_size = 4,
326         },
327     },
328     [0].endianness = DEVICE_LITTLE_ENDIAN,
329     [1].endianness = DEVICE_BIG_ENDIAN,
330 };
331 
332 static void xilinx_spi_realize(DeviceState *dev, Error **errp)
333 {
334     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
335     XilinxSPI *s = XILINX_SPI(dev);
336     int i;
337 
338     if (s->model_endianness == ENDIAN_MODE_UNSPECIFIED) {
339         error_setg(errp, TYPE_XILINX_SPI " property 'endianness'"
340                          " must be set to 'big' or 'little'");
341         return;
342     }
343 
344     DB_PRINT("\n");
345 
346     s->spi = ssi_create_bus(dev, "spi");
347 
348     sysbus_init_irq(sbd, &s->irq);
349     s->cs_lines = g_new0(qemu_irq, s->num_cs);
350     for (i = 0; i < s->num_cs; ++i) {
351         sysbus_init_irq(sbd, &s->cs_lines[i]);
352     }
353 
354     memory_region_init_io(&s->mmio, OBJECT(s),
355                           &spi_ops[s->model_endianness == ENDIAN_MODE_BIG], s,
356                           "xilinx-spi", R_MAX * 4);
357     sysbus_init_mmio(sbd, &s->mmio);
358 
359     s->irqline = -1;
360 
361     fifo8_create(&s->tx_fifo, FIFO_CAPACITY);
362     fifo8_create(&s->rx_fifo, FIFO_CAPACITY);
363 }
364 
365 static const VMStateDescription vmstate_xilinx_spi = {
366     .name = "xilinx_spi",
367     .version_id = 1,
368     .minimum_version_id = 1,
369     .fields = (const VMStateField[]) {
370         VMSTATE_FIFO8(tx_fifo, XilinxSPI),
371         VMSTATE_FIFO8(rx_fifo, XilinxSPI),
372         VMSTATE_UINT32_ARRAY(regs, XilinxSPI, R_MAX),
373         VMSTATE_END_OF_LIST()
374     }
375 };
376 
377 static const Property xilinx_spi_properties[] = {
378     DEFINE_PROP_ENDIAN_NODEFAULT("endianness", XilinxSPI, model_endianness),
379     DEFINE_PROP_UINT8("num-ss-bits", XilinxSPI, num_cs, 1),
380 };
381 
382 static void xilinx_spi_class_init(ObjectClass *klass, void *data)
383 {
384     DeviceClass *dc = DEVICE_CLASS(klass);
385 
386     dc->realize = xilinx_spi_realize;
387     device_class_set_legacy_reset(dc, xlx_spi_reset);
388     device_class_set_props(dc, xilinx_spi_properties);
389     dc->vmsd = &vmstate_xilinx_spi;
390 }
391 
392 static const TypeInfo xilinx_spi_info = {
393     .name           = TYPE_XILINX_SPI,
394     .parent         = TYPE_SYS_BUS_DEVICE,
395     .instance_size  = sizeof(XilinxSPI),
396     .class_init     = xilinx_spi_class_init,
397 };
398 
399 static void xilinx_spi_register_types(void)
400 {
401     type_register_static(&xilinx_spi_info);
402 }
403 
404 type_init(xilinx_spi_register_types)
405