15ae74402SAlistair Francis /* 25ae74402SAlistair Francis * STM32F405 SPI 35ae74402SAlistair Francis * 45ae74402SAlistair Francis * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 55ae74402SAlistair Francis * 65ae74402SAlistair Francis * Permission is hereby granted, free of charge, to any person obtaining a copy 75ae74402SAlistair Francis * of this software and associated documentation files (the "Software"), to deal 85ae74402SAlistair Francis * in the Software without restriction, including without limitation the rights 95ae74402SAlistair Francis * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 105ae74402SAlistair Francis * copies of the Software, and to permit persons to whom the Software is 115ae74402SAlistair Francis * furnished to do so, subject to the following conditions: 125ae74402SAlistair Francis * 135ae74402SAlistair Francis * The above copyright notice and this permission notice shall be included in 145ae74402SAlistair Francis * all copies or substantial portions of the Software. 155ae74402SAlistair Francis * 165ae74402SAlistair Francis * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 175ae74402SAlistair Francis * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 185ae74402SAlistair Francis * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 195ae74402SAlistair Francis * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 205ae74402SAlistair Francis * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 215ae74402SAlistair Francis * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 225ae74402SAlistair Francis * THE SOFTWARE. 235ae74402SAlistair Francis */ 245ae74402SAlistair Francis 255ae74402SAlistair Francis #include "qemu/osdep.h" 265ae74402SAlistair Francis #include "qemu/log.h" 27*0b8fa32fSMarkus Armbruster #include "qemu/module.h" 285ae74402SAlistair Francis #include "hw/ssi/stm32f2xx_spi.h" 295ae74402SAlistair Francis 305ae74402SAlistair Francis #ifndef STM_SPI_ERR_DEBUG 315ae74402SAlistair Francis #define STM_SPI_ERR_DEBUG 0 325ae74402SAlistair Francis #endif 335ae74402SAlistair Francis 345ae74402SAlistair Francis #define DB_PRINT_L(lvl, fmt, args...) do { \ 355ae74402SAlistair Francis if (STM_SPI_ERR_DEBUG >= lvl) { \ 365ae74402SAlistair Francis qemu_log("%s: " fmt, __func__, ## args); \ 375ae74402SAlistair Francis } \ 382562755eSEric Blake } while (0) 395ae74402SAlistair Francis 405ae74402SAlistair Francis #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) 415ae74402SAlistair Francis 425ae74402SAlistair Francis static void stm32f2xx_spi_reset(DeviceState *dev) 435ae74402SAlistair Francis { 445ae74402SAlistair Francis STM32F2XXSPIState *s = STM32F2XX_SPI(dev); 455ae74402SAlistair Francis 465ae74402SAlistair Francis s->spi_cr1 = 0x00000000; 475ae74402SAlistair Francis s->spi_cr2 = 0x00000000; 485ae74402SAlistair Francis s->spi_sr = 0x0000000A; 495ae74402SAlistair Francis s->spi_dr = 0x0000000C; 505ae74402SAlistair Francis s->spi_crcpr = 0x00000007; 515ae74402SAlistair Francis s->spi_rxcrcr = 0x00000000; 525ae74402SAlistair Francis s->spi_txcrcr = 0x00000000; 535ae74402SAlistair Francis s->spi_i2scfgr = 0x00000000; 545ae74402SAlistair Francis s->spi_i2spr = 0x00000002; 555ae74402SAlistair Francis } 565ae74402SAlistair Francis 575ae74402SAlistair Francis static void stm32f2xx_spi_transfer(STM32F2XXSPIState *s) 585ae74402SAlistair Francis { 595ae74402SAlistair Francis DB_PRINT("Data to send: 0x%x\n", s->spi_dr); 605ae74402SAlistair Francis 615ae74402SAlistair Francis s->spi_dr = ssi_transfer(s->ssi, s->spi_dr); 625ae74402SAlistair Francis s->spi_sr |= STM_SPI_SR_RXNE; 635ae74402SAlistair Francis 645ae74402SAlistair Francis DB_PRINT("Data received: 0x%x\n", s->spi_dr); 655ae74402SAlistair Francis } 665ae74402SAlistair Francis 675ae74402SAlistair Francis static uint64_t stm32f2xx_spi_read(void *opaque, hwaddr addr, 685ae74402SAlistair Francis unsigned int size) 695ae74402SAlistair Francis { 705ae74402SAlistair Francis STM32F2XXSPIState *s = opaque; 715ae74402SAlistair Francis 725ae74402SAlistair Francis DB_PRINT("Address: 0x%" HWADDR_PRIx "\n", addr); 735ae74402SAlistair Francis 745ae74402SAlistair Francis switch (addr) { 755ae74402SAlistair Francis case STM_SPI_CR1: 765ae74402SAlistair Francis return s->spi_cr1; 775ae74402SAlistair Francis case STM_SPI_CR2: 785ae74402SAlistair Francis qemu_log_mask(LOG_UNIMP, "%s: Interrupts and DMA are not implemented\n", 795ae74402SAlistair Francis __func__); 805ae74402SAlistair Francis return s->spi_cr2; 815ae74402SAlistair Francis case STM_SPI_SR: 825ae74402SAlistair Francis return s->spi_sr; 835ae74402SAlistair Francis case STM_SPI_DR: 845ae74402SAlistair Francis stm32f2xx_spi_transfer(s); 855ae74402SAlistair Francis s->spi_sr &= ~STM_SPI_SR_RXNE; 865ae74402SAlistair Francis return s->spi_dr; 875ae74402SAlistair Francis case STM_SPI_CRCPR: 885ae74402SAlistair Francis qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \ 895ae74402SAlistair Francis "are included for compatibility\n", __func__); 905ae74402SAlistair Francis return s->spi_crcpr; 915ae74402SAlistair Francis case STM_SPI_RXCRCR: 925ae74402SAlistair Francis qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \ 935ae74402SAlistair Francis "are included for compatibility\n", __func__); 945ae74402SAlistair Francis return s->spi_rxcrcr; 955ae74402SAlistair Francis case STM_SPI_TXCRCR: 965ae74402SAlistair Francis qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \ 975ae74402SAlistair Francis "are included for compatibility\n", __func__); 985ae74402SAlistair Francis return s->spi_txcrcr; 995ae74402SAlistair Francis case STM_SPI_I2SCFGR: 1005ae74402SAlistair Francis qemu_log_mask(LOG_UNIMP, "%s: I2S is not implemented, the registers " \ 1015ae74402SAlistair Francis "are included for compatibility\n", __func__); 1025ae74402SAlistair Francis return s->spi_i2scfgr; 1035ae74402SAlistair Francis case STM_SPI_I2SPR: 1045ae74402SAlistair Francis qemu_log_mask(LOG_UNIMP, "%s: I2S is not implemented, the registers " \ 1055ae74402SAlistair Francis "are included for compatibility\n", __func__); 1065ae74402SAlistair Francis return s->spi_i2spr; 1075ae74402SAlistair Francis default: 1085ae74402SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", 1095ae74402SAlistair Francis __func__, addr); 1105ae74402SAlistair Francis } 1115ae74402SAlistair Francis 1125ae74402SAlistair Francis return 0; 1135ae74402SAlistair Francis } 1145ae74402SAlistair Francis 1155ae74402SAlistair Francis static void stm32f2xx_spi_write(void *opaque, hwaddr addr, 1165ae74402SAlistair Francis uint64_t val64, unsigned int size) 1175ae74402SAlistair Francis { 1185ae74402SAlistair Francis STM32F2XXSPIState *s = opaque; 1195ae74402SAlistair Francis uint32_t value = val64; 1205ae74402SAlistair Francis 1215ae74402SAlistair Francis DB_PRINT("Address: 0x%" HWADDR_PRIx ", Value: 0x%x\n", addr, value); 1225ae74402SAlistair Francis 1235ae74402SAlistair Francis switch (addr) { 1245ae74402SAlistair Francis case STM_SPI_CR1: 1255ae74402SAlistair Francis s->spi_cr1 = value; 1265ae74402SAlistair Francis return; 1275ae74402SAlistair Francis case STM_SPI_CR2: 1285ae74402SAlistair Francis qemu_log_mask(LOG_UNIMP, "%s: " \ 1295ae74402SAlistair Francis "Interrupts and DMA are not implemented\n", __func__); 1305ae74402SAlistair Francis s->spi_cr2 = value; 1315ae74402SAlistair Francis return; 1325ae74402SAlistair Francis case STM_SPI_SR: 1335ae74402SAlistair Francis /* Read only register, except for clearing the CRCERR bit, which 1345ae74402SAlistair Francis * is not supported 1355ae74402SAlistair Francis */ 1365ae74402SAlistair Francis return; 1375ae74402SAlistair Francis case STM_SPI_DR: 1385ae74402SAlistair Francis s->spi_dr = value; 1395ae74402SAlistair Francis stm32f2xx_spi_transfer(s); 1405ae74402SAlistair Francis return; 1415ae74402SAlistair Francis case STM_SPI_CRCPR: 1425ae74402SAlistair Francis qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented\n", __func__); 1435ae74402SAlistair Francis return; 1445ae74402SAlistair Francis case STM_SPI_RXCRCR: 1455ae74402SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, "%s: Read only register: " \ 1465ae74402SAlistair Francis "0x%" HWADDR_PRIx "\n", __func__, addr); 1475ae74402SAlistair Francis return; 1485ae74402SAlistair Francis case STM_SPI_TXCRCR: 1495ae74402SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, "%s: Read only register: " \ 1505ae74402SAlistair Francis "0x%" HWADDR_PRIx "\n", __func__, addr); 1515ae74402SAlistair Francis return; 1525ae74402SAlistair Francis case STM_SPI_I2SCFGR: 1535ae74402SAlistair Francis qemu_log_mask(LOG_UNIMP, "%s: " \ 1545ae74402SAlistair Francis "I2S is not implemented\n", __func__); 1555ae74402SAlistair Francis return; 1565ae74402SAlistair Francis case STM_SPI_I2SPR: 1575ae74402SAlistair Francis qemu_log_mask(LOG_UNIMP, "%s: " \ 1585ae74402SAlistair Francis "I2S is not implemented\n", __func__); 1595ae74402SAlistair Francis return; 1605ae74402SAlistair Francis default: 1615ae74402SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, 1625ae74402SAlistair Francis "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr); 1635ae74402SAlistair Francis } 1645ae74402SAlistair Francis } 1655ae74402SAlistair Francis 1665ae74402SAlistair Francis static const MemoryRegionOps stm32f2xx_spi_ops = { 1675ae74402SAlistair Francis .read = stm32f2xx_spi_read, 1685ae74402SAlistair Francis .write = stm32f2xx_spi_write, 1695ae74402SAlistair Francis .endianness = DEVICE_NATIVE_ENDIAN, 1705ae74402SAlistair Francis }; 1715ae74402SAlistair Francis 1725ae74402SAlistair Francis static const VMStateDescription vmstate_stm32f2xx_spi = { 1735ae74402SAlistair Francis .name = TYPE_STM32F2XX_SPI, 1745ae74402SAlistair Francis .version_id = 1, 1755ae74402SAlistair Francis .minimum_version_id = 1, 1765ae74402SAlistair Francis .fields = (VMStateField[]) { 1775ae74402SAlistair Francis VMSTATE_UINT32(spi_cr1, STM32F2XXSPIState), 1785ae74402SAlistair Francis VMSTATE_UINT32(spi_cr2, STM32F2XXSPIState), 1795ae74402SAlistair Francis VMSTATE_UINT32(spi_sr, STM32F2XXSPIState), 1805ae74402SAlistair Francis VMSTATE_UINT32(spi_dr, STM32F2XXSPIState), 1815ae74402SAlistair Francis VMSTATE_UINT32(spi_crcpr, STM32F2XXSPIState), 1825ae74402SAlistair Francis VMSTATE_UINT32(spi_rxcrcr, STM32F2XXSPIState), 1835ae74402SAlistair Francis VMSTATE_UINT32(spi_txcrcr, STM32F2XXSPIState), 1845ae74402SAlistair Francis VMSTATE_UINT32(spi_i2scfgr, STM32F2XXSPIState), 1855ae74402SAlistair Francis VMSTATE_UINT32(spi_i2spr, STM32F2XXSPIState), 1865ae74402SAlistair Francis VMSTATE_END_OF_LIST() 1875ae74402SAlistair Francis } 1885ae74402SAlistair Francis }; 1895ae74402SAlistair Francis 1905ae74402SAlistair Francis static void stm32f2xx_spi_init(Object *obj) 1915ae74402SAlistair Francis { 1925ae74402SAlistair Francis STM32F2XXSPIState *s = STM32F2XX_SPI(obj); 1935ae74402SAlistair Francis DeviceState *dev = DEVICE(obj); 1945ae74402SAlistair Francis 1955ae74402SAlistair Francis memory_region_init_io(&s->mmio, obj, &stm32f2xx_spi_ops, s, 1965ae74402SAlistair Francis TYPE_STM32F2XX_SPI, 0x400); 1975ae74402SAlistair Francis sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 1985ae74402SAlistair Francis 1995ae74402SAlistair Francis sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 2005ae74402SAlistair Francis 2015ae74402SAlistair Francis s->ssi = ssi_create_bus(dev, "ssi"); 2025ae74402SAlistair Francis } 2035ae74402SAlistair Francis 2045ae74402SAlistair Francis static void stm32f2xx_spi_class_init(ObjectClass *klass, void *data) 2055ae74402SAlistair Francis { 2065ae74402SAlistair Francis DeviceClass *dc = DEVICE_CLASS(klass); 2075ae74402SAlistair Francis 2085ae74402SAlistair Francis dc->reset = stm32f2xx_spi_reset; 2095ae74402SAlistair Francis dc->vmsd = &vmstate_stm32f2xx_spi; 2105ae74402SAlistair Francis } 2115ae74402SAlistair Francis 2125ae74402SAlistair Francis static const TypeInfo stm32f2xx_spi_info = { 2135ae74402SAlistair Francis .name = TYPE_STM32F2XX_SPI, 2145ae74402SAlistair Francis .parent = TYPE_SYS_BUS_DEVICE, 2155ae74402SAlistair Francis .instance_size = sizeof(STM32F2XXSPIState), 2165ae74402SAlistair Francis .instance_init = stm32f2xx_spi_init, 2175ae74402SAlistair Francis .class_init = stm32f2xx_spi_class_init, 2185ae74402SAlistair Francis }; 2195ae74402SAlistair Francis 2205ae74402SAlistair Francis static void stm32f2xx_spi_register_types(void) 2215ae74402SAlistair Francis { 2225ae74402SAlistair Francis type_register_static(&stm32f2xx_spi_info); 2235ae74402SAlistair Francis } 2245ae74402SAlistair Francis 2255ae74402SAlistair Francis type_init(stm32f2xx_spi_register_types) 226