1 /* 2 * QEMU PowerPC SPI model 3 * 4 * Copyright (c) 2024, IBM Corporation. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #include "qemu/osdep.h" 10 #include "qemu/log.h" 11 #include "hw/qdev-properties.h" 12 #include "hw/ppc/pnv_xscom.h" 13 #include "hw/ssi/pnv_spi.h" 14 #include "hw/ssi/pnv_spi_regs.h" 15 #include "hw/ssi/ssi.h" 16 #include <libfdt.h> 17 #include "hw/irq.h" 18 #include "trace.h" 19 20 #define PNV_SPI_OPCODE_LO_NIBBLE(x) (x & 0x0F) 21 #define PNV_SPI_MASKED_OPCODE(x) (x & 0xF0) 22 23 /* 24 * Macro from include/hw/ppc/fdt.h 25 * fdt.h cannot be included here as it contain ppc target specific dependency. 26 */ 27 #define _FDT(exp) \ 28 do { \ 29 int _ret = (exp); \ 30 if (_ret < 0) { \ 31 qemu_log_mask(LOG_GUEST_ERROR, \ 32 "error creating device tree: %s: %s", \ 33 #exp, fdt_strerror(_ret)); \ 34 exit(1); \ 35 } \ 36 } while (0) 37 38 /* PnvXferBuffer */ 39 typedef struct PnvXferBuffer { 40 41 uint32_t len; 42 uint8_t *data; 43 44 } PnvXferBuffer; 45 46 /* pnv_spi_xfer_buffer_methods */ 47 static PnvXferBuffer *pnv_spi_xfer_buffer_new(void) 48 { 49 PnvXferBuffer *payload = g_malloc0(sizeof(*payload)); 50 51 return payload; 52 } 53 54 static void pnv_spi_xfer_buffer_free(PnvXferBuffer *payload) 55 { 56 g_free(payload->data); 57 g_free(payload); 58 } 59 60 static uint8_t *pnv_spi_xfer_buffer_write_ptr(PnvXferBuffer *payload, 61 uint32_t offset, uint32_t length) 62 { 63 if (payload->len < (offset + length)) { 64 payload->len = offset + length; 65 payload->data = g_realloc(payload->data, payload->len); 66 } 67 return &payload->data[offset]; 68 } 69 70 static bool does_rdr_match(PnvSpi *s) 71 { 72 /* 73 * According to spec, the mask bits that are 0 are compared and the 74 * bits that are 1 are ignored. 75 */ 76 uint16_t rdr_match_mask = GETFIELD(SPI_MM_RDR_MATCH_MASK, 77 s->regs[SPI_MM_REG]); 78 uint16_t rdr_match_val = GETFIELD(SPI_MM_RDR_MATCH_VAL, 79 s->regs[SPI_MM_REG]); 80 81 if ((~rdr_match_mask & rdr_match_val) == ((~rdr_match_mask) & 82 GETFIELD(PPC_BITMASK(48, 63), s->regs[SPI_RCV_DATA_REG]))) { 83 return true; 84 } 85 return false; 86 } 87 88 static uint8_t get_from_offset(PnvSpi *s, uint8_t offset) 89 { 90 uint8_t byte; 91 92 /* 93 * Offset is an index between 0 and PNV_SPI_REG_SIZE - 1 94 * Check the offset before using it. 95 */ 96 if (offset < PNV_SPI_REG_SIZE) { 97 byte = (s->regs[SPI_XMIT_DATA_REG] >> (56 - offset * 8)) & 0xFF; 98 } else { 99 /* 100 * Log an error and return a 0xFF since we have to assign something 101 * to byte before returning. 102 */ 103 qemu_log_mask(LOG_GUEST_ERROR, "Invalid offset = %d used to get byte " 104 "from TDR\n", offset); 105 byte = 0xff; 106 } 107 return byte; 108 } 109 110 static uint8_t read_from_frame(PnvSpi *s, uint8_t *read_buf, uint8_t nr_bytes, 111 uint8_t ecc_count, uint8_t shift_in_count) 112 { 113 uint8_t byte; 114 int count = 0; 115 116 while (count < nr_bytes) { 117 shift_in_count++; 118 if ((ecc_count != 0) && 119 (shift_in_count == (PNV_SPI_REG_SIZE + ecc_count))) { 120 shift_in_count = 0; 121 } else { 122 byte = read_buf[count]; 123 trace_pnv_spi_shift_rx(byte, count); 124 s->regs[SPI_RCV_DATA_REG] = (s->regs[SPI_RCV_DATA_REG] << 8) | byte; 125 } 126 count++; 127 } /* end of while */ 128 return shift_in_count; 129 } 130 131 static void spi_response(PnvSpi *s, int bits, PnvXferBuffer *rsp_payload) 132 { 133 uint8_t ecc_count; 134 uint8_t shift_in_count; 135 136 /* 137 * Processing here must handle: 138 * - Which bytes in the payload we should move to the RDR 139 * - Explicit mode counter configuration settings 140 * - RDR full and RDR overrun status 141 */ 142 143 /* 144 * First check that the response payload is the exact same 145 * number of bytes as the request payload was 146 */ 147 if (rsp_payload->len != (s->N1_bytes + s->N2_bytes)) { 148 qemu_log_mask(LOG_GUEST_ERROR, "Invalid response payload size in " 149 "bytes, expected %d, got %d\n", 150 (s->N1_bytes + s->N2_bytes), rsp_payload->len); 151 } else { 152 uint8_t ecc_control; 153 trace_pnv_spi_rx_received(rsp_payload->len); 154 trace_pnv_spi_log_Ncounts(s->N1_bits, s->N1_bytes, s->N1_tx, 155 s->N1_rx, s->N2_bits, s->N2_bytes, s->N2_tx, s->N2_rx); 156 /* 157 * Adding an ECC count let's us know when we have found a payload byte 158 * that was shifted in but cannot be loaded into RDR. Bits 29-30 of 159 * clock_config_reset_control register equal to either 0b00 or 0b10 160 * indicate that we are taking in data with ECC and either applying 161 * the ECC or discarding it. 162 */ 163 ecc_count = 0; 164 ecc_control = GETFIELD(SPI_CLK_CFG_ECC_CTRL, s->regs[SPI_CLK_CFG_REG]); 165 if (ecc_control == 0 || ecc_control == 2) { 166 ecc_count = 1; 167 } 168 /* 169 * Use the N1_rx and N2_rx counts to control shifting data from the 170 * payload into the RDR. Keep an overall count of the number of bytes 171 * shifted into RDR so we can discard every 9th byte when ECC is 172 * enabled. 173 */ 174 shift_in_count = 0; 175 /* Handle the N1 portion of the frame first */ 176 if (s->N1_rx != 0) { 177 trace_pnv_spi_rx_read_N1frame(); 178 shift_in_count = read_from_frame(s, &rsp_payload->data[0], 179 s->N1_bytes, ecc_count, shift_in_count); 180 } 181 /* Handle the N2 portion of the frame */ 182 if (s->N2_rx != 0) { 183 trace_pnv_spi_rx_read_N2frame(); 184 shift_in_count = read_from_frame(s, 185 &rsp_payload->data[s->N1_bytes], s->N2_bytes, 186 ecc_count, shift_in_count); 187 } 188 if ((s->N1_rx + s->N2_rx) > 0) { 189 /* 190 * Data was received so handle RDR status. 191 * It is easier to handle RDR_full and RDR_overrun status here 192 * since the RDR register's shift_byte_in method is called 193 * multiple times in a row. Controlling RDR status is done here 194 * instead of in the RDR scoped methods for that reason. 195 */ 196 if (GETFIELD(SPI_STS_RDR_FULL, s->status) == 1) { 197 /* 198 * Data was shifted into the RDR before having been read 199 * causing previous data to have been overrun. 200 */ 201 s->status = SETFIELD(SPI_STS_RDR_OVERRUN, s->status, 1); 202 } else { 203 /* 204 * Set status to indicate that the received data register is 205 * full. This flag is only cleared once the RDR is unloaded. 206 */ 207 s->status = SETFIELD(SPI_STS_RDR_FULL, s->status, 1); 208 } 209 } 210 } /* end of else */ 211 } /* end of spi_response() */ 212 213 static void transfer(PnvSpi *s, PnvXferBuffer *payload) 214 { 215 uint32_t tx; 216 uint32_t rx; 217 PnvXferBuffer *rsp_payload = NULL; 218 219 rsp_payload = pnv_spi_xfer_buffer_new(); 220 if (!rsp_payload) { 221 return; 222 } 223 for (int offset = 0; offset < payload->len; offset += s->transfer_len) { 224 tx = 0; 225 for (int i = 0; i < s->transfer_len; i++) { 226 if ((offset + i) >= payload->len) { 227 tx <<= 8; 228 } else { 229 tx = (tx << 8) | payload->data[offset + i]; 230 } 231 } 232 rx = ssi_transfer(s->ssi_bus, tx); 233 for (int i = 0; i < s->transfer_len; i++) { 234 if ((offset + i) >= payload->len) { 235 break; 236 } 237 *(pnv_spi_xfer_buffer_write_ptr(rsp_payload, rsp_payload->len, 1)) = 238 (rx >> (8 * (s->transfer_len - 1) - i * 8)) & 0xFF; 239 } 240 } 241 spi_response(s, s->N1_bits, rsp_payload); 242 } 243 244 static inline uint8_t get_seq_index(PnvSpi *s) 245 { 246 return GETFIELD(SPI_STS_SEQ_INDEX, s->status); 247 } 248 249 static inline void next_sequencer_fsm(PnvSpi *s) 250 { 251 uint8_t seq_index = get_seq_index(s); 252 s->status = SETFIELD(SPI_STS_SEQ_INDEX, s->status, (seq_index + 1)); 253 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_INDEX_INCREMENT); 254 } 255 256 /* 257 * Calculate the N1 counters based on passed in opcode and 258 * internal register values. 259 * The method assumes that the opcode is a Shift_N1 opcode 260 * and doesn't test it. 261 * The counters returned are: 262 * N1 bits: Number of bits in the payload data that are significant 263 * to the responder. 264 * N1_bytes: Total count of payload bytes for the N1 (portion of the) frame. 265 * N1_tx: Total number of bytes taken from TDR for N1 266 * N1_rx: Total number of bytes taken from the payload for N1 267 */ 268 static void calculate_N1(PnvSpi *s, uint8_t opcode) 269 { 270 /* 271 * Shift_N1 opcode form: 0x3M 272 * Implicit mode: 273 * If M != 0 the shift count is M bytes and M is the number of tx bytes. 274 * Forced Implicit mode: 275 * M is the shift count but tx and rx is determined by the count control 276 * register fields. Note that we only check for forced Implicit mode when 277 * M != 0 since the mode doesn't make sense when M = 0. 278 * Explicit mode: 279 * If M == 0 then shift count is number of bits defined in the 280 * Counter Configuration Register's shift_count_N1 field. 281 */ 282 if (PNV_SPI_OPCODE_LO_NIBBLE(opcode) == 0) { 283 /* Explicit mode */ 284 s->N1_bits = GETFIELD(SPI_CTR_CFG_N1, s->regs[SPI_CTR_CFG_REG]); 285 s->N1_bytes = (s->N1_bits + 7) / 8; 286 s->N1_tx = 0; 287 s->N1_rx = 0; 288 /* If tx count control for N1 is set, load the tx value */ 289 if (GETFIELD(SPI_CTR_CFG_N1_CTRL_B2, s->regs[SPI_CTR_CFG_REG]) == 1) { 290 s->N1_tx = s->N1_bytes; 291 } 292 /* If rx count control for N1 is set, load the rx value */ 293 if (GETFIELD(SPI_CTR_CFG_N1_CTRL_B3, s->regs[SPI_CTR_CFG_REG]) == 1) { 294 s->N1_rx = s->N1_bytes; 295 } 296 } else { 297 /* Implicit mode/Forced Implicit mode, use M field from opcode */ 298 s->N1_bytes = PNV_SPI_OPCODE_LO_NIBBLE(opcode); 299 s->N1_bits = s->N1_bytes * 8; 300 /* 301 * Assume that we are going to transmit the count 302 * (pure Implicit only) 303 */ 304 s->N1_tx = s->N1_bytes; 305 s->N1_rx = 0; 306 /* Let Forced Implicit mode have an effect on the counts */ 307 if (GETFIELD(SPI_CTR_CFG_N1_CTRL_B1, s->regs[SPI_CTR_CFG_REG]) == 1) { 308 /* 309 * If Forced Implicit mode and count control doesn't 310 * indicate transmit then reset the tx count to 0 311 */ 312 if (GETFIELD(SPI_CTR_CFG_N1_CTRL_B2, 313 s->regs[SPI_CTR_CFG_REG]) == 0) { 314 s->N1_tx = 0; 315 } 316 /* If rx count control for N1 is set, load the rx value */ 317 if (GETFIELD(SPI_CTR_CFG_N1_CTRL_B3, 318 s->regs[SPI_CTR_CFG_REG]) == 1) { 319 s->N1_rx = s->N1_bytes; 320 } 321 } 322 } 323 /* 324 * Enforce an upper limit on the size of N1 that is equal to the known size 325 * of the shift register, 64 bits or 72 bits if ECC is enabled. 326 * If the size exceeds 72 bits it is a user error so log an error, 327 * cap the size at a max of 64 bits or 72 bits and set the sequencer FSM 328 * error bit. 329 */ 330 uint8_t ecc_control = GETFIELD(SPI_CLK_CFG_ECC_CTRL, 331 s->regs[SPI_CLK_CFG_REG]); 332 if (ecc_control == 0 || ecc_control == 2) { 333 if (s->N1_bytes > (PNV_SPI_REG_SIZE + 1)) { 334 qemu_log_mask(LOG_GUEST_ERROR, "Unsupported N1 shift size when " 335 "ECC enabled, bytes = 0x%x, bits = 0x%x\n", 336 s->N1_bytes, s->N1_bits); 337 s->N1_bytes = PNV_SPI_REG_SIZE + 1; 338 s->N1_bits = s->N1_bytes * 8; 339 } 340 } else if (s->N1_bytes > PNV_SPI_REG_SIZE) { 341 qemu_log_mask(LOG_GUEST_ERROR, "Unsupported N1 shift size, " 342 "bytes = 0x%x, bits = 0x%x\n", 343 s->N1_bytes, s->N1_bits); 344 s->N1_bytes = PNV_SPI_REG_SIZE; 345 s->N1_bits = s->N1_bytes * 8; 346 } 347 } /* end of calculate_N1 */ 348 349 /* 350 * Shift_N1 operation handler method 351 */ 352 static bool operation_shiftn1(PnvSpi *s, uint8_t opcode, 353 PnvXferBuffer **payload, bool send_n1_alone) 354 { 355 uint8_t n1_count; 356 bool stop = false; 357 358 /* 359 * If there isn't a current payload left over from a stopped sequence 360 * create a new one. 361 */ 362 if (*payload == NULL) { 363 *payload = pnv_spi_xfer_buffer_new(); 364 } 365 /* 366 * Use a combination of N1 counters to build the N1 portion of the 367 * transmit payload. 368 * We only care about transmit at this time since the request payload 369 * only represents data going out on the controller output line. 370 * Leave mode specific considerations in the calculate function since 371 * all we really care about are counters that tell use exactly how 372 * many bytes are in the payload and how many of those bytes to 373 * include from the TDR into the payload. 374 */ 375 calculate_N1(s, opcode); 376 trace_pnv_spi_log_Ncounts(s->N1_bits, s->N1_bytes, s->N1_tx, 377 s->N1_rx, s->N2_bits, s->N2_bytes, s->N2_tx, s->N2_rx); 378 /* 379 * Zero out the N2 counters here in case there is no N2 operation following 380 * the N1 operation in the sequencer. This keeps leftover N2 information 381 * from interfering with spi_response logic. 382 */ 383 s->N2_bits = 0; 384 s->N2_bytes = 0; 385 s->N2_tx = 0; 386 s->N2_rx = 0; 387 /* 388 * N1_bytes is the overall size of the N1 portion of the frame regardless of 389 * whether N1 is used for tx, rx or both. Loop over the size to build a 390 * payload that is N1_bytes long. 391 * N1_tx is the count of bytes to take from the TDR and "shift" into the 392 * frame which means append those bytes to the payload for the N1 portion 393 * of the frame. 394 * If N1_tx is 0 or if the count exceeds the size of the TDR append 0xFF to 395 * the frame until the overall N1 count is reached. 396 */ 397 n1_count = 0; 398 while (n1_count < s->N1_bytes) { 399 /* 400 * Assuming that if N1_tx is not equal to 0 then it is the same as 401 * N1_bytes. 402 */ 403 if ((s->N1_tx != 0) && (n1_count < PNV_SPI_REG_SIZE)) { 404 405 if (GETFIELD(SPI_STS_TDR_FULL, s->status) == 1) { 406 /* 407 * Note that we are only appending to the payload IF the TDR 408 * is full otherwise we don't touch the payload because we are 409 * going to NOT send the payload and instead tell the sequencer 410 * that called us to stop and wait for a TDR write so we have 411 * data to load into the payload. 412 */ 413 uint8_t n1_byte = 0x00; 414 n1_byte = get_from_offset(s, n1_count); 415 trace_pnv_spi_tx_append("n1_byte", n1_byte, n1_count); 416 *(pnv_spi_xfer_buffer_write_ptr(*payload, (*payload)->len, 1)) = 417 n1_byte; 418 } else { 419 /* 420 * We hit a shift_n1 opcode TX but the TDR is empty, tell the 421 * sequencer to stop and break this loop. 422 */ 423 trace_pnv_spi_sequencer_stop_requested("Shift N1" 424 "set for transmit but TDR is empty"); 425 stop = true; 426 break; 427 } 428 } else { 429 /* 430 * Cases here: 431 * - we are receiving during the N1 frame segment and the RDR 432 * is full so we need to stop until the RDR is read 433 * - we are transmitting and we don't care about RDR status 434 * since we won't be loading RDR during the frame segment. 435 * - we are receiving and the RDR is empty so we allow the operation 436 * to proceed. 437 */ 438 if ((s->N1_rx != 0) && (GETFIELD(SPI_STS_RDR_FULL, 439 s->status) == 1)) { 440 trace_pnv_spi_sequencer_stop_requested("shift N1" 441 "set for receive but RDR is full"); 442 stop = true; 443 break; 444 } else { 445 trace_pnv_spi_tx_append_FF("n1_byte"); 446 *(pnv_spi_xfer_buffer_write_ptr(*payload, (*payload)->len, 1)) 447 = 0xff; 448 } 449 } 450 n1_count++; 451 } /* end of while */ 452 /* 453 * If we are not stopping due to an empty TDR and we are doing an N1 TX 454 * and the TDR is full we need to clear the TDR_full status. 455 * Do this here instead of up in the loop above so we don't log the message 456 * in every loop iteration. 457 * Ignore the send_n1_alone flag, all that does is defer the TX until the N2 458 * operation, which was found immediately after the current opcode. The TDR 459 * was unloaded and will be shifted so we have to clear the TDR_full status. 460 */ 461 if (!stop && (s->N1_tx != 0) && 462 (GETFIELD(SPI_STS_TDR_FULL, s->status) == 1)) { 463 s->status = SETFIELD(SPI_STS_TDR_FULL, s->status, 0); 464 } 465 /* 466 * There are other reasons why the shifter would stop, such as a TDR empty 467 * or RDR full condition with N1 set to receive. If we haven't stopped due 468 * to either one of those conditions then check if the send_n1_alone flag is 469 * equal to False, indicating the next opcode is an N2 operation, AND if 470 * the N2 counter reload switch (bit 0 of the N2 count control field) is 471 * set. This condition requires a pacing write to "kick" off the N2 472 * shift which includes the N1 shift as well when send_n1_alone is False. 473 */ 474 if (!stop && !send_n1_alone && 475 (GETFIELD(SPI_CTR_CFG_N2_CTRL_B0, s->regs[SPI_CTR_CFG_REG]) == 1)) { 476 trace_pnv_spi_sequencer_stop_requested("N2 counter reload " 477 "active, stop N1 shift, TDR_underrun set to 1"); 478 stop = true; 479 s->status = SETFIELD(SPI_STS_TDR_UNDERRUN, s->status, 1); 480 } 481 /* 482 * If send_n1_alone is set AND we have a full TDR then this is the first and 483 * last payload to send and we don't have an N2 frame segment to add to the 484 * payload. 485 */ 486 if (send_n1_alone && !stop) { 487 /* We have a TX and a full TDR or an RX and an empty RDR */ 488 trace_pnv_spi_tx_request("Shifting N1 frame", (*payload)->len); 489 transfer(s, *payload); 490 /* The N1 frame shift is complete so reset the N1 counters */ 491 s->N2_bits = 0; 492 s->N2_bytes = 0; 493 s->N2_tx = 0; 494 s->N2_rx = 0; 495 pnv_spi_xfer_buffer_free(*payload); 496 *payload = NULL; 497 } 498 return stop; 499 } /* end of operation_shiftn1() */ 500 501 /* 502 * Calculate the N2 counters based on passed in opcode and 503 * internal register values. 504 * The method assumes that the opcode is a Shift_N2 opcode 505 * and doesn't test it. 506 * The counters returned are: 507 * N2 bits: Number of bits in the payload data that are significant 508 * to the responder. 509 * N2_bytes: Total count of payload bytes for the N2 frame. 510 * N2_tx: Total number of bytes taken from TDR for N2 511 * N2_rx: Total number of bytes taken from the payload for N2 512 */ 513 static void calculate_N2(PnvSpi *s, uint8_t opcode) 514 { 515 /* 516 * Shift_N2 opcode form: 0x4M 517 * Implicit mode: 518 * If M!=0 the shift count is M bytes and M is the number of rx bytes. 519 * Forced Implicit mode: 520 * M is the shift count but tx and rx is determined by the count control 521 * register fields. Note that we only check for Forced Implicit mode when 522 * M != 0 since the mode doesn't make sense when M = 0. 523 * Explicit mode: 524 * If M==0 then shift count is number of bits defined in the 525 * Counter Configuration Register's shift_count_N1 field. 526 */ 527 if (PNV_SPI_OPCODE_LO_NIBBLE(opcode) == 0) { 528 /* Explicit mode */ 529 s->N2_bits = GETFIELD(SPI_CTR_CFG_N2, s->regs[SPI_CTR_CFG_REG]); 530 s->N2_bytes = (s->N2_bits + 7) / 8; 531 s->N2_tx = 0; 532 s->N2_rx = 0; 533 /* If tx count control for N2 is set, load the tx value */ 534 if (GETFIELD(SPI_CTR_CFG_N2_CTRL_B2, s->regs[SPI_CTR_CFG_REG]) == 1) { 535 s->N2_tx = s->N2_bytes; 536 } 537 /* If rx count control for N2 is set, load the rx value */ 538 if (GETFIELD(SPI_CTR_CFG_N2_CTRL_B3, s->regs[SPI_CTR_CFG_REG]) == 1) { 539 s->N2_rx = s->N2_bytes; 540 } 541 } else { 542 /* Implicit mode/Forced Implicit mode, use M field from opcode */ 543 s->N2_bytes = PNV_SPI_OPCODE_LO_NIBBLE(opcode); 544 s->N2_bits = s->N2_bytes * 8; 545 /* Assume that we are going to receive the count */ 546 s->N2_rx = s->N2_bytes; 547 s->N2_tx = 0; 548 /* Let Forced Implicit mode have an effect on the counts */ 549 if (GETFIELD(SPI_CTR_CFG_N2_CTRL_B1, s->regs[SPI_CTR_CFG_REG]) == 1) { 550 /* 551 * If Forced Implicit mode and count control doesn't 552 * indicate a receive then reset the rx count to 0 553 */ 554 if (GETFIELD(SPI_CTR_CFG_N2_CTRL_B3, 555 s->regs[SPI_CTR_CFG_REG]) == 0) { 556 s->N2_rx = 0; 557 } 558 /* If tx count control for N2 is set, load the tx value */ 559 if (GETFIELD(SPI_CTR_CFG_N2_CTRL_B2, 560 s->regs[SPI_CTR_CFG_REG]) == 1) { 561 s->N2_tx = s->N2_bytes; 562 } 563 } 564 } 565 /* 566 * Enforce an upper limit on the size of N1 that is equal to the 567 * known size of the shift register, 64 bits or 72 bits if ECC 568 * is enabled. 569 * If the size exceeds 72 bits it is a user error so log an error, 570 * cap the size at a max of 64 bits or 72 bits and set the sequencer FSM 571 * error bit. 572 */ 573 uint8_t ecc_control = GETFIELD(SPI_CLK_CFG_ECC_CTRL, 574 s->regs[SPI_CLK_CFG_REG]); 575 if (ecc_control == 0 || ecc_control == 2) { 576 if (s->N2_bytes > (PNV_SPI_REG_SIZE + 1)) { 577 /* Unsupported N2 shift size when ECC enabled */ 578 s->N2_bytes = PNV_SPI_REG_SIZE + 1; 579 s->N2_bits = s->N2_bytes * 8; 580 } 581 } else if (s->N2_bytes > PNV_SPI_REG_SIZE) { 582 /* Unsupported N2 shift size */ 583 s->N2_bytes = PNV_SPI_REG_SIZE; 584 s->N2_bits = s->N2_bytes * 8; 585 } 586 } /* end of calculate_N2 */ 587 588 /* 589 * Shift_N2 operation handler method 590 */ 591 592 static bool operation_shiftn2(PnvSpi *s, uint8_t opcode, 593 PnvXferBuffer **payload) 594 { 595 uint8_t n2_count; 596 bool stop = false; 597 598 /* 599 * If there isn't a current payload left over from a stopped sequence 600 * create a new one. 601 */ 602 if (*payload == NULL) { 603 *payload = pnv_spi_xfer_buffer_new(); 604 } 605 /* 606 * Use a combination of N2 counters to build the N2 portion of the 607 * transmit payload. 608 */ 609 calculate_N2(s, opcode); 610 trace_pnv_spi_log_Ncounts(s->N1_bits, s->N1_bytes, s->N1_tx, 611 s->N1_rx, s->N2_bits, s->N2_bytes, s->N2_tx, s->N2_rx); 612 /* 613 * The only difference between this code and the code for shift N1 is 614 * that this code has to account for the possible presence of N1 transmit 615 * bytes already taken from the TDR. 616 * If there are bytes to be transmitted for the N2 portion of the frame 617 * and there are still bytes in TDR that have not been copied into the 618 * TX data of the payload, this code will handle transmitting those 619 * remaining bytes. 620 * If for some reason the transmit count(s) add up to more than the size 621 * of the TDR we will just append 0xFF to the transmit payload data until 622 * the payload is N1 + N2 bytes long. 623 */ 624 n2_count = 0; 625 while (n2_count < s->N2_bytes) { 626 /* 627 * If the RDR is full and we need to RX just bail out, letting the 628 * code continue will end up building the payload twice in the same 629 * buffer since RDR full causes a sequence stop and restart. 630 */ 631 if ((s->N2_rx != 0) && 632 (GETFIELD(SPI_STS_RDR_FULL, s->status) == 1)) { 633 trace_pnv_spi_sequencer_stop_requested("shift N2 set" 634 "for receive but RDR is full"); 635 stop = true; 636 break; 637 } 638 if ((s->N2_tx != 0) && ((s->N1_tx + n2_count) < 639 PNV_SPI_REG_SIZE)) { 640 /* Always append data for the N2 segment if it is set for TX */ 641 uint8_t n2_byte = 0x00; 642 n2_byte = get_from_offset(s, (s->N1_tx + n2_count)); 643 trace_pnv_spi_tx_append("n2_byte", n2_byte, (s->N1_tx + n2_count)); 644 *(pnv_spi_xfer_buffer_write_ptr(*payload, (*payload)->len, 1)) 645 = n2_byte; 646 } else { 647 /* 648 * Regardless of whether or not N2 is set for TX or RX, we need 649 * the number of bytes in the payload to match the overall length 650 * of the operation. 651 */ 652 trace_pnv_spi_tx_append_FF("n2_byte"); 653 *(pnv_spi_xfer_buffer_write_ptr(*payload, (*payload)->len, 1)) 654 = 0xff; 655 } 656 n2_count++; 657 } /* end of while */ 658 if (!stop) { 659 /* We have a TX and a full TDR or an RX and an empty RDR */ 660 trace_pnv_spi_tx_request("Shifting N2 frame", (*payload)->len); 661 transfer(s, *payload); 662 /* 663 * If we are doing an N2 TX and the TDR is full we need to clear the 664 * TDR_full status. Do this here instead of up in the loop above so we 665 * don't log the message in every loop iteration. 666 */ 667 if ((s->N2_tx != 0) && 668 (GETFIELD(SPI_STS_TDR_FULL, s->status) == 1)) { 669 s->status = SETFIELD(SPI_STS_TDR_FULL, s->status, 0); 670 } 671 /* 672 * The N2 frame shift is complete so reset the N2 counters. 673 * Reset the N1 counters also in case the frame was a combination of 674 * N1 and N2 segments. 675 */ 676 s->N2_bits = 0; 677 s->N2_bytes = 0; 678 s->N2_tx = 0; 679 s->N2_rx = 0; 680 s->N1_bits = 0; 681 s->N1_bytes = 0; 682 s->N1_tx = 0; 683 s->N1_rx = 0; 684 pnv_spi_xfer_buffer_free(*payload); 685 *payload = NULL; 686 } 687 return stop; 688 } /* end of operation_shiftn2()*/ 689 690 static void operation_sequencer(PnvSpi *s) 691 { 692 /* 693 * Loop through each sequencer operation ID and perform the requested 694 * operations. 695 * Flag for indicating if we should send the N1 frame or wait to combine 696 * it with a preceding N2 frame. 697 */ 698 bool send_n1_alone = true; 699 bool stop = false; /* Flag to stop the sequencer */ 700 uint8_t opcode = 0; 701 uint8_t masked_opcode = 0; 702 703 /* 704 * PnvXferBuffer for containing the payload of the SPI frame. 705 * This is a static because there are cases where a sequence has to stop 706 * and wait for the target application to unload the RDR. If this occurs 707 * during a sequence where N1 is not sent alone and instead combined with 708 * N2 since the N1 tx length + the N2 tx length is less than the size of 709 * the TDR. 710 */ 711 static PnvXferBuffer *payload; 712 713 if (payload == NULL) { 714 payload = pnv_spi_xfer_buffer_new(); 715 } 716 /* 717 * Clear the sequencer FSM error bit - general_SPI_status[3] 718 * before starting a sequence. 719 */ 720 s->status = SETFIELD(SPI_STS_GEN_STATUS_B3, s->status, 0); 721 /* 722 * If the FSM is idle set the sequencer index to 0 723 * (new/restarted sequence) 724 */ 725 if (GETFIELD(SPI_STS_SEQ_FSM, s->status) == SEQ_STATE_IDLE) { 726 s->status = SETFIELD(SPI_STS_SEQ_INDEX, s->status, 0); 727 } 728 /* 729 * There are only 8 possible operation IDs to iterate through though 730 * some operations may cause more than one frame to be sequenced. 731 */ 732 while (get_seq_index(s) < NUM_SEQ_OPS) { 733 opcode = s->seq_op[get_seq_index(s)]; 734 /* Set sequencer state to decode */ 735 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_DECODE); 736 /* 737 * Only the upper nibble of the operation ID is needed to know what 738 * kind of operation is requested. 739 */ 740 masked_opcode = PNV_SPI_MASKED_OPCODE(opcode); 741 switch (masked_opcode) { 742 /* 743 * Increment the operation index in each case instead of just 744 * once at the end in case an operation like the branch 745 * operation needs to change the index. 746 */ 747 case SEQ_OP_STOP: 748 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE); 749 /* A stop operation in any position stops the sequencer */ 750 trace_pnv_spi_sequencer_op("STOP", get_seq_index(s)); 751 752 stop = true; 753 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_IDLE); 754 s->loop_counter_1 = 0; 755 s->loop_counter_2 = 0; 756 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_IDLE); 757 break; 758 759 case SEQ_OP_SELECT_SLAVE: 760 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE); 761 trace_pnv_spi_sequencer_op("SELECT_SLAVE", get_seq_index(s)); 762 /* 763 * This device currently only supports a single responder 764 * connection at position 0. De-selecting a responder is fine 765 * and expected at the end of a sequence but selecting any 766 * responder other than 0 should cause an error. 767 */ 768 s->responder_select = PNV_SPI_OPCODE_LO_NIBBLE(opcode); 769 if (s->responder_select == 0) { 770 trace_pnv_spi_shifter_done(); 771 qemu_set_irq(s->cs_line[0], 1); 772 s->status = SETFIELD(SPI_STS_SEQ_INDEX, s->status, 773 (get_seq_index(s) + 1)); 774 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_DONE); 775 } else if (s->responder_select != 1) { 776 qemu_log_mask(LOG_GUEST_ERROR, "Slave selection other than 1 " 777 "not supported, select = 0x%x\n", 778 s->responder_select); 779 trace_pnv_spi_sequencer_stop_requested("invalid " 780 "responder select"); 781 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_IDLE); 782 stop = true; 783 } else { 784 /* 785 * Only allow an FSM_START state when a responder is 786 * selected 787 */ 788 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_START); 789 trace_pnv_spi_shifter_stating(); 790 qemu_set_irq(s->cs_line[0], 0); 791 /* 792 * A Shift_N2 operation is only valid after a Shift_N1 793 * according to the spec. The spec doesn't say if that means 794 * immediately after or just after at any point. We will track 795 * the occurrence of a Shift_N1 to enforce this requirement in 796 * the most generic way possible by assuming that the rule 797 * applies once a valid responder select has occurred. 798 */ 799 s->shift_n1_done = false; 800 next_sequencer_fsm(s); 801 } 802 break; 803 804 case SEQ_OP_SHIFT_N1: 805 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE); 806 trace_pnv_spi_sequencer_op("SHIFT_N1", get_seq_index(s)); 807 /* 808 * Only allow a shift_n1 when the state is not IDLE or DONE. 809 * In either of those two cases the sequencer is not in a proper 810 * state to perform shift operations because the sequencer has: 811 * - processed a responder deselect (DONE) 812 * - processed a stop opcode (IDLE) 813 * - encountered an error (IDLE) 814 */ 815 if ((GETFIELD(SPI_STS_SHIFTER_FSM, s->status) == FSM_IDLE) || 816 (GETFIELD(SPI_STS_SHIFTER_FSM, s->status) == FSM_DONE)) { 817 qemu_log_mask(LOG_GUEST_ERROR, "Shift_N1 not allowed in " 818 "shifter state = 0x%llx", GETFIELD( 819 SPI_STS_SHIFTER_FSM, s->status)); 820 /* 821 * Set sequencer FSM error bit 3 (general_SPI_status[3]) 822 * in status reg. 823 */ 824 s->status = SETFIELD(SPI_STS_GEN_STATUS_B3, s->status, 1); 825 trace_pnv_spi_sequencer_stop_requested("invalid shifter state"); 826 stop = true; 827 } else { 828 /* 829 * Look for the special case where there is a shift_n1 set for 830 * transmit and it is followed by a shift_n2 set for transmit 831 * AND the combined transmit length of the two operations is 832 * less than or equal to the size of the TDR register. In this 833 * case we want to use both this current shift_n1 opcode and the 834 * following shift_n2 opcode to assemble the frame for 835 * transmission to the responder without requiring a refill of 836 * the TDR between the two operations. 837 */ 838 if (PNV_SPI_MASKED_OPCODE(s->seq_op[get_seq_index(s) + 1]) 839 == SEQ_OP_SHIFT_N2) { 840 send_n1_alone = false; 841 } 842 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, 843 FSM_SHIFT_N1); 844 stop = operation_shiftn1(s, opcode, &payload, send_n1_alone); 845 if (stop) { 846 /* 847 * The operation code says to stop, this can occur if: 848 * (1) RDR is full and the N1 shift is set for receive 849 * (2) TDR was empty at the time of the N1 shift so we need 850 * to wait for data. 851 * (3) Neither 1 nor 2 are occurring and we aren't sending 852 * N1 alone and N2 counter reload is set (bit 0 of the N2 853 * counter reload field). In this case TDR_underrun will 854 * will be set and the Payload has been loaded so it is 855 * ok to advance the sequencer. 856 */ 857 if (GETFIELD(SPI_STS_TDR_UNDERRUN, s->status)) { 858 s->shift_n1_done = true; 859 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, 860 FSM_SHIFT_N2); 861 s->status = SETFIELD(SPI_STS_SEQ_INDEX, s->status, 862 (get_seq_index(s) + 1)); 863 } else { 864 /* 865 * This is case (1) or (2) so the sequencer needs to 866 * wait and NOT go to the next sequence yet. 867 */ 868 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, 869 FSM_WAIT); 870 } 871 } else { 872 /* Ok to move on to the next index */ 873 s->shift_n1_done = true; 874 next_sequencer_fsm(s); 875 } 876 } 877 break; 878 879 case SEQ_OP_SHIFT_N2: 880 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE); 881 trace_pnv_spi_sequencer_op("SHIFT_N2", get_seq_index(s)); 882 if (!s->shift_n1_done) { 883 qemu_log_mask(LOG_GUEST_ERROR, "Shift_N2 is not allowed if a " 884 "Shift_N1 is not done, shifter state = 0x%llx", 885 GETFIELD(SPI_STS_SHIFTER_FSM, s->status)); 886 /* 887 * In case the sequencer actually stops if an N2 shift is 888 * requested before any N1 shift is done. Set sequencer FSM 889 * error bit 3 (general_SPI_status[3]) in status reg. 890 */ 891 s->status = SETFIELD(SPI_STS_GEN_STATUS_B3, s->status, 1); 892 trace_pnv_spi_sequencer_stop_requested("shift_n2 " 893 "w/no shift_n1 done"); 894 stop = true; 895 } else { 896 /* Ok to do a Shift_N2 */ 897 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, 898 FSM_SHIFT_N2); 899 stop = operation_shiftn2(s, opcode, &payload); 900 /* 901 * If the operation code says to stop set the shifter state to 902 * wait and stop 903 */ 904 if (stop) { 905 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, 906 FSM_WAIT); 907 } else { 908 /* Ok to move on to the next index */ 909 next_sequencer_fsm(s); 910 } 911 } 912 break; 913 914 case SEQ_OP_BRANCH_IFNEQ_RDR: 915 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE); 916 trace_pnv_spi_sequencer_op("BRANCH_IFNEQ_RDR", get_seq_index(s)); 917 /* 918 * The memory mapping register RDR match value is compared against 919 * the 16 rightmost bytes of the RDR (potentially with masking). 920 * Since this comparison is performed against the contents of the 921 * RDR then a receive must have previously occurred otherwise 922 * there is no data to compare and the operation cannot be 923 * completed and will stop the sequencer until RDR full is set to 924 * 1. 925 */ 926 if (GETFIELD(SPI_STS_RDR_FULL, s->status) == 1) { 927 bool rdr_matched = false; 928 rdr_matched = does_rdr_match(s); 929 if (rdr_matched) { 930 trace_pnv_spi_RDR_match("success"); 931 /* A match occurred, increment the sequencer index. */ 932 next_sequencer_fsm(s); 933 } else { 934 trace_pnv_spi_RDR_match("failed"); 935 /* 936 * Branch the sequencer to the index coded into the op 937 * code. 938 */ 939 s->status = SETFIELD(SPI_STS_SEQ_INDEX, s->status, 940 PNV_SPI_OPCODE_LO_NIBBLE(opcode)); 941 } 942 /* 943 * Regardless of where the branch ended up we want the 944 * sequencer to continue shifting so we have to clear 945 * RDR_full. 946 */ 947 s->status = SETFIELD(SPI_STS_RDR_FULL, s->status, 0); 948 } else { 949 trace_pnv_spi_sequencer_stop_requested("RDR not" 950 "full for 0x6x opcode"); 951 stop = true; 952 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_WAIT); 953 } 954 break; 955 956 case SEQ_OP_TRANSFER_TDR: 957 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE); 958 qemu_log_mask(LOG_GUEST_ERROR, "Transfer TDR is not supported\n"); 959 next_sequencer_fsm(s); 960 break; 961 962 case SEQ_OP_BRANCH_IFNEQ_INC_1: 963 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE); 964 trace_pnv_spi_sequencer_op("BRANCH_IFNEQ_INC_1", get_seq_index(s)); 965 /* 966 * The spec says the loop should execute count compare + 1 times. 967 * However we learned from engineering that we really only loop 968 * count_compare times, count compare = 0 makes this op code a 969 * no-op 970 */ 971 if (s->loop_counter_1 != 972 GETFIELD(SPI_CTR_CFG_CMP1, s->regs[SPI_CTR_CFG_REG])) { 973 /* 974 * Next index is the lower nibble of the branch operation ID, 975 * mask off all but the first three bits so we don't try to 976 * access beyond the sequencer_operation_reg boundary. 977 */ 978 s->status = SETFIELD(SPI_STS_SEQ_INDEX, s->status, 979 PNV_SPI_OPCODE_LO_NIBBLE(opcode)); 980 s->loop_counter_1++; 981 } else { 982 /* Continue to next index if loop counter is reached */ 983 next_sequencer_fsm(s); 984 } 985 break; 986 987 case SEQ_OP_BRANCH_IFNEQ_INC_2: 988 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE); 989 trace_pnv_spi_sequencer_op("BRANCH_IFNEQ_INC_2", get_seq_index(s)); 990 uint8_t condition2 = GETFIELD(SPI_CTR_CFG_CMP2, 991 s->regs[SPI_CTR_CFG_REG]); 992 /* 993 * The spec says the loop should execute count compare + 1 times. 994 * However we learned from engineering that we really only loop 995 * count_compare times, count compare = 0 makes this op code a 996 * no-op 997 */ 998 if (s->loop_counter_2 != condition2) { 999 /* 1000 * Next index is the lower nibble of the branch operation ID, 1001 * mask off all but the first three bits so we don't try to 1002 * access beyond the sequencer_operation_reg boundary. 1003 */ 1004 s->status = SETFIELD(SPI_STS_SEQ_INDEX, 1005 s->status, PNV_SPI_OPCODE_LO_NIBBLE(opcode)); 1006 s->loop_counter_2++; 1007 } else { 1008 /* Continue to next index if loop counter is reached */ 1009 next_sequencer_fsm(s); 1010 } 1011 break; 1012 1013 default: 1014 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_EXECUTE); 1015 /* Ignore unsupported operations. */ 1016 next_sequencer_fsm(s); 1017 break; 1018 } /* end of switch */ 1019 /* 1020 * If we used all 8 opcodes without seeing a 00 - STOP in the sequence 1021 * we need to go ahead and end things as if there was a STOP at the 1022 * end. 1023 */ 1024 if (get_seq_index(s) == NUM_SEQ_OPS) { 1025 /* All 8 opcodes completed, sequencer idling */ 1026 s->status = SETFIELD(SPI_STS_SHIFTER_FSM, s->status, FSM_IDLE); 1027 s->status = SETFIELD(SPI_STS_SEQ_INDEX, s->status, 0); 1028 s->loop_counter_1 = 0; 1029 s->loop_counter_2 = 0; 1030 s->status = SETFIELD(SPI_STS_SEQ_FSM, s->status, SEQ_STATE_IDLE); 1031 break; 1032 } 1033 /* Break the loop if a stop was requested */ 1034 if (stop) { 1035 break; 1036 } 1037 } /* end of while */ 1038 return; 1039 } /* end of operation_sequencer() */ 1040 1041 /* 1042 * The SPIC engine and its internal sequencer can be interrupted and reset by 1043 * a hardware signal, the sbe_spicst_hard_reset bits from Pervasive 1044 * Miscellaneous Register of sbe_register_bo device. 1045 * Reset immediately aborts any SPI transaction in progress and returns the 1046 * sequencer and state machines to idle state. 1047 * The configuration register values are not changed. The status register is 1048 * not reset. The engine registers are not reset. 1049 * The SPIC engine reset does not have any affect on the attached devices. 1050 * Reset handling of any attached devices is beyond the scope of the engine. 1051 */ 1052 static void do_reset(DeviceState *dev) 1053 { 1054 PnvSpi *s = PNV_SPI(dev); 1055 DeviceState *ssi_dev; 1056 1057 trace_pnv_spi_reset(); 1058 1059 /* Connect cs irq */ 1060 ssi_dev = ssi_get_cs(s->ssi_bus, 0); 1061 if (ssi_dev) { 1062 qemu_irq cs_line = qdev_get_gpio_in_named(ssi_dev, SSI_GPIO_CS, 0); 1063 qdev_connect_gpio_out_named(DEVICE(s), "cs", 0, cs_line); 1064 } 1065 1066 /* Reset all N1 and N2 counters, and other constants */ 1067 s->N2_bits = 0; 1068 s->N2_bytes = 0; 1069 s->N2_tx = 0; 1070 s->N2_rx = 0; 1071 s->N1_bits = 0; 1072 s->N1_bytes = 0; 1073 s->N1_tx = 0; 1074 s->N1_rx = 0; 1075 s->loop_counter_1 = 0; 1076 s->loop_counter_2 = 0; 1077 /* Disconnected from responder */ 1078 qemu_set_irq(s->cs_line[0], 1); 1079 } 1080 1081 static uint64_t pnv_spi_xscom_read(void *opaque, hwaddr addr, unsigned size) 1082 { 1083 PnvSpi *s = PNV_SPI(opaque); 1084 uint32_t reg = addr >> 3; 1085 uint64_t val = ~0ull; 1086 1087 switch (reg) { 1088 case ERROR_REG: 1089 case SPI_CTR_CFG_REG: 1090 case CONFIG_REG1: 1091 case SPI_CLK_CFG_REG: 1092 case SPI_MM_REG: 1093 case SPI_XMIT_DATA_REG: 1094 val = s->regs[reg]; 1095 break; 1096 case SPI_RCV_DATA_REG: 1097 val = s->regs[reg]; 1098 trace_pnv_spi_read_RDR(val); 1099 s->status = SETFIELD(SPI_STS_RDR_FULL, s->status, 0); 1100 if (GETFIELD(SPI_STS_SHIFTER_FSM, s->status) == FSM_WAIT) { 1101 trace_pnv_spi_start_sequencer(); 1102 operation_sequencer(s); 1103 } 1104 break; 1105 case SPI_SEQ_OP_REG: 1106 val = 0; 1107 for (int i = 0; i < PNV_SPI_REG_SIZE; i++) { 1108 val = (val << 8) | s->seq_op[i]; 1109 } 1110 break; 1111 case SPI_STS_REG: 1112 val = s->status; 1113 break; 1114 default: 1115 qemu_log_mask(LOG_GUEST_ERROR, "pnv_spi_regs: Invalid xscom " 1116 "read at 0x%" PRIx32 "\n", reg); 1117 } 1118 1119 trace_pnv_spi_read(addr, val); 1120 return val; 1121 } 1122 1123 static void pnv_spi_xscom_write(void *opaque, hwaddr addr, 1124 uint64_t val, unsigned size) 1125 { 1126 PnvSpi *s = PNV_SPI(opaque); 1127 uint32_t reg = addr >> 3; 1128 1129 trace_pnv_spi_write(addr, val); 1130 1131 switch (reg) { 1132 case ERROR_REG: 1133 case SPI_CTR_CFG_REG: 1134 case CONFIG_REG1: 1135 case SPI_MM_REG: 1136 case SPI_RCV_DATA_REG: 1137 s->regs[reg] = val; 1138 break; 1139 case SPI_CLK_CFG_REG: 1140 /* 1141 * To reset the SPI controller write the sequence 0x5 0xA to 1142 * reset_control field 1143 */ 1144 if ((GETFIELD(SPI_CLK_CFG_RST_CTRL, s->regs[SPI_CLK_CFG_REG]) == 0x5) 1145 && (GETFIELD(SPI_CLK_CFG_RST_CTRL, val) == 0xA)) { 1146 /* SPI controller reset sequence completed, resetting */ 1147 s->regs[reg] = SPI_CLK_CFG_HARD_RST; 1148 } else { 1149 s->regs[reg] = val; 1150 } 1151 break; 1152 case SPI_XMIT_DATA_REG: 1153 /* 1154 * Writing to the transmit data register causes the transmit data 1155 * register full status bit in the status register to be set. Writing 1156 * when the transmit data register full status bit is already set 1157 * causes a "Resource Not Available" condition. This is not possible 1158 * in the model since writes to this register are not asynchronous to 1159 * the operation sequence like it would be in hardware. 1160 */ 1161 s->regs[reg] = val; 1162 trace_pnv_spi_write_TDR(val); 1163 s->status = SETFIELD(SPI_STS_TDR_FULL, s->status, 1); 1164 s->status = SETFIELD(SPI_STS_TDR_UNDERRUN, s->status, 0); 1165 trace_pnv_spi_start_sequencer(); 1166 operation_sequencer(s); 1167 break; 1168 case SPI_SEQ_OP_REG: 1169 for (int i = 0; i < PNV_SPI_REG_SIZE; i++) { 1170 s->seq_op[i] = (val >> (56 - i * 8)) & 0xFF; 1171 } 1172 break; 1173 case SPI_STS_REG: 1174 /* other fields are ignore_write */ 1175 s->status = SETFIELD(SPI_STS_RDR_OVERRUN, s->status, 1176 GETFIELD(SPI_STS_RDR, val)); 1177 s->status = SETFIELD(SPI_STS_TDR_OVERRUN, s->status, 1178 GETFIELD(SPI_STS_TDR, val)); 1179 break; 1180 default: 1181 qemu_log_mask(LOG_GUEST_ERROR, "pnv_spi_regs: Invalid xscom " 1182 "write at 0x%" PRIx32 "\n", reg); 1183 } 1184 return; 1185 } 1186 1187 static const MemoryRegionOps pnv_spi_xscom_ops = { 1188 .read = pnv_spi_xscom_read, 1189 .write = pnv_spi_xscom_write, 1190 .valid.min_access_size = 8, 1191 .valid.max_access_size = 8, 1192 .impl.min_access_size = 8, 1193 .impl.max_access_size = 8, 1194 .endianness = DEVICE_BIG_ENDIAN, 1195 }; 1196 1197 static Property pnv_spi_properties[] = { 1198 DEFINE_PROP_UINT32("spic_num", PnvSpi, spic_num, 0), 1199 DEFINE_PROP_UINT8("transfer_len", PnvSpi, transfer_len, 4), 1200 DEFINE_PROP_END_OF_LIST(), 1201 }; 1202 1203 static void pnv_spi_realize(DeviceState *dev, Error **errp) 1204 { 1205 PnvSpi *s = PNV_SPI(dev); 1206 g_autofree char *name = g_strdup_printf(TYPE_PNV_SPI_BUS ".%d", 1207 s->spic_num); 1208 s->ssi_bus = ssi_create_bus(dev, name); 1209 s->cs_line = g_new0(qemu_irq, 1); 1210 qdev_init_gpio_out_named(DEVICE(s), s->cs_line, "cs", 1); 1211 1212 /* spi scoms */ 1213 pnv_xscom_region_init(&s->xscom_spic_regs, OBJECT(s), &pnv_spi_xscom_ops, 1214 s, "xscom-spi", PNV10_XSCOM_PIB_SPIC_SIZE); 1215 } 1216 1217 static int pnv_spi_dt_xscom(PnvXScomInterface *dev, void *fdt, 1218 int offset) 1219 { 1220 PnvSpi *s = PNV_SPI(dev); 1221 g_autofree char *name; 1222 int s_offset; 1223 const char compat[] = "ibm,power10-spi"; 1224 uint32_t spic_pcba = PNV10_XSCOM_PIB_SPIC_BASE + 1225 s->spic_num * PNV10_XSCOM_PIB_SPIC_SIZE; 1226 uint32_t reg[] = { 1227 cpu_to_be32(spic_pcba), 1228 cpu_to_be32(PNV10_XSCOM_PIB_SPIC_SIZE) 1229 }; 1230 name = g_strdup_printf("pnv_spi@%x", spic_pcba); 1231 s_offset = fdt_add_subnode(fdt, offset, name); 1232 _FDT(s_offset); 1233 1234 _FDT(fdt_setprop(fdt, s_offset, "reg", reg, sizeof(reg))); 1235 _FDT(fdt_setprop(fdt, s_offset, "compatible", compat, sizeof(compat))); 1236 _FDT((fdt_setprop_cell(fdt, s_offset, "spic_num#", s->spic_num))); 1237 return 0; 1238 } 1239 1240 static void pnv_spi_class_init(ObjectClass *klass, void *data) 1241 { 1242 DeviceClass *dc = DEVICE_CLASS(klass); 1243 PnvXScomInterfaceClass *xscomc = PNV_XSCOM_INTERFACE_CLASS(klass); 1244 1245 xscomc->dt_xscom = pnv_spi_dt_xscom; 1246 1247 dc->desc = "PowerNV SPI"; 1248 dc->realize = pnv_spi_realize; 1249 device_class_set_legacy_reset(dc, do_reset); 1250 device_class_set_props(dc, pnv_spi_properties); 1251 } 1252 1253 static const TypeInfo pnv_spi_info = { 1254 .name = TYPE_PNV_SPI, 1255 .parent = TYPE_SYS_BUS_DEVICE, 1256 .instance_size = sizeof(PnvSpi), 1257 .class_init = pnv_spi_class_init, 1258 .interfaces = (InterfaceInfo[]) { 1259 { TYPE_PNV_XSCOM_INTERFACE }, 1260 { } 1261 } 1262 }; 1263 1264 static void pnv_spi_register_types(void) 1265 { 1266 type_register_static(&pnv_spi_info); 1267 } 1268 1269 type_init(pnv_spi_register_types); 1270