1 /* 2 * QEMU sun4u IOMMU emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2012,2013 Artyom Tarasenko 6 * Copyright (c) 2017 Mark Cave-Ayland 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "hw/sysbus.h" 29 #include "hw/sparc/sun4u_iommu.h" 30 #include "exec/address-spaces.h" 31 #include "qapi/error.h" 32 #include "qemu/log.h" 33 34 /* debug IOMMU */ 35 //#define DEBUG_IOMMU 36 37 #ifdef DEBUG_IOMMU 38 #define IOMMU_DPRINTF(fmt, ...) \ 39 do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0) 40 #else 41 #define IOMMU_DPRINTF(fmt, ...) 42 #endif 43 44 45 #define IOMMU_PAGE_SIZE_8K (1ULL << 13) 46 #define IOMMU_PAGE_MASK_8K (~(IOMMU_PAGE_SIZE_8K - 1)) 47 #define IOMMU_PAGE_SIZE_64K (1ULL << 16) 48 #define IOMMU_PAGE_MASK_64K (~(IOMMU_PAGE_SIZE_64K - 1)) 49 50 #define IOMMU_CTRL 0x0 51 #define IOMMU_CTRL_TBW_SIZE (1ULL << 2) 52 #define IOMMU_CTRL_MMU_EN (1ULL) 53 54 #define IOMMU_CTRL_TSB_SHIFT 16 55 56 #define IOMMU_BASE 0x8 57 #define IOMMU_FLUSH 0x10 58 59 #define IOMMU_TTE_DATA_V (1ULL << 63) 60 #define IOMMU_TTE_DATA_SIZE (1ULL << 61) 61 #define IOMMU_TTE_DATA_W (1ULL << 1) 62 63 #define IOMMU_TTE_PHYS_MASK_8K 0x1ffffffe000ULL 64 #define IOMMU_TTE_PHYS_MASK_64K 0x1ffffff8000ULL 65 66 #define IOMMU_TSB_8K_OFFSET_MASK_8M 0x00000000007fe000ULL 67 #define IOMMU_TSB_8K_OFFSET_MASK_16M 0x0000000000ffe000ULL 68 #define IOMMU_TSB_8K_OFFSET_MASK_32M 0x0000000001ffe000ULL 69 #define IOMMU_TSB_8K_OFFSET_MASK_64M 0x0000000003ffe000ULL 70 #define IOMMU_TSB_8K_OFFSET_MASK_128M 0x0000000007ffe000ULL 71 #define IOMMU_TSB_8K_OFFSET_MASK_256M 0x000000000fffe000ULL 72 #define IOMMU_TSB_8K_OFFSET_MASK_512M 0x000000001fffe000ULL 73 #define IOMMU_TSB_8K_OFFSET_MASK_1G 0x000000003fffe000ULL 74 75 #define IOMMU_TSB_64K_OFFSET_MASK_64M 0x0000000003ff0000ULL 76 #define IOMMU_TSB_64K_OFFSET_MASK_128M 0x0000000007ff0000ULL 77 #define IOMMU_TSB_64K_OFFSET_MASK_256M 0x000000000fff0000ULL 78 #define IOMMU_TSB_64K_OFFSET_MASK_512M 0x000000001fff0000ULL 79 #define IOMMU_TSB_64K_OFFSET_MASK_1G 0x000000003fff0000ULL 80 #define IOMMU_TSB_64K_OFFSET_MASK_2G 0x000000007fff0000ULL 81 82 83 /* Called from RCU critical section */ 84 static IOMMUTLBEntry sun4u_translate_iommu(IOMMUMemoryRegion *iommu, 85 hwaddr addr, 86 IOMMUAccessFlags flag) 87 { 88 IOMMUState *is = container_of(iommu, IOMMUState, iommu); 89 hwaddr baseaddr, offset; 90 uint64_t tte; 91 uint32_t tsbsize; 92 IOMMUTLBEntry ret = { 93 .target_as = &address_space_memory, 94 .iova = 0, 95 .translated_addr = 0, 96 .addr_mask = ~(hwaddr)0, 97 .perm = IOMMU_NONE, 98 }; 99 100 if (!(is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_MMU_EN)) { 101 /* IOMMU disabled, passthrough using standard 8K page */ 102 ret.iova = addr & IOMMU_PAGE_MASK_8K; 103 ret.translated_addr = addr; 104 ret.addr_mask = IOMMU_PAGE_MASK_8K; 105 ret.perm = IOMMU_RW; 106 107 return ret; 108 } 109 110 baseaddr = is->regs[IOMMU_BASE >> 3]; 111 tsbsize = (is->regs[IOMMU_CTRL >> 3] >> IOMMU_CTRL_TSB_SHIFT) & 0x7; 112 113 if (is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_TBW_SIZE) { 114 /* 64K */ 115 switch (tsbsize) { 116 case 0: 117 offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_64M) >> 13; 118 break; 119 case 1: 120 offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_128M) >> 13; 121 break; 122 case 2: 123 offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_256M) >> 13; 124 break; 125 case 3: 126 offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_512M) >> 13; 127 break; 128 case 4: 129 offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_1G) >> 13; 130 break; 131 case 5: 132 offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_2G) >> 13; 133 break; 134 default: 135 /* Not implemented, error */ 136 return ret; 137 } 138 } else { 139 /* 8K */ 140 switch (tsbsize) { 141 case 0: 142 offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_8M) >> 10; 143 break; 144 case 1: 145 offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_16M) >> 10; 146 break; 147 case 2: 148 offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_32M) >> 10; 149 break; 150 case 3: 151 offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_64M) >> 10; 152 break; 153 case 4: 154 offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_128M) >> 10; 155 break; 156 case 5: 157 offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_256M) >> 10; 158 break; 159 case 6: 160 offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_512M) >> 10; 161 break; 162 case 7: 163 offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_1G) >> 10; 164 break; 165 } 166 } 167 168 tte = address_space_ldq_be(&address_space_memory, baseaddr + offset, 169 MEMTXATTRS_UNSPECIFIED, NULL); 170 171 if (!(tte & IOMMU_TTE_DATA_V)) { 172 /* Invalid mapping */ 173 return ret; 174 } 175 176 if (tte & IOMMU_TTE_DATA_W) { 177 /* Writeable */ 178 ret.perm = IOMMU_RW; 179 } else { 180 ret.perm = IOMMU_RO; 181 } 182 183 /* Extract phys */ 184 if (tte & IOMMU_TTE_DATA_SIZE) { 185 /* 64K */ 186 ret.iova = addr & IOMMU_PAGE_MASK_64K; 187 ret.translated_addr = tte & IOMMU_TTE_PHYS_MASK_64K; 188 ret.addr_mask = (IOMMU_PAGE_SIZE_64K - 1); 189 } else { 190 /* 8K */ 191 ret.iova = addr & IOMMU_PAGE_MASK_8K; 192 ret.translated_addr = tte & IOMMU_TTE_PHYS_MASK_8K; 193 ret.addr_mask = (IOMMU_PAGE_SIZE_8K - 1); 194 } 195 196 return ret; 197 } 198 199 static void iommu_mem_write(void *opaque, hwaddr addr, 200 uint64_t val, unsigned size) 201 { 202 IOMMUState *is = opaque; 203 204 IOMMU_DPRINTF("IOMMU config write: 0x%" HWADDR_PRIx " val: %" PRIx64 205 " size: %d\n", addr, val, size); 206 207 switch (addr) { 208 case IOMMU_CTRL: 209 if (size == 4) { 210 is->regs[IOMMU_CTRL >> 3] &= 0xffffffffULL; 211 is->regs[IOMMU_CTRL >> 3] |= val << 32; 212 } else { 213 is->regs[IOMMU_CTRL >> 3] = val; 214 } 215 break; 216 case IOMMU_CTRL + 0x4: 217 is->regs[IOMMU_CTRL >> 3] &= 0xffffffff00000000ULL; 218 is->regs[IOMMU_CTRL >> 3] |= val & 0xffffffffULL; 219 break; 220 case IOMMU_BASE: 221 if (size == 4) { 222 is->regs[IOMMU_BASE >> 3] &= 0xffffffffULL; 223 is->regs[IOMMU_BASE >> 3] |= val << 32; 224 } else { 225 is->regs[IOMMU_BASE >> 3] = val; 226 } 227 break; 228 case IOMMU_BASE + 0x4: 229 is->regs[IOMMU_BASE >> 3] &= 0xffffffff00000000ULL; 230 is->regs[IOMMU_BASE >> 3] |= val & 0xffffffffULL; 231 break; 232 case IOMMU_FLUSH: 233 case IOMMU_FLUSH + 0x4: 234 break; 235 default: 236 qemu_log_mask(LOG_UNIMP, 237 "sun4u-iommu: Unimplemented register write " 238 "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n", 239 addr, size, val); 240 break; 241 } 242 } 243 244 static uint64_t iommu_mem_read(void *opaque, hwaddr addr, unsigned size) 245 { 246 IOMMUState *is = opaque; 247 uint64_t val; 248 249 switch (addr) { 250 case IOMMU_CTRL: 251 if (size == 4) { 252 val = is->regs[IOMMU_CTRL >> 3] >> 32; 253 } else { 254 val = is->regs[IOMMU_CTRL >> 3]; 255 } 256 break; 257 case IOMMU_CTRL + 0x4: 258 val = is->regs[IOMMU_CTRL >> 3] & 0xffffffffULL; 259 break; 260 case IOMMU_BASE: 261 if (size == 4) { 262 val = is->regs[IOMMU_BASE >> 3] >> 32; 263 } else { 264 val = is->regs[IOMMU_BASE >> 3]; 265 } 266 break; 267 case IOMMU_BASE + 0x4: 268 val = is->regs[IOMMU_BASE >> 3] & 0xffffffffULL; 269 break; 270 case IOMMU_FLUSH: 271 case IOMMU_FLUSH + 0x4: 272 val = 0; 273 break; 274 default: 275 qemu_log_mask(LOG_UNIMP, 276 "sun4u-iommu: Unimplemented register read " 277 "reg 0x%" HWADDR_PRIx " size 0x%x\n", 278 addr, size); 279 val = 0; 280 break; 281 } 282 283 IOMMU_DPRINTF("IOMMU config read: 0x%" HWADDR_PRIx " val: %" PRIx64 284 " size: %d\n", addr, val, size); 285 286 return val; 287 } 288 289 static const MemoryRegionOps iommu_mem_ops = { 290 .read = iommu_mem_read, 291 .write = iommu_mem_write, 292 .endianness = DEVICE_BIG_ENDIAN, 293 }; 294 295 static void iommu_reset(DeviceState *d) 296 { 297 IOMMUState *s = SUN4U_IOMMU(d); 298 299 memset(s->regs, 0, IOMMU_NREGS * sizeof(uint64_t)); 300 } 301 302 static void iommu_init(Object *obj) 303 { 304 IOMMUState *s = SUN4U_IOMMU(obj); 305 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 306 307 memory_region_init_iommu(&s->iommu, sizeof(s->iommu), 308 TYPE_SUN4U_IOMMU_MEMORY_REGION, OBJECT(s), 309 "iommu-sun4u", UINT64_MAX); 310 address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "iommu-as"); 311 312 memory_region_init_io(&s->iomem, obj, &iommu_mem_ops, s, "iommu", 313 IOMMU_NREGS * sizeof(uint64_t)); 314 sysbus_init_mmio(sbd, &s->iomem); 315 } 316 317 static void iommu_class_init(ObjectClass *klass, void *data) 318 { 319 DeviceClass *dc = DEVICE_CLASS(klass); 320 321 dc->reset = iommu_reset; 322 } 323 324 static const TypeInfo iommu_info = { 325 .name = TYPE_SUN4U_IOMMU, 326 .parent = TYPE_SYS_BUS_DEVICE, 327 .instance_size = sizeof(IOMMUState), 328 .instance_init = iommu_init, 329 .class_init = iommu_class_init, 330 }; 331 332 static void sun4u_iommu_memory_region_class_init(ObjectClass *klass, void *data) 333 { 334 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass); 335 336 imrc->translate = sun4u_translate_iommu; 337 } 338 339 static const TypeInfo sun4u_iommu_memory_region_info = { 340 .parent = TYPE_IOMMU_MEMORY_REGION, 341 .name = TYPE_SUN4U_IOMMU_MEMORY_REGION, 342 .class_init = sun4u_iommu_memory_region_class_init, 343 }; 344 345 static void iommu_register_types(void) 346 { 347 type_register_static(&iommu_info); 348 type_register_static(&sun4u_iommu_memory_region_info); 349 } 350 351 type_init(iommu_register_types) 352